From b2a6967114b2fa9d477226ff7ad53fb55fb692bc Mon Sep 17 00:00:00 2001 From: Alessandro Decina Date: Tue, 20 Apr 2021 19:03:10 +1000 Subject: [PATCH] Add support for BPF inline assembly --- compiler/rustc_codegen_llvm/src/asm.rs | 6 + .../rustc_codegen_ssa/src/target_features.rs | 4 + compiler/rustc_span/src/symbol.rs | 2 + compiler/rustc_target/src/abi/call/mod.rs | 2 +- compiler/rustc_target/src/asm/bpf.rs | 129 ++++++++++++++++++ compiler/rustc_target/src/asm/mod.rs | 25 ++++ compiler/rustc_target/src/spec/bpf_base.rs | 1 + .../src/spec/bpfeb_unknown_none.rs | 2 +- .../src/spec/bpfel_unknown_none.rs | 2 +- .../unstable-book/src/library-features/asm.md | 6 + 10 files changed, 176 insertions(+), 3 deletions(-) create mode 100644 compiler/rustc_target/src/asm/bpf.rs diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs index 0aef77129d8..ecf62ed213d 100644 --- a/compiler/rustc_codegen_llvm/src/asm.rs +++ b/compiler/rustc_codegen_llvm/src/asm.rs @@ -288,6 +288,7 @@ fn codegen_inline_asm( InlineAsmArch::Mips | InlineAsmArch::Mips64 => {} InlineAsmArch::SpirV => {} InlineAsmArch::Wasm32 => {} + InlineAsmArch::Bpf => {} } } if !options.contains(InlineAsmOptions::NOMEM) { @@ -593,6 +594,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>) InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v", InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk", InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r", + InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r", + InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w", InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("LLVM backend does not support SPIR-V") } @@ -661,6 +664,7 @@ fn modifier_to_llvm( }, InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None, InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => None, + InlineAsmRegClass::Bpf(_) => None, InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("LLVM backend does not support SPIR-V") } @@ -708,6 +712,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll | InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(), InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(), InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(), + InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(), + InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(), InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => { bug!("LLVM backend does not support SPIR-V") } diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs index 98d550d732f..b10de567744 100644 --- a/compiler/rustc_codegen_ssa/src/target_features.rs +++ b/compiler/rustc_codegen_ssa/src/target_features.rs @@ -210,6 +210,8 @@ ("nontrapping-fptoint", Some(sym::wasm_target_feature)), ]; +const BPF_ALLOWED_FEATURES: &[(&str, Option)] = &[("alu32", Some(sym::bpf_target_feature))]; + /// When rustdoc is running, provide a list of all known features so that all their respective /// primitives may be documented. /// @@ -224,6 +226,7 @@ pub fn all_known_features() -> impl Iterator &'static [(&'static str, Opt "powerpc" | "powerpc64" => POWERPC_ALLOWED_FEATURES, "riscv32" | "riscv64" => RISCV_ALLOWED_FEATURES, "wasm32" | "wasm64" => WASM_ALLOWED_FEATURES, + "bpf" => BPF_ALLOWED_FEATURES, _ => &[], } } diff --git a/compiler/rustc_span/src/symbol.rs b/compiler/rustc_span/src/symbol.rs index 46ef308cbf2..31b425f1a79 100644 --- a/compiler/rustc_span/src/symbol.rs +++ b/compiler/rustc_span/src/symbol.rs @@ -328,6 +328,7 @@ box_free, box_patterns, box_syntax, + bpf_target_feature, braced_empty_structs, branch, breakpoint, @@ -1332,6 +1333,7 @@ wrapping_add, wrapping_mul, wrapping_sub, + wreg, write_bytes, xmm_reg, ymm_reg, diff --git a/compiler/rustc_target/src/abi/call/mod.rs b/compiler/rustc_target/src/abi/call/mod.rs index 864b4fe5f08..6e0e1403740 100644 --- a/compiler/rustc_target/src/abi/call/mod.rs +++ b/compiler/rustc_target/src/abi/call/mod.rs @@ -655,7 +655,7 @@ pub fn adjust_for_cabi(&mut self, cx: &C, abi: spec::abi::Abi) -> Result<(), } } "asmjs" => wasm::compute_c_abi_info(cx, self), - "bpfel" | "bpfeb" => bpf::compute_abi_info(self), + "bpf" => bpf::compute_abi_info(self), a => return Err(format!("unrecognized arch \"{}\" in target specification", a)), } diff --git a/compiler/rustc_target/src/asm/bpf.rs b/compiler/rustc_target/src/asm/bpf.rs new file mode 100644 index 00000000000..ecb6bdc95ce --- /dev/null +++ b/compiler/rustc_target/src/asm/bpf.rs @@ -0,0 +1,129 @@ +use super::{InlineAsmArch, InlineAsmType, Target}; +use rustc_macros::HashStable_Generic; +use std::fmt; + +def_reg_class! { + Bpf BpfInlineAsmRegClass { + reg, + wreg, + } +} + +impl BpfInlineAsmRegClass { + pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] { + &[] + } + + pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option { + None + } + + pub fn suggest_modifier( + self, + _arch: InlineAsmArch, + _ty: InlineAsmType, + ) -> Option<(char, &'static str)> { + None + } + + pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> { + None + } + + pub fn supported_types( + self, + _arch: InlineAsmArch, + ) -> &'static [(InlineAsmType, Option<&'static str>)] { + match self { + Self::reg => types! { _: I8, I16, I32, I64; }, + Self::wreg => types! { "alu32": I8, I16, I32; }, + } + } +} + +fn only_alu32( + _arch: InlineAsmArch, + mut has_feature: impl FnMut(&str) -> bool, + _target: &Target, +) -> Result<(), &'static str> { + if !has_feature("alu32") { + Err("register can't be used without the `alu32` target feature") + } else { + Ok(()) + } +} + +def_regs! { + Bpf BpfInlineAsmReg BpfInlineAsmRegClass { + r0: reg = ["r0"], + r1: reg = ["r1"], + r2: reg = ["r2"], + r3: reg = ["r3"], + r4: reg = ["r4"], + r5: reg = ["r5"], + r6: reg = ["r6"], + r7: reg = ["r7"], + r8: reg = ["r8"], + r9: reg = ["r9"], + w0: wreg = ["w0"] % only_alu32, + w1: wreg = ["w1"] % only_alu32, + w2: wreg = ["w2"] % only_alu32, + w3: wreg = ["w3"] % only_alu32, + w4: wreg = ["w4"] % only_alu32, + w5: wreg = ["w5"] % only_alu32, + w6: wreg = ["w6"] % only_alu32, + w7: wreg = ["w7"] % only_alu32, + w8: wreg = ["w8"] % only_alu32, + w9: wreg = ["w9"] % only_alu32, + + #error = ["r10", "w10"] => + "the stack pointer cannot be used as an operand for inline asm", + } +} + +impl BpfInlineAsmReg { + pub fn emit( + self, + out: &mut dyn fmt::Write, + _arch: InlineAsmArch, + _modifier: Option, + ) -> fmt::Result { + out.write_str(self.name()) + } + + pub fn overlapping_regs(self, mut cb: impl FnMut(BpfInlineAsmReg)) { + cb(self); + + macro_rules! reg_conflicts { + ( + $( + $r:ident : $w:ident + ),* + ) => { + match self { + $( + Self::$r => { + cb(Self::$w); + } + Self::$w => { + cb(Self::$r); + } + )* + } + }; + } + + reg_conflicts! { + r0 : w0, + r1 : w1, + r2 : w2, + r3 : w3, + r4 : w4, + r5 : w5, + r6 : w6, + r7 : w7, + r8 : w8, + r9 : w9 + } + } +} diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs index c17c2961434..305ea7d50e6 100644 --- a/compiler/rustc_target/src/asm/mod.rs +++ b/compiler/rustc_target/src/asm/mod.rs @@ -148,6 +148,7 @@ macro_rules! types { mod aarch64; mod arm; +mod bpf; mod hexagon; mod mips; mod nvptx; @@ -159,6 +160,7 @@ macro_rules! types { pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass}; pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass}; +pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass}; pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass}; pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass}; pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass}; @@ -184,6 +186,7 @@ pub enum InlineAsmArch { PowerPC64, SpirV, Wasm32, + Bpf, } impl FromStr for InlineAsmArch { @@ -205,6 +208,7 @@ fn from_str(s: &str) -> Result { "mips64" => Ok(Self::Mips64), "spirv" => Ok(Self::SpirV), "wasm32" => Ok(Self::Wasm32), + "bpf" => Ok(Self::Bpf), _ => Err(()), } } @@ -233,6 +237,7 @@ pub enum InlineAsmReg { Mips(MipsInlineAsmReg), SpirV(SpirVInlineAsmReg), Wasm(WasmInlineAsmReg), + Bpf(BpfInlineAsmReg), // Placeholder for invalid register constraints for the current target Err, } @@ -247,6 +252,7 @@ pub fn name(self) -> &'static str { Self::PowerPC(r) => r.name(), Self::Hexagon(r) => r.name(), Self::Mips(r) => r.name(), + Self::Bpf(r) => r.name(), Self::Err => "", } } @@ -260,6 +266,7 @@ pub fn reg_class(self) -> InlineAsmRegClass { Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()), Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()), Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()), + Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()), Self::Err => InlineAsmRegClass::Err, } } @@ -304,6 +311,9 @@ pub fn parse( InlineAsmArch::Wasm32 => { Self::Wasm(WasmInlineAsmReg::parse(arch, has_feature, target, &name)?) } + InlineAsmArch::Bpf => { + Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?) + } }) } @@ -323,6 +333,7 @@ pub fn emit( Self::PowerPC(r) => r.emit(out, arch, modifier), Self::Hexagon(r) => r.emit(out, arch, modifier), Self::Mips(r) => r.emit(out, arch, modifier), + Self::Bpf(r) => r.emit(out, arch, modifier), Self::Err => unreachable!("Use of InlineAsmReg::Err"), } } @@ -336,6 +347,7 @@ pub fn overlapping_regs(self, mut cb: impl FnMut(InlineAsmReg)) { Self::PowerPC(_) => cb(self), Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))), Self::Mips(_) => cb(self), + Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))), Self::Err => unreachable!("Use of InlineAsmReg::Err"), } } @@ -364,6 +376,7 @@ pub enum InlineAsmRegClass { Mips(MipsInlineAsmRegClass), SpirV(SpirVInlineAsmRegClass), Wasm(WasmInlineAsmRegClass), + Bpf(BpfInlineAsmRegClass), // Placeholder for invalid register constraints for the current target Err, } @@ -381,6 +394,7 @@ pub fn name(self) -> Symbol { Self::Mips(r) => r.name(), Self::SpirV(r) => r.name(), Self::Wasm(r) => r.name(), + Self::Bpf(r) => r.name(), Self::Err => rustc_span::symbol::sym::reg, } } @@ -400,6 +414,7 @@ pub fn suggest_class(self, arch: InlineAsmArch, ty: InlineAsmType) -> Option r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips), Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV), Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm), + Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -426,6 +441,7 @@ pub fn suggest_modifier( Self::Mips(r) => r.suggest_modifier(arch, ty), Self::SpirV(r) => r.suggest_modifier(arch, ty), Self::Wasm(r) => r.suggest_modifier(arch, ty), + Self::Bpf(r) => r.suggest_modifier(arch, ty), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -448,6 +464,7 @@ pub fn default_modifier(self, arch: InlineAsmArch) -> Option<(char, &'static str Self::Mips(r) => r.default_modifier(arch), Self::SpirV(r) => r.default_modifier(arch), Self::Wasm(r) => r.default_modifier(arch), + Self::Bpf(r) => r.default_modifier(arch), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -469,6 +486,7 @@ pub fn supported_types( Self::Mips(r) => r.supported_types(arch), Self::SpirV(r) => r.supported_types(arch), Self::Wasm(r) => r.supported_types(arch), + Self::Bpf(r) => r.supported_types(arch), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -493,6 +511,7 @@ pub fn parse(arch: InlineAsmArch, name: Symbol) -> Result { } InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?), InlineAsmArch::Wasm32 => Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?), + InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?), }) } @@ -510,6 +529,7 @@ pub fn valid_modifiers(self, arch: InlineAsmArch) -> &'static [char] { Self::Mips(r) => r.valid_modifiers(arch), Self::SpirV(r) => r.valid_modifiers(arch), Self::Wasm(r) => r.valid_modifiers(arch), + Self::Bpf(r) => r.valid_modifiers(arch), Self::Err => unreachable!("Use of InlineAsmRegClass::Err"), } } @@ -679,5 +699,10 @@ pub fn allocatable_registers( wasm::fill_reg_map(arch, has_feature, target, &mut map); map } + InlineAsmArch::Bpf => { + let mut map = bpf::regclass_map(); + bpf::fill_reg_map(arch, has_feature, target, &mut map); + map + } } } diff --git a/compiler/rustc_target/src/spec/bpf_base.rs b/compiler/rustc_target/src/spec/bpf_base.rs index 0853255999c..f8322567a8d 100644 --- a/compiler/rustc_target/src/spec/bpf_base.rs +++ b/compiler/rustc_target/src/spec/bpf_base.rs @@ -3,6 +3,7 @@ pub fn opts(endian: Endian) -> TargetOptions { TargetOptions { + allow_asm: true, endian, linker_flavor: LinkerFlavor::BpfLinker, atomic_cas: false, diff --git a/compiler/rustc_target/src/spec/bpfeb_unknown_none.rs b/compiler/rustc_target/src/spec/bpfeb_unknown_none.rs index cb3e4bbece4..a45da82eb40 100644 --- a/compiler/rustc_target/src/spec/bpfeb_unknown_none.rs +++ b/compiler/rustc_target/src/spec/bpfeb_unknown_none.rs @@ -6,7 +6,7 @@ pub fn target() -> Target { llvm_target: "bpfeb".to_string(), data_layout: "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128".to_string(), pointer_width: 64, - arch: "bpfeb".to_string(), + arch: "bpf".to_string(), options: bpf_base::opts(Endian::Big), } } diff --git a/compiler/rustc_target/src/spec/bpfel_unknown_none.rs b/compiler/rustc_target/src/spec/bpfel_unknown_none.rs index 92840306f89..6c9afdf35ae 100644 --- a/compiler/rustc_target/src/spec/bpfel_unknown_none.rs +++ b/compiler/rustc_target/src/spec/bpfel_unknown_none.rs @@ -6,7 +6,7 @@ pub fn target() -> Target { llvm_target: "bpfel".to_string(), data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".to_string(), pointer_width: 64, - arch: "bpfel".to_string(), + arch: "bpf".to_string(), options: bpf_base::opts(Endian::Little), } } diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md index 5503b3b4b32..77080b54dc8 100644 --- a/src/doc/unstable-book/src/library-features/asm.md +++ b/src/doc/unstable-book/src/library-features/asm.md @@ -30,6 +30,7 @@ Inline assembly is currently supported on the following architectures: - Hexagon - MIPS32r2 and MIPS64r2 - wasm32 +- BPF ## Basic usage @@ -570,6 +571,8 @@ Here is the list of currently supported register classes: | PowerPC | `reg_nonzero` | | `r[1-31]` | `b` | | PowerPC | `freg` | `f[0-31]` | `f` | | wasm32 | `local` | None\* | `r` | +| BPF | `reg` | `r[0-10]` | `r`| +| BPF | `wreg` | `w[0-10]` | `w`| > **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register. > @@ -615,6 +618,8 @@ Each register class has constraints on which value types they can be used with. | PowerPC | `reg_nonzero` | None | `i8`, `i16`, `i32` | | PowerPC | `freg` | None | `f32`, `f64` | | wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` | +| BPF | `reg` | None | `i8` `i16` `i32` `i64` | +| BPF | `wreg` | `alu32` | `i8` `i16` `i32`| > **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target). @@ -674,6 +679,7 @@ Some registers have multiple names. These are all treated by the compiler as ide | Hexagon | `r29` | `sp` | | Hexagon | `r30` | `fr` | | Hexagon | `r31` | `lr` | +| BPF | `r[0-10]` | `w[0-10]` | Some registers cannot be used for input or output operands: -- 2.44.0