Create Verilog dir & add Dita holding Verilog HDL.

(Vandread)

diff --git a/Verilog/Dita_Verilog_HDL.png b/Verilog/Dita_Verilog_HDL.png
new file mode 100644 (file)
index 0000000..bf9a49e
Binary files /dev/null and b/Verilog/Dita_Verilog_HDL.png differ