bcm64: fix usb xhci controller on pi4 8GB variant (thanks richard miller)

On the 8GB variant of the raspberry pi 4,
the eeprom chip for the xhci controller is missing and
instead loaded from sdram (by the gpu firmware).

for this, the gpu firmware needs to be notified of
the xhci controllers pci bus address (after reset)
that was assigned by our pci enumeration code.

diff --git a/sys/src/9/bcm/vcore.c b/sys/src/9/bcm/vcore.c
index 818c12a35ed4f2635cdb5403d0461db669486792..91cc7dcf99fef83981be267315e7e872db6f4783 100644 (file)
--- a/sys/src/9/bcm/vcore.c
+++ b/sys/src/9/bcm/vcore.c
@@ -53,6 +53,7 @@ enum {
        TagSetEgpioConf = 0x00038043,
 
        TagGettemp      = 0x00030006,
+       TagXhciReset    = 0x00030058,
        TagFballoc      = 0x00040001,
        TagFbfree       = 0x00048001,
        TagFbblank      = 0x00040002,
@@ -413,3 +414,19 @@ egpset(uint port, int on)
        buf[1] = on;
        vcreq(TagSetEgpioState, buf, sizeof(buf), sizeof(buf));
 }
+
+/*
+ * Notify gpu that xhci firmware might need loading. This is for some
+ * pi4 board versions which are missing the eeprom chip for the vl805,
+ * requiring its firmware to come from the boot eeprom instead.
+ */
+int
+xhcireset(int devaddr)
+{
+       u32int buf[1];
+
+       buf[0] = devaddr;
+       if(vcreq(TagXhciReset, buf, sizeof(buf), sizeof(buf[0])) == sizeof(buf[0]))
+               return buf[0];
+       return -1;
+}

diff --git a/sys/src/9/bcm64/archbcm4.c b/sys/src/9/bcm64/archbcm4.c
index 55e90d45ae0f335d699e4f35064a7976bd6d2dae..d47ba96e19030dca71ae54b456d33de08f6ef7de 100644 (file)
--- a/sys/src/9/bcm64/archbcm4.c
+++ b/sys/src/9/bcm64/archbcm4.c
@@ -172,5 +172,18 @@ wakecpu(uint cpu)
 void
 archbcm4link(void)
 {
+       Pcidev *p;
+
+       /*
+        * The firmware resets PCI before starting the host OS because
+        * without SDRAM the VL805 makes inbound requests to page-in firmware
+        * from SDRAM. If the OS has a different PCI mapping that would all break.
+        * There's no way to pause and move the mappings and it's not really desirable
+        * for the firmware to dictate the PCI configuration. Consequently, the mailbox
+        * is required so that the OS can reset the VLI after asserting PCI chip reset.
+        */
+       if((p = pcimatch(nil, 0x1106, 0x3483)) != nil)
+               xhcireset(BUSBNO(p->tbdf)<<20 | BUSDNO(p->tbdf)<<15 | BUSFNO(p->tbdf)<<12);
+
        // addclock0link(wdogfeed, HZ);
 }

diff --git a/sys/src/9/bcm64/fns.h b/sys/src/9/bcm64/fns.h
index 34cc0c812e7411170932ec2ef9eec894fb15b2a0..f42c2736ceb150b1f661bbdb3c343a72f707f2df 100644 (file)
--- a/sys/src/9/bcm64/fns.h
+++ b/sys/src/9/bcm64/fns.h
@@ -170,6 +170,7 @@ extern uint getcputemp(void);
 extern void vgpinit(void);
 extern void vgpset(uint port, int on);
 extern void egpset(uint port, int on);
+extern int xhcireset(int devaddr);
 
 /* bootargs */
 extern void bootargsinit(uintptr);

diff --git a/sys/src/9/bcm64/pi4 b/sys/src/9/bcm64/pi4
index 8d30d289dd537352c1aecc19369db5cd2c339e60..1a3b815ff5cd45ee1c32ceb3d5adc2c1777cac56 100644 (file)
--- a/sys/src/9/bcm64/pi4
+++ b/sys/src/9/bcm64/pi4
@@ -27,11 +27,11 @@ dev
 link
        gisb
        pci
-       archbcm4
+       archbcm4        pci
+       usbxhci         pci archbcm4
        ethergenet      ethermii
        ethermedium
        loopbackmedium
-       usbxhci         pci
 
 ip
        tcp