PciPMC = 0xa4,
- Nbars = 6,
Ncmd = 10,
CBIRQ = 9,
break;
default:
if(DEBUG)
- print("#Y%ld: Invalid message %s in SlotEmpty state\n",
+ print("#Y%zd: Invalid message %s in SlotEmpty state\n",
cb - cbslots, messages[message]);
break;
}
break;
default:
if(DEBUG)
- print("#Y%ld: Invalid message %s in SlotFull state\n",
+ print("#Y%zd: Invalid message %s in SlotFull state\n",
cb - cbslots, messages[message]);
break;
}
powerdown(cb);
break;
default:
- print("#Y%ld: Invalid message %s in SlotPowered state\n",
+ print("#Y%zd: Invalid message %s in SlotPowered state\n",
cb - cbslots, messages[message]);
break;
}
break;
default:
if(DEBUG)
- print("#Y%ld: Invalid message %s in SlotConfigured state\n",
+ print("#Y%zd: Invalid message %s in SlotConfigured state\n",
cb - cbslots, messages[message]);
break;
}
rdreg(cb, Rcsc); /* Ack the interrupt */
if(DEBUG)
- print("#Y%ld: interrupt: event %.8lX, state %.8lX, (%s)\n",
+ print("#Y%zd: interrupt: event %.8lX, state %.8lX, (%s)\n",
cb - cbslots, event, state, states[cb->state]);
if (event & SE_CCD) {
static int initialized;
Pcidev *pci;
int i;
- uchar intl;
char *p;
if (initialized)
/* Find all CardBus controllers */
pci = nil;
- intl = 0xff;
while ((pci = pcimatch(pci, 0, 0)) != nil) {
- uvlong baddr;
Cardbus *cb;
uchar pin;
cb->pci = pci;
cb->variant = &variant[i];
- if (pci->vid != TI_vid) {
- /*
- * Gross hack, needs a fix. Inherit the mappings from
- * 9load for the TIs (pb)
- */
- pcicfgw32(pci, PciCBMBR0, 0xffffffff);
- pcicfgw32(pci, PciCBMLR0, 0);
- pcicfgw32(pci, PciCBMBR1, 0xffffffff);
- pcicfgw32(pci, PciCBMLR1, 0);
- pcicfgw32(pci, PciCBIBR0, 0xffffffff);
- pcicfgw32(pci, PciCBILR0, 0);
- pcicfgw32(pci, PciCBIBR1, 0xffffffff);
- pcicfgw32(pci, PciCBILR1, 0);
- }
+ if(pci->mem[0].size == 0 || (pci->mem[0].bar & 0xF) != 0)
+ continue;
+ cb->regs = (ulong *)vmap(pci->mem[0].bar & ~0xFULL, pci->mem[0].size);
+ if(cb->regs == nil)
+ continue;
+
+ pcicfgw32(pci, PciCBMBR0, 0xffffffff);
+ pcicfgw32(pci, PciCBMLR0, 0);
+ pcicfgw32(pci, PciCBMBR1, 0xffffffff);
+ pcicfgw32(pci, PciCBMLR1, 0);
+ pcicfgw32(pci, PciCBIBR0, 0xffffffff);
+ pcicfgw32(pci, PciCBILR0, 0);
+ pcicfgw32(pci, PciCBIBR1, 0xffffffff);
+ pcicfgw32(pci, PciCBILR1, 0);
/* Set up PCI bus numbers if needed. */
if (pcicfgr8(pci, PciSBN) == 0) {
pcicfgw8(pci, PciINTL, pci->intl);
if (pci->intl == 0xff || pci->intl == 0)
- print("#Y%ld: No interrupt?\n", cb - cbslots);
+ print("#Y%zd: No interrupt?\n", cb - cbslots);
}
/* Don't you love standards! */
pcicfgw8(cb->pci, 0x94, 0xCA);
pcicfgw8(cb->pci, 0xD4, 0xCA);
}
-
- baddr = pcicfgr32(cb->pci, PciBAR0);
- if (baddr == 0) {
- int size = (pci->did == Ricoh_478_did)? 0x10000: 0x1000;
- baddr = upaalloc(-1ULL, size, size);
- if(baddr == -1)
- continue;
- pcicfgw32(cb->pci, PciBAR0, (ulong)baddr);
- cb->regs = (ulong *)vmap(baddr, size);
- }
- else
- cb->regs = (ulong *)vmap(baddr, 4096);
- if(cb->regs == nil)
- continue;
cb->state = SlotEmpty;
- if (intl != 0xff && intl != pci->intl)
- intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");
+ intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");
/* Don't really know what to do with this... */
i82365probe(cb, LegacyAddr, LegacyAddr + 1);
- print("#Y%ld: %s, %.8lluX intl %d\n", cb - cbslots,
- variant[i].name, baddr, pci->intl);
+ print("#Y%zd: %s, %.8lluX intl %d\n", cb - cbslots,
+ variant[i].name, pci->mem[0].bar, pci->intl);
nslots++;
}
state = cb->regs[SocketState];
if (state & SS_PC16) {
if(DEBUG)
- print("#Y%ld: Probed a PC16 card, powering up card\n",
+ print("#Y%zd: Probed a PC16 card, powering up card\n",
cb - cbslots);
cb->type = PC16;
memset(&cb->linfo, 0, sizeof(Pcminfo));
return 0;
if (state & SS_NOTCARD) {
- print("#Y%ld: No card inserted\n", cb - cbslots);
+ print("#Y%zd: No card inserted\n", cb - cbslots);
return 0;
}
if ((state & SS_3V) == 0 && (state & SS_5V) == 0) {
- print("#Y%ld: Unsupported voltage, powering down card!\n",
+ print("#Y%zd: Unsupported voltage, powering down card!\n",
cb - cbslots);
cb->regs[SocketControl] = 0;
return 0;
}
if(DEBUG)
- print("#Y%ld: card %spowered at %d volt\n", cb - cbslots,
+ print("#Y%zd: card %spowered at %d volt\n", cb - cbslots,
(state & SS_POWER)? "": "not ",
(state & SS_3V)? 3: (state & SS_5V)? 5: -1);
static void
configure(Cardbus *cb)
{
- int i, r;
Pcidev *pci;
- uvlong romlen, memlen, membase, rombase, bar;
- ulong iobase, iolen, size;
+ ulong iobase, iolen;
+ uvlong membase, memlen;
if(DEBUG)
print("configuring slot %ld (%s)\n", cb - cbslots, states[cb->state]);
}
/* Scan the CardBus for new PCI devices */
- pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge);
+ pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge, cb->pci);
- /*
- * size the devices on the bus, reserve a minimum for devices arriving later,
- * allow for ROM space, allocate space, and set the cardbus mapping registers
- */
- pcibussize(cb->pci->bridge, &memlen, &iolen); /* TO DO: need initial alignments */
-
- romlen = 0;
- for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
- size = pcibarsize(pci, PciEBAR0);
- if(size > 0){
- pci->rom.bar = -1;
- pci->rom.size = size;
- romlen += size;
- }
- }
+ /* size the devices on the bus, reserve a minimum for devices arriving later */
+ pcibussize(cb->pci->bridge, &memlen, &iolen);
if(iolen < 512)
iolen = 512;
- iobase = ioreserve(-1, iolen, 0, "cardbus");
- if(iobase == -1)
- return;
-
- rombase = memlen;
- memlen += romlen;
if(memlen < 1*1024*1024)
memlen = 1*1024*1024;
- membase = upaalloc(-1ULL, memlen, 4*1024*1024); /* TO DO: better alignment */
- if(membase == -1)
+
+ print("#Y%zd: iolen=%lud, memlen=%llud\n", cb - cbslots, iolen, memlen);
+
+ if(cb->pci->parent == nil){
+ iobase = ioreserve(-1,
+ iolen, iolen, "cardbus");
+ if(iobase == -1){
+NoIO:
+ print("#Y%zd: can't allocate io space\n", cb - cbslots);
+ return;
+ }
+ membase = upaalloc(-1ULL,
+ memlen, 4*1024*1024);
+ } else {
+ iobase = ioreservewin(cb->pci->parent->ioa.bar, cb->pci->parent->ioa.size,
+ iolen, iolen, "cardbus");
+ if(iobase == -1)
+ goto NoIO;
+ membase = upaallocwin(cb->pci->parent->mema.bar, cb->pci->parent->mema.size,
+ memlen, 4*1024*1024);
+ }
+ if(membase == -1){
+ print("#Y%zd: can't allocate memory space\n", cb - cbslots);
return;
+ }
+
+ print("#Y%zd: iobase=%lux, membase=%llux\n", cb - cbslots, iobase, membase);
pcicfgw32(cb->pci, PciCBIBR0, iobase);
pcicfgw32(cb->pci, PciCBILR0, iobase + iolen-1);
- pcicfgw32(cb->pci, PciCBIBR1, 0);
+ pcicfgw32(cb->pci, PciCBIBR1, 0xffffffff);
pcicfgw32(cb->pci, PciCBILR1, 0);
+ cb->pci->ioa.bar = iobase;
+ cb->pci->ioa.size = iolen;
pcicfgw32(cb->pci, PciCBMBR0, (ulong)membase);
pcicfgw32(cb->pci, PciCBMLR0, (ulong)membase + memlen-1);
- pcicfgw32(cb->pci, PciCBMBR1, 0);
+ pcicfgw32(cb->pci, PciCBMBR1, 0xffffffff);
pcicfgw32(cb->pci, PciCBMLR1, 0);
+ cb->pci->mema.bar = membase;
+ cb->pci->mema.size = memlen;
-// pcibussize(cb->pci->bridge, &membase, &iobase); /* now assign them */
- rombase += membase;
-
- for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
- r = pcicfgr16(pci, PciPCR);
- r &= ~(PciPCR_IO|PciPCR_MEM);
- pcicfgw16(pci, PciPCR, r);
-
- /*
- * Treat the found device as an ordinary PCI card.
- * It seems that the CIS is not always present in
- * CardBus cards.
- * XXX, need to support multifunction cards
- */
- for(i = 0; i < Nbars; i++) {
- if(pci->mem[i].size == 0)
- continue;
- bar = pci->mem[i].bar;
- if(bar & 1)
- bar += iobase;
- else
- bar += membase;
- pci->mem[i].bar = bar;
- pcicfgw32(pci, PciBAR0 + 4*i, bar);
- if((bar & 1) == 0){
- print("%T mem[%d] %8.8llux %d\n", pci->tbdf, i, bar, pci->mem[i].size);
- if(bar & 0x80){ /* TO DO: enable prefetch */
- ;
- }
- }
- }
- if((size = pcibarsize(pci, PciEBAR0)) > 0) { /* TO DO: can this be done by pci.c? */
- pci->rom.bar = rombase;
- pci->rom.size = size;
- rombase += size;
- pcicfgw32(pci, PciEBAR0, pci->rom.bar);
- }
+ /* Route interrupts to INTA#/B#, Disable prefetch for MEM0/1 */
+ pcicfgw16(cb->pci, PciBCR, pcicfgr16(cb->pci, PciBCR) & ~(7 << 7));
- /* Set the basic PCI registers for the device */
- pci->pcr = pcicfgr16(pci, PciPCR);
- pci->pcr |= PciPCR_IO|PciPCR_MEM|PciPCR_Master;
- pci->cls = 8;
- pci->ltr = 64;
- pcicfgw16(pci, PciPCR, pci->pcr);
- pcicfgw8(pci, PciCLS, pci->cls);
- pcicfgw8(pci, PciLTR, pci->ltr);
-
- if (pcicfgr8(pci, PciINTP)) {
- pci->intl = pcicfgr8(cb->pci, PciINTL);
- pcicfgw8(pci, PciINTL, pci->intl);
+ /* Assign resources */
+ pcibusmap(cb->pci->bridge, &membase, &iobase, 1);
- /* Route interrupts to INTA#/B# */
- pcicfgw16(cb->pci, PciBCR,
- pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));
+ /* Assign legacy IRQ's */
+ for(pci = cb->pci->bridge; pci != nil; pci = pci->link) {
+ if(pcicfgr8(pci, PciINTP) != 0) {
+ pci->intl = cb->pci->intl;
+ pcicfgw8(pci, PciINTL, pci->intl);
}
}
}
static void
unconfigure(Cardbus *cb)
{
- Pcidev *pci;
- int i, ioindex, memindex, r;
-
if (cb->type == PC16) {
- print("#Y%d: Don't know how to unconfigure a PC16 card\n",
- (int)(cb - cbslots));
-
+ print("#Y%zd: Don't know how to unconfigure a PC16 card\n", cb - cbslots);
memset(&cb->linfo, 0, sizeof(Pcminfo));
return;
}
- pci = cb->pci->bridge;
- if (pci == nil)
- return; /* Not configured */
- cb->pci->bridge = nil;
+ pcicfgw32(cb->pci, PciCBIBR0, 0xffffffff);
+ pcicfgw32(cb->pci, PciCBILR0, 0);
+ pcicfgw32(cb->pci, PciCBIBR1, 0xffffffff);
+ pcicfgw32(cb->pci, PciCBILR1, 0);
- memindex = ioindex = 0;
- while (pci) {
- Pcidev *_pci;
+ pcicfgw32(cb->pci, PciCBMBR0, 0xffffffff);
+ pcicfgw32(cb->pci, PciCBMLR0, 0);
+ pcicfgw32(cb->pci, PciCBMBR1, 0xffffffff);
+ pcicfgw32(cb->pci, PciCBMLR1, 0);
- for (i = 0; i != Nbars; i++) {
- if (pci->mem[i].size == 0)
- continue;
- if (pci->mem[i].bar & 1) {
+ /* free i/o space */
+ if(cb->pci->ioa.size){
+ Pcidev *pci;
+ int i;
+
+ for(pci = cb->pci->bridge; pci != nil; pci = pci->link) {
+ for(i = 0; i < nelem(pci->mem); i++) {
+ if((pci->mem[i].size == 0)
+ || (pci->mem[i].bar & 1) == 0
+ || (pci->mem[i].bar & ~3) == 0)
+ continue;
iofree(pci->mem[i].bar & ~3);
- pcicfgw16(cb->pci, PciCBIBR0 + ioindex * 8,
- (ushort)-1);
- pcicfgw16(cb->pci, PciCBILR0 + ioindex * 8, 0);
- ioindex++;
- continue;
}
-
- upafree(pci->mem[i].bar & ~0xF, pci->mem[i].size);
- pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1);
- pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0);
- r = pcicfgr16(cb->pci, PciBCR);
- r &= ~(1 << (8 + memindex));
- pcicfgw16(cb->pci, PciBCR, r);
- memindex++;
- }
-
- if (pci->rom.bar && memindex < 2) {
- upafree(pci->rom.bar & ~0xF, pci->rom.size);
- pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1);
- pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0);
- memindex++;
}
+ iofree(cb->pci->ioa.bar);
+ cb->pci->ioa.bar = 0;
+ cb->pci->ioa.size = 0;
+ }
- _pci = pci->list;
- free(_pci);
- pci = _pci;
+ /* free memory space */
+ if(cb->pci->mema.size){
+ upafree(cb->pci->mema.bar, cb->pci->mema.size);
+ cb->pci->mema.bar = 0;
+ cb->pci->mema.size = 0;
}
+
+ /* remove the devices */
+ while(cb->pci->bridge != nil)
+ pcidevfree(cb->pci->bridge);
}
static void
pi->irq = isa->irq;
unlock(cb);
- print("#Y%ld: %s irq %d, port %lluX\n", cb - cbslots, pi->verstr, isa->irq, isa->port);
+ print("#Y%zd: %s irq %d, port %lluX\n", cb - cbslots, pi->verstr, isa->irq, isa->port);
return (int)(cb - cbslots);
}
Pcidev *pci = cb->pci->bridge;
int i;
- while (pci) {
+ while (pci != nil) {
p = seprint(p, e, "%.4uX %.4uX; irq %d\n",
pci->vid, pci->did, pci->intl);
- for (i = 0; i != Nbars; i++)
+ for (i = 0; i < nelem(pci->mem); i++)
if (pci->mem[i].size)
p = seprint(p, e,
"\tmem[%d] %.8ullX (%.8uX)\n",
if (pci->rom.size)
p = seprint(p, e, "\tROM %.8ullX (%.8uX)\n",
pci->rom.bar, pci->rom.size);
- pci = pci->list;
+ pci = pci->link;
}
}
break;
int pcimaxdno;
static Lock pcicfglock;
-static Pcidev* pcilist;
-static Pcidev* pcitail;
+static Pcidev *pcilist, **pcitail;
static char* bustypes[] = {
"CBUSI",
}
}
+static Pcidev*
+pcidevalloc(void)
+{
+ Pcidev *p;
+
+ p = xalloc(sizeof(*p));
+ if(p == nil)
+ panic("pci: no memory for Pcidev");
+ return p;
+}
+
+void
+pcidevfree(Pcidev *p)
+{
+ Pcidev **l;
+
+ if(p == nil)
+ return;
+
+ while(p->bridge != nil)
+ pcidevfree(p->bridge);
+
+ if(p->parent != nil){
+ for(l = &p->parent->bridge; *l != nil; l = &(*l)->link) {
+ if(*l == p) {
+ *l = p->link;
+ break;
+ }
+ }
+ }
+ for(l = &pcilist; *l != nil; l = &(*l)->list) {
+ if(*l == p) {
+ if((*l = p->list) == nil)
+ pcitail = l;
+ break;
+ }
+ }
+ /* leaked */
+}
+
int
pcicfgr8(Pcidev* p, int rno)
{
pcicfgrw32(p->tbdf, rno, v, 0);
iunlock(&pcicfglock);
- if(v & 1){
+ if(rno == PciEBAR0 || rno == PciEBAR1){
+ size &= ~0x7FF;
+ } else if(v & 1){
size = (short)size;
size &= ~3;
} else {
size &= ~0xF;
}
+
return -size;
}
ntb++;
ntb *= (PciCIS-PciBAR0)/4;
- table = malloc(2*ntb*sizeof(Pcisiz));
+ table = malloc((2*ntb+1)*sizeof(Pcisiz));
if(table == nil)
panic("pcibusmap: can't allocate memory");
itb = table;
*/
for(p = root; p != nil; p = p->link) {
if(p->ccrb == 0x06) {
+ /* carbus bridge? */
+ if(p->ccru == 0x07){
+ if(pcicfgr32(p, PciBAR0) & 1)
+ continue;
+ size = pcibarsize(p, PciBAR0);
+ if(size == 0)
+ continue;
+ mtb->dev = p;
+ mtb->bar = 0;
+ mtb->siz = size;
+ mtb->typ = 0;
+ mtb++;
+ continue;
+ }
+
+ /* pci bridge? */
if(p->ccru != 0x04 || p->bridge == nil)
continue;
mtb->siz = hole;
mtb->typ = 0;
mtb++;
+
+ size = pcibarsize(p, PciEBAR1);
+ if(size != 0){
+ mtb->dev = p;
+ mtb->bar = -3;
+ mtb->siz = size;
+ mtb->typ = 0;
+ mtb++;
+ }
continue;
}
+ size = pcibarsize(p, PciEBAR0);
+ if(size != 0){
+ mtb->dev = p;
+ mtb->bar = -2;
+ mtb->siz = size;
+ mtb->typ = 0;
+ mtb++;
+ }
+
for(i = 0; i < nelem(p->mem); i++) {
rno = PciBAR0 + i*4;
v = pcicfgr32(p, rno);
if(tptr->bar == -1) {
p->mema.bar = mema;
p->mema.size = tptr->siz;
+ } else if(tptr->bar == -2) {
+ p->rom.bar = mema|1;
+ p->rom.size = tptr->siz;
+ pcisetbar(p, PciEBAR0, p->rom.bar);
+ } else if(tptr->bar == -3) {
+ p->rom.bar = mema|1;
+ p->rom.size = tptr->siz;
+ pcisetbar(p, PciEBAR1, p->rom.bar);
} else {
p->mem[tptr->bar].size = tptr->siz;
p->mem[tptr->bar].bar = mema|tptr->typ;
}
}
-static int
-pcilscan(int bno, Pcidev** list, Pcidev *parent)
+int
+pciscan(int bno, Pcidev** list, Pcidev *parent)
{
- Pcidev *p, *head, *tail;
+ Pcidev *p, *head, **tail;
int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
maxubn = bno;
if(l == 0xFFFFFFFF || l == 0)
continue;
- p = malloc(sizeof(*p));
- if(p == nil)
- panic("pcilscan: can't allocate memory");
+ p = pcidevalloc();
p->tbdf = tbdf;
p->vid = l;
p->did = l>>16;
- if(pcilist != nil)
- pcitail->list = p;
- else
- pcilist = p;
- pcitail = p;
-
p->pcr = pcicfgr16(p, PciPCR);
p->rid = pcicfgr8(p, PciRID);
p->ccrp = pcicfgr8(p, PciCCRp);
}
rno += 4;
}
+
+ p->rom.bar = (ulong)pcicfgr32(p, PciEBAR0);
+ p->rom.size = pcibarsize(p, PciEBAR0);
break;
- case 0x05: /* memory controller */
case 0x06: /* bridge device */
+ /* cardbus bridge? */
+ if(p->ccru == 0x07){
+ p->mem[0].bar = (ulong)pcicfgr32(p, PciBAR0);
+ p->mem[0].size = pcibarsize(p, PciBAR0);
+ break;
+ }
+
+ /* pci bridge? */
+ if(p->ccru != 0x04)
+ break;
+
+ p->rom.bar = (ulong)pcicfgr32(p, PciEBAR1);
+ p->rom.size = pcibarsize(p, PciEBAR1);
+ break;
+ case 0x05: /* memory controller */
default:
break;
}
p->parent = parent;
if(head != nil)
- tail->link = p;
+ *tail = p;
else
head = p;
- tail = p;
+ tail = &p->link;
+
+ if(pcilist != nil)
+ *pcitail = p;
+ else
+ pcilist = p;
+ pcitail = &p->list;
}
}
if(p->ccru == 0x04)
break;
default:
+ /* check and clear invalid membars for non bridges */
for(i = 0; i < nelem(p->mem); i++) {
if(p->mem[i].size == 0)
continue;
pcisetbar(p, PciBAR0 + i*4, p->mem[i].bar);
}
}
+ if(p->rom.size) {
+ if((p->rom.bar & 1) == 0
+ || !pcivalidbar(p, p->rom.bar & ~0x7FFUL, p->rom.size)){
+ p->rom.bar = 0;
+ pcisetbar(p, PciEBAR0, p->rom.bar);
+ }
+ }
continue;
}
+ if(p->rom.size) {
+ if((p->rom.bar & 1) == 0
+ || !pcivalidbar(p, p->rom.bar & ~0x7FFULL, p->rom.size)){
+ p->rom.bar = 0;
+ pcisetbar(p, PciEBAR1, p->rom.bar);
+ }
+ }
+
/*
* If the secondary or subordinate bus number is not
* initialised try to do what the PCI BIOS should have
pcisetwin(p, 0xFFF00000|0, 0);
pcisetwin(p, 0xFFF00000|8, 0);
- maxubn = pcilscan(sbn, &p->bridge, p);
+ maxubn = pciscan(sbn, &p->bridge, p);
l = (maxubn<<16)|(sbn<<8)|bno;
pcicfgw32(p, PciPBN, l);
if(ubn > maxubn)
maxubn = ubn;
- pcilscan(sbn, &p->bridge, p);
+ pciscan(sbn, &p->bridge, p);
}
}
return maxubn;
}
-int
-pciscan(int bno, Pcidev **list)
-{
- return pcilscan(bno, list, nil);
-}
-
void
pcibussize(Pcidev *root, uvlong *msize, ulong *iosize)
{
continue;
print("%d:%.8llux %d ", i, t->mem[i].bar, t->mem[i].size);
}
+ if(t->rom.bar || t->rom.size)
+ print("rom:%.8llux %d ", t->rom.bar, t->rom.size);
if(t->ioa.bar || t->ioa.size)
print("ioa:%.8llux-%.8llux %d ", t->ioa.bar, t->ioa.bar+t->ioa.size, t->ioa.size);
if(t->mema.bar || t->mema.size)
projects / plan9front.git / commitdiff