Add missing vendor intrinsics

diff --git a/src/base.rs b/src/base.rs
index 4ce5cdaccd3a183f405bf1f571aae14dd552260e..d88fe9bca2ac5ef070eec64ed76852746508713b 100644 (file)
--- a/src/base.rs
+++ b/src/base.rs
@@ -79,7 +79,10 @@ fn module_codegen(tcx: TyCtxt<'_>, (cgu_name, supports_128bit_integers): (Symbol
         // TODO(antoyo): only set on x86 platforms.
         context.add_command_line_option("-masm=intel");
         // TODO(antoyo): only add the following cli argument if the feature is supported.
+        context.add_command_line_option("-msse2");
         context.add_command_line_option("-mavx2");
+        context.add_command_line_option("-msha");
+        context.add_command_line_option("-mpclmul");
         // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU.
         // Only add if the CPU supports it.
         //context.add_command_line_option("-mavx512f");

diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs
index 1a2a352b5a3bd9642d50984a30ee93e034b7dc2c..7634c649bc34327dd5c6fe7ee2b3ed90fc8e2aca 100644 (file)
--- a/src/intrinsic/llvm.rs
+++ b/src/intrinsic/llvm.rs
@@ -16,6 +16,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
             "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256",
             "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256",
             "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256",
+            "llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128",
             "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper",
             "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256",
             "llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256",
@@ -28,6 +29,11 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
             "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256",
             "llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256",
             "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128",
+            "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128",
+            "llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi",
+            "llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi",
+            "llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si",
+            "llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di",
             "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256",
             "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256",
             "llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256",
@@ -113,6 +119,14 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
             "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di",
             "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di",
             "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss",
+            "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128",
+            "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1",
+            "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2",
+            "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte",
+            "llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4",
+            "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1",
+            "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2",
+            "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2",
 
             "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd",
             _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),