Merge commit 'e8dca3e87d164d2806098c462c6ce41301341f68' into sync_from_cg_gcc

diff --git a/compiler/rustc_codegen_gcc/.github/workflows/ci.yml b/compiler/rustc_codegen_gcc/.github/workflows/ci.yml
index 337837c40bfb86eb03fcb00a01b576af1156116d..8ebdabe82610ec65cf17e62fdd709281e327b6ae 100644 (file)
--- a/compiler/rustc_codegen_gcc/.github/workflows/ci.yml
+++ b/compiler/rustc_codegen_gcc/.github/workflows/ci.yml
@@ -11,7 +11,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        libgccjit_version: ["libgccjit.so", "libgccjit_without_int128.so"]
+        libgccjit_version: ["libgccjit.so", "libgccjit_without_int128.so", "libgccjit12.so"]
 
     steps:
     - uses: actions/checkout@v2
@@ -78,12 +78,21 @@ jobs:
         key: ${{ runner.os }}-cargo-build-target-${{ hashFiles('rust-toolchain') }}
 
     - name: Build
+      if: matrix.libgccjit_version != 'libgccjit12.so'
       run: |
         ./prepare_build.sh
         ./build.sh
         cargo test
         ./clean_all.sh
 
+    - name: Build
+      if: matrix.libgccjit_version == 'libgccjit12.so'
+      run: |
+        ./prepare_build.sh
+        ./build.sh --no-default-features
+        cargo test --no-default-features
+        ./clean_all.sh
+
     - name: Prepare dependencies
       run: |
         git config --global user.email "user@example.com"
@@ -98,6 +107,7 @@ jobs:
         args: --release
 
     - name: Test
+      if: matrix.libgccjit_version != 'libgccjit12.so'
       run: |
         # Enable backtraces for easier debugging
         export RUST_BACKTRACE=1
@@ -107,3 +117,15 @@ jobs:
         export RUN_RUNS=2
 
         ./test.sh --release
+
+    - name: Test
+      if: matrix.libgccjit_version == 'libgccjit12.so'
+      run: |
+        # Enable backtraces for easier debugging
+        export RUST_BACKTRACE=1
+
+        # Reduce amount of benchmark runs as they are slow
+        export COMPILE_RUNS=2
+        export RUN_RUNS=2
+
+        ./test.sh --release --no-default-features

diff --git a/compiler/rustc_codegen_gcc/.gitignore b/compiler/rustc_codegen_gcc/.gitignore
index efda74b2633aedb0f50449b1500e9cd0f46ed0f9..12ed56675639c8525feef60ef9bec1d04ef5b824 100644 (file)
--- a/compiler/rustc_codegen_gcc/.gitignore
+++ b/compiler/rustc_codegen_gcc/.gitignore
@@ -13,9 +13,13 @@ perf.data.old
 /rust
 /simple-raytracer
 /regex
+/rand
 gimple*
 *asm
 res
 test-backend
 gcc_path
 benchmarks
+tools/llvm-project
+tools/llvmint
+tools/llvmint-2

diff --git a/compiler/rustc_codegen_gcc/.rustfmt.toml b/compiler/rustc_codegen_gcc/.rustfmt.toml
new file mode 100644 (file)
index 0000000..c7ad93b
--- /dev/null
+++ b/compiler/rustc_codegen_gcc/.rustfmt.toml
@@ -0,0 +1 @@
+disable_all_formatting = true

diff --git a/compiler/rustc_codegen_gcc/Cargo.lock b/compiler/rustc_codegen_gcc/Cargo.lock
index a1d9f2f5e3822a813641c02e93d869e4e028aa19..6df2102470fe680daa1495b97cc47badc53d8619 100644 (file)
--- a/compiler/rustc_codegen_gcc/Cargo.lock
+++ b/compiler/rustc_codegen_gcc/Cargo.lock
@@ -41,7 +41,7 @@ dependencies = [
 [[package]]
 name = "gccjit"
 version = "1.0.0"
-source = "git+https://github.com/antoyo/gccjit.rs#bdecdecfb8a02ec861a39a350f990faa33bd31c3"
+source = "git+https://github.com/antoyo/gccjit.rs#bdb86fb5092895ff5589726b33250010c64d93f6"
 dependencies = [
  "gccjit_sys",
 ]
@@ -49,7 +49,7 @@ dependencies = [
 [[package]]
 name = "gccjit_sys"
 version = "0.0.1"
-source = "git+https://github.com/antoyo/gccjit.rs#bdecdecfb8a02ec861a39a350f990faa33bd31c3"
+source = "git+https://github.com/antoyo/gccjit.rs#bdb86fb5092895ff5589726b33250010c64d93f6"
 dependencies = [
  "libc 0.1.12",
 ]

diff --git a/compiler/rustc_codegen_gcc/Cargo.toml b/compiler/rustc_codegen_gcc/Cargo.toml
index 21f0bfbf69d7fac441bccb879999fbc80bd801b5..211d19a8dc8909546bac8558553d2f8ca5c9959c 100644 (file)
--- a/compiler/rustc_codegen_gcc/Cargo.toml
+++ b/compiler/rustc_codegen_gcc/Cargo.toml
@@ -9,9 +9,17 @@ license = "MIT OR Apache-2.0"
 crate-type = ["dylib"]
 
 [[test]]
-name = "lang_tests"
-path = "tests/lib.rs"
+name = "lang_tests_debug"
+path = "tests/lang_tests_debug.rs"
 harness = false
+[[test]]
+name = "lang_tests_release"
+path = "tests/lang_tests_release.rs"
+harness = false
+
+[features]
+default = ["master"]
+master = ["gccjit/master"]
 
 [dependencies]
 gccjit = { git = "https://github.com/antoyo/gccjit.rs" }

diff --git a/compiler/rustc_codegen_gcc/build.sh b/compiler/rustc_codegen_gcc/build.sh
index 230ab7b6d42baf42715936bb3805c8e71ef4eb8b..ba0d0d04948aa3e5f8e789c6507171b3266f2959 100755 (executable)
--- a/compiler/rustc_codegen_gcc/build.sh
+++ b/compiler/rustc_codegen_gcc/build.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 #set -x
 set -e
@@ -6,6 +6,8 @@ set -e
 codegen_channel=debug
 sysroot_channel=debug
 
+flags=
+
 while [[ $# -gt 0 ]]; do
     case $1 in
         --release)
@@ -16,6 +18,15 @@ while [[ $# -gt 0 ]]; do
             sysroot_channel=release
             shift
             ;;
+        --no-default-features)
+            flags="$flags --no-default-features"
+            shift
+            ;;
+        --features)
+            shift
+            flags="$flags --features $1"
+            shift
+            ;;
         *)
             echo "Unknown option $1"
             exit 1
@@ -33,21 +44,13 @@ fi
 export LD_LIBRARY_PATH="$GCC_PATH"
 export LIBRARY_PATH="$GCC_PATH"
 
-features=
-
-if [[ "$1" == "--features" ]]; then
-    shift
-    features="--features $1"
-    shift
-fi
-
 if [[ "$codegen_channel" == "release" ]]; then
     export CHANNEL='release'
-    CARGO_INCREMENTAL=1 cargo rustc --release $features
+    CARGO_INCREMENTAL=1 cargo rustc --release $flags
 else
     echo $LD_LIBRARY_PATH
     export CHANNEL='debug'
-    cargo rustc $features
+    cargo rustc $flags
 fi
 
 source config.sh

diff --git a/compiler/rustc_codegen_gcc/build_sysroot/build_sysroot.sh b/compiler/rustc_codegen_gcc/build_sysroot/build_sysroot.sh
index a965ca971a07d362635049c8a40a138800d20a60..f293192a099de8062cebbaae4c55653d5f587ae5 100755 (executable)
--- a/compiler/rustc_codegen_gcc/build_sysroot/build_sysroot.sh
+++ b/compiler/rustc_codegen_gcc/build_sysroot/build_sysroot.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 # Requires the CHANNEL env var to be set to `debug` or `release.`
 

diff --git a/compiler/rustc_codegen_gcc/build_sysroot/prepare_sysroot_src.sh b/compiler/rustc_codegen_gcc/build_sysroot/prepare_sysroot_src.sh
index 071e7ed1f85df465dabe68bf1ee3e0216d2f424d..56768bbf1d0150431f913ad65462ff509f101eea 100755 (executable)
--- a/compiler/rustc_codegen_gcc/build_sysroot/prepare_sysroot_src.sh
+++ b/compiler/rustc_codegen_gcc/build_sysroot/prepare_sysroot_src.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 cd $(dirname "$0")
 

diff --git a/compiler/rustc_codegen_gcc/cargo.sh b/compiler/rustc_codegen_gcc/cargo.sh
index 332f365ce0ceed7cc0cf71fc6c08f51b3e69f4fa..16e49b20423c6f2a49ab2109d82eab660b1bbf5b 100755 (executable)
--- a/compiler/rustc_codegen_gcc/cargo.sh
+++ b/compiler/rustc_codegen_gcc/cargo.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 if [ -z $CHANNEL ]; then
 export CHANNEL='debug'
@@ -20,4 +20,4 @@ fi
 cmd=$1
 shift
 
-RUSTDOCFLAGS="$RUSTFLAGS" cargo +${TOOLCHAIN} $cmd --target $TARGET_TRIPLE $@
+RUSTDOCFLAGS="$RUSTFLAGS" cargo +${TOOLCHAIN} $cmd $@

diff --git a/compiler/rustc_codegen_gcc/clean_all.sh b/compiler/rustc_codegen_gcc/clean_all.sh
index a77d1486fe283f8a22819fc58b5e7edb3863fb7d..782bd3e5058c430929a49dbf107cfd3768864339 100755 (executable)
--- a/compiler/rustc_codegen_gcc/clean_all.sh
+++ b/compiler/rustc_codegen_gcc/clean_all.sh
@@ -1,5 +1,6 @@
-#!/bin/bash --verbose
+#!/usr/bin/env bash
 set -e
+set -v
 
 rm -rf target/ build_sysroot/{sysroot/,sysroot_src/,target/,Cargo.lock} perf.data{,.old}
 rm -rf regex/ simple-raytracer/

diff --git a/compiler/rustc_codegen_gcc/config.sh b/compiler/rustc_codegen_gcc/config.sh
index a932c1c8372b488dc479bbba4d8fd85f864d14f5..b25e215fb9ee9053c473e6fdfdeb7d63c57e5822 100644 (file)
--- a/compiler/rustc_codegen_gcc/config.sh
+++ b/compiler/rustc_codegen_gcc/config.sh
@@ -2,7 +2,7 @@ set -e
 
 export CARGO_INCREMENTAL=0
 
-if [ -f ./gcc_path ]; then 
+if [ -f ./gcc_path ]; then
     export GCC_PATH=$(cat gcc_path)
 else
     echo 'Please put the path to your custom build of libgccjit in the file `gcc_path`, see Readme.md for details'
@@ -38,7 +38,7 @@ if [[ "$HOST_TRIPLE" != "$TARGET_TRIPLE" ]]; then
    fi
 fi
 
-export RUSTFLAGS="$linker -Cpanic=abort -Csymbol-mangling-version=v0 -Cdebuginfo=2 -Clto=off -Zpanic-abort-tests -Zcodegen-backend=$(pwd)/target/${CHANNEL:-debug}/librustc_codegen_gcc.$dylib_ext --sysroot $(pwd)/build_sysroot/sysroot"
+export RUSTFLAGS="$CG_RUSTFLAGS $linker -Cpanic=abort -Csymbol-mangling-version=v0 -Cdebuginfo=2 -Clto=off -Zpanic-abort-tests -Zcodegen-backend=$(pwd)/target/${CHANNEL:-debug}/librustc_codegen_gcc.$dylib_ext --sysroot $(pwd)/build_sysroot/sysroot"
 
 # FIXME(antoyo): remove once the atomic shim is gone
 if [[ `uname` == 'Darwin' ]]; then

diff --git a/compiler/rustc_codegen_gcc/crate_patches/0002-rand-Disable-failing-test.patch b/compiler/rustc_codegen_gcc/crate_patches/0002-rand-Disable-failing-test.patch
new file mode 100644 (file)
index 0000000..449ca5f
--- /dev/null
+++ b/compiler/rustc_codegen_gcc/crate_patches/0002-rand-Disable-failing-test.patch
@@ -0,0 +1,32 @@
+From a8fb97120d71252538b6b026695df40d02696bdb Mon Sep 17 00:00:00 2001
+From: bjorn3 <bjorn3@users.noreply.github.com>
+Date: Sat, 15 Aug 2020 20:04:38 +0200
+Subject: [PATCH] [rand] Disable failing test
+
+---
+ src/distributions/uniform.rs | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/src/distributions/uniform.rs b/src/distributions/uniform.rs
+index 480b859..c80bb6f 100644
+--- a/src/distributions/uniform.rs
++++ b/src/distributions/uniform.rs
+@@ -1085,7 +1085,7 @@ mod tests {
+             _ => panic!("`UniformDurationMode` was not serialized/deserialized correctly")
+         }
+     }
+-    
++
+     #[test]
+     #[cfg(feature = "serde1")]
+     fn test_uniform_serialization() {
+@@ -1314,6 +1314,7 @@ mod tests {
+         not(target_arch = "wasm32"),
+         not(target_arch = "asmjs")
+     ))]
++    #[ignore] // FIXME
+     fn test_float_assertions() {
+         use super::SampleUniform;
+         use std::panic::catch_unwind;
+-- 
+2.20.1

diff --git a/compiler/rustc_codegen_gcc/example/std_example.rs b/compiler/rustc_codegen_gcc/example/std_example.rs
index eba0eb82896004c7168823ec909530aa7967aee4..31069058aea3417e668cc2f6c407af00dd68ef58 100644 (file)
--- a/compiler/rustc_codegen_gcc/example/std_example.rs
+++ b/compiler/rustc_codegen_gcc/example/std_example.rs
@@ -93,9 +93,10 @@ fn main() {
 
     println!("{:?}", std::intrinsics::caller_location());
 
-    /*unsafe {
+    #[cfg(feature="master")]
+    unsafe {
         test_simd();
-    }*/
+    }
 
     Box::pin(move |mut _task_context| {
         yield ();
@@ -104,7 +105,8 @@ fn main() {
     println!("End");
 }
 
-/*#[target_feature(enable = "sse2")]
+#[cfg(feature="master")]
+#[target_feature(enable = "sse2")]
 unsafe fn test_simd() {
     let x = _mm_setzero_si128();
     let y = _mm_set1_epi16(7);
@@ -112,7 +114,7 @@ unsafe fn test_simd() {
     let cmp_eq = _mm_cmpeq_epi8(y, y);
     let cmp_lt = _mm_cmplt_epi8(y, y);
 
-    /*assert_eq!(std::mem::transmute::<_, [u16; 8]>(or), [7, 7, 7, 7, 7, 7, 7, 7]);
+    assert_eq!(std::mem::transmute::<_, [u16; 8]>(or), [7, 7, 7, 7, 7, 7, 7, 7]);
     assert_eq!(std::mem::transmute::<_, [u16; 8]>(cmp_eq), [0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff]);
     assert_eq!(std::mem::transmute::<_, [u16; 8]>(cmp_lt), [0, 0, 0, 0, 0, 0, 0, 0]);
 
@@ -124,14 +126,15 @@ unsafe fn test_simd() {
     test_mm_cvtepi8_epi16();
     test_mm_cvtsi128_si64();
 
-    // FIXME(#666) implement `#[rustc_arg_required_const(..)]` support
-    //test_mm_extract_epi8();
+    test_mm_extract_epi8();
+    test_mm_insert_epi16();
 
     let mask1 = _mm_movemask_epi8(dbg!(_mm_setr_epi8(255u8 as i8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)));
-    assert_eq!(mask1, 1);*/
-}*/
+    assert_eq!(mask1, 1);
+}
 
-/*#[target_feature(enable = "sse2")]
+#[cfg(feature="master")]
+#[target_feature(enable = "sse2")]
 unsafe fn test_mm_slli_si128() {
     #[rustfmt::skip]
     let a = _mm_setr_epi8(
@@ -155,22 +158,10 @@ unsafe fn test_mm_slli_si128() {
     );
     let r = _mm_slli_si128(a, 16);
     assert_eq_m128i(r, _mm_set1_epi8(0));
-
-    #[rustfmt::skip]
-    let a = _mm_setr_epi8(
-        1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
-    );
-    let r = _mm_slli_si128(a, -1);
-    assert_eq_m128i(_mm_set1_epi8(0), r);
-
-    #[rustfmt::skip]
-    let a = _mm_setr_epi8(
-        1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
-    );
-    let r = _mm_slli_si128(a, -0x80000000);
-    assert_eq_m128i(r, _mm_set1_epi8(0));
 }
 
+
+#[cfg(feature="master")]
 #[target_feature(enable = "sse2")]
 unsafe fn test_mm_movemask_epi8() {
     #[rustfmt::skip]
@@ -184,6 +175,7 @@ unsafe fn test_mm_movemask_epi8() {
     assert_eq!(r, 0b10100100_00100101);
 }
 
+#[cfg(feature="master")]
 #[target_feature(enable = "avx2")]
 unsafe fn test_mm256_movemask_epi8() {
     let a = _mm256_set1_epi8(-1);
@@ -192,6 +184,7 @@ unsafe fn test_mm256_movemask_epi8() {
     assert_eq!(r, e);
 }
 
+#[cfg(feature="master")]
 #[target_feature(enable = "sse2")]
 unsafe fn test_mm_add_epi8() {
     let a = _mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
@@ -207,6 +200,7 @@ unsafe fn test_mm_add_epi8() {
     assert_eq_m128i(r, e);
 }
 
+#[cfg(feature="master")]
 #[target_feature(enable = "sse2")]
 unsafe fn test_mm_add_pd() {
     let a = _mm_setr_pd(1.0, 2.0);
@@ -215,12 +209,14 @@ unsafe fn test_mm_add_pd() {
     assert_eq_m128d(r, _mm_setr_pd(6.0, 12.0));
 }
 
+#[cfg(feature="master")]
 fn assert_eq_m128i(x: std::arch::x86_64::__m128i, y: std::arch::x86_64::__m128i) {
     unsafe {
         assert_eq!(std::mem::transmute::<_, [u8; 16]>(x), std::mem::transmute::<_, [u8; 16]>(y));
     }
 }
 
+#[cfg(feature="master")]
 #[target_feature(enable = "sse2")]
 pub unsafe fn assert_eq_m128d(a: __m128d, b: __m128d) {
     if _mm_movemask_pd(_mm_cmpeq_pd(a, b)) != 0b11 {
@@ -228,12 +224,14 @@ pub unsafe fn assert_eq_m128d(a: __m128d, b: __m128d) {
     }
 }
 
+#[cfg(feature="master")]
 #[target_feature(enable = "sse2")]
 unsafe fn test_mm_cvtsi128_si64() {
     let r = _mm_cvtsi128_si64(std::mem::transmute::<[i64; 2], _>([5, 0]));
     assert_eq!(r, 5);
 }
 
+#[cfg(feature="master")]
 #[target_feature(enable = "sse4.1")]
 unsafe fn test_mm_cvtepi8_epi16() {
     let a = _mm_set1_epi8(10);
@@ -246,6 +244,7 @@ unsafe fn test_mm_cvtepi8_epi16() {
     assert_eq_m128i(r, e);
 }
 
+#[cfg(feature="master")]
 #[target_feature(enable = "sse4.1")]
 unsafe fn test_mm_extract_epi8() {
     #[rustfmt::skip]
@@ -254,10 +253,19 @@ unsafe fn test_mm_extract_epi8() {
         8, 9, 10, 11, 12, 13, 14, 15
     );
     let r1 = _mm_extract_epi8(a, 0);
-    let r2 = _mm_extract_epi8(a, 19);
+    let r2 = _mm_extract_epi8(a, 3);
     assert_eq!(r1, 0xFF);
     assert_eq!(r2, 3);
-}*/
+}
+
+#[cfg(all(feature="master", target_arch = "x86_64"))]
+#[target_feature(enable = "sse2")]
+unsafe fn test_mm_insert_epi16() {
+    let a = _mm_setr_epi16(0, 1, 2, 3, 4, 5, 6, 7);
+    let r = _mm_insert_epi16(a, 9, 0);
+    let e = _mm_setr_epi16(9, 1, 2, 3, 4, 5, 6, 7);
+    assert_eq_m128i(r, e);
+}
 
 #[derive(PartialEq)]
 enum LoopState {

diff --git a/compiler/rustc_codegen_gcc/patches/0024-core-Disable-portable-simd-test.patch b/compiler/rustc_codegen_gcc/patches/0024-core-Disable-portable-simd-test.patch
index 03900ba101a900b67f484827b237a9842449a9cc..d5fa1cec061dd6f9d441246bb8bec4bc61186f6f 100644 (file)
--- a/compiler/rustc_codegen_gcc/patches/0024-core-Disable-portable-simd-test.patch
+++ b/compiler/rustc_codegen_gcc/patches/0024-core-Disable-portable-simd-test.patch
@@ -7,167 +7,6 @@ Subject: [PATCH] [core] Disable portable-simd test
  library/core/tests/lib.rs | 1 -
  1 file changed, 1 deletion(-)
 
-diff --git a/library/core/src/lib.rs b/library/core/src/lib.rs
-index aa1ad93..95fbf55 100644
---- a/library/core/src/lib.rs
-+++ b/library/core/src/lib.rs
-@@ -398,23 +398,4 @@ pub mod arch {
-     }
- }
- 
--// Pull in the `core_simd` crate directly into libcore. The contents of
--// `core_simd` are in a different repository: rust-lang/portable-simd.
--//
--// `core_simd` depends on libcore, but the contents of this module are
--// set up in such a way that directly pulling it here works such that the
--// crate uses this crate as its libcore.
--#[path = "../../portable-simd/crates/core_simd/src/mod.rs"]
--#[allow(missing_debug_implementations, dead_code, unsafe_op_in_unsafe_fn, unused_unsafe)]
--#[allow(rustdoc::bare_urls)]
--#[unstable(feature = "portable_simd", issue = "86656")]
--mod core_simd;
--
--#[doc = include_str!("../../portable-simd/crates/core_simd/src/core_simd_docs.md")]
--#[unstable(feature = "portable_simd", issue = "86656")]
--pub mod simd {
--    #[unstable(feature = "portable_simd", issue = "86656")]
--    pub use crate::core_simd::simd::*;
--}
--
- include!("primitive_docs.rs");
-diff --git a/library/core/src/slice/mod.rs b/library/core/src/slice/mod.rs
-index cd38c3a..ad632dc 100644
---- a/library/core/src/slice/mod.rs
-+++ b/library/core/src/slice/mod.rs
-@@ -17,6 +17,5 @@ use crate::ptr;
- use crate::result::Result;
- use crate::result::Result::{Err, Ok};
--use crate::simd::{self, Simd};
- use crate::slice;
- 
- #[unstable(
-@@ -3475,121 +3474,6 @@ impl<T> [T] {
-         }
-     }
- 
--    /// Split a slice into a prefix, a middle of aligned SIMD types, and a suffix.
--    ///
--    /// This is a safe wrapper around [`slice::align_to`], so has the same weak
--    /// postconditions as that method.  You're only assured that
--    /// `self.len() == prefix.len() + middle.len() * LANES + suffix.len()`.
--    ///
--    /// Notably, all of the following are possible:
--    /// - `prefix.len() >= LANES`.
--    /// - `middle.is_empty()` despite `self.len() >= 3 * LANES`.
--    /// - `suffix.len() >= LANES`.
--    ///
--    /// That said, this is a safe method, so if you're only writing safe code,
--    /// then this can at most cause incorrect logic, not unsoundness.
--    ///
--    /// # Panics
--    ///
--    /// This will panic if the size of the SIMD type is different from
--    /// `LANES` times that of the scalar.
--    ///
--    /// At the time of writing, the trait restrictions on `Simd<T, LANES>` keeps
--    /// that from ever happening, as only power-of-two numbers of lanes are
--    /// supported.  It's possible that, in the future, those restrictions might
--    /// be lifted in a way that would make it possible to see panics from this
--    /// method for something like `LANES == 3`.
--    ///
--    /// # Examples
--    ///
--    /// ```
--    /// #![feature(portable_simd)]
--    ///
--    /// let short = &[1, 2, 3];
--    /// let (prefix, middle, suffix) = short.as_simd::<4>();
--    /// assert_eq!(middle, []); // Not enough elements for anything in the middle
--    ///
--    /// // They might be split in any possible way between prefix and suffix
--    /// let it = prefix.iter().chain(suffix).copied();
--    /// assert_eq!(it.collect::<Vec<_>>(), vec![1, 2, 3]);
--    ///
--    /// fn basic_simd_sum(x: &[f32]) -> f32 {
--    ///     use std::ops::Add;
--    ///     use std::simd::f32x4;
--    ///     let (prefix, middle, suffix) = x.as_simd();
--    ///     let sums = f32x4::from_array([
--    ///         prefix.iter().copied().sum(),
--    ///         0.0,
--    ///         0.0,
--    ///         suffix.iter().copied().sum(),
--    ///     ]);
--    ///     let sums = middle.iter().copied().fold(sums, f32x4::add);
--    ///     sums.reduce_sum()
--    /// }
--    ///
--    /// let numbers: Vec<f32> = (1..101).map(|x| x as _).collect();
--    /// assert_eq!(basic_simd_sum(&numbers[1..99]), 4949.0);
--    /// ```
--    #[unstable(feature = "portable_simd", issue = "86656")]
--    pub fn as_simd<const LANES: usize>(&self) -> (&[T], &[Simd<T, LANES>], &[T])
--    where
--        Simd<T, LANES>: AsRef<[T; LANES]>,
--        T: simd::SimdElement,
--        simd::LaneCount<LANES>: simd::SupportedLaneCount,
--    {
--        // These are expected to always match, as vector types are laid out like
--        // arrays per <https://llvm.org/docs/LangRef.html#vector-type>, but we
--        // might as well double-check since it'll optimize away anyhow.
--        assert_eq!(mem::size_of::<Simd<T, LANES>>(), mem::size_of::<[T; LANES]>());
--
--        // SAFETY: The simd types have the same layout as arrays, just with
--        // potentially-higher alignment, so the de-facto transmutes are sound.
--        unsafe { self.align_to() }
--    }
--
--    /// Split a slice into a prefix, a middle of aligned SIMD types, and a suffix.
--    ///
--    /// This is a safe wrapper around [`slice::align_to_mut`], so has the same weak
--    /// postconditions as that method.  You're only assured that
--    /// `self.len() == prefix.len() + middle.len() * LANES + suffix.len()`.
--    ///
--    /// Notably, all of the following are possible:
--    /// - `prefix.len() >= LANES`.
--    /// - `middle.is_empty()` despite `self.len() >= 3 * LANES`.
--    /// - `suffix.len() >= LANES`.
--    ///
--    /// That said, this is a safe method, so if you're only writing safe code,
--    /// then this can at most cause incorrect logic, not unsoundness.
--    ///
--    /// This is the mutable version of [`slice::as_simd`]; see that for examples.
--    ///
--    /// # Panics
--    ///
--    /// This will panic if the size of the SIMD type is different from
--    /// `LANES` times that of the scalar.
--    ///
--    /// At the time of writing, the trait restrictions on `Simd<T, LANES>` keeps
--    /// that from ever happening, as only power-of-two numbers of lanes are
--    /// supported.  It's possible that, in the future, those restrictions might
--    /// be lifted in a way that would make it possible to see panics from this
--    /// method for something like `LANES == 3`.
--    #[unstable(feature = "portable_simd", issue = "86656")]
--    pub fn as_simd_mut<const LANES: usize>(&mut self) -> (&mut [T], &mut [Simd<T, LANES>], &mut [T])
--    where
--        Simd<T, LANES>: AsMut<[T; LANES]>,
--        T: simd::SimdElement,
--        simd::LaneCount<LANES>: simd::SupportedLaneCount,
--    {
--        // These are expected to always match, as vector types are laid out like
--        // arrays per <https://llvm.org/docs/LangRef.html#vector-type>, but we
--        // might as well double-check since it'll optimize away anyhow.
--        assert_eq!(mem::size_of::<Simd<T, LANES>>(), mem::size_of::<[T; LANES]>());
--
--        // SAFETY: The simd types have the same layout as arrays, just with
--        // potentially-higher alignment, so the de-facto transmutes are sound.
--        unsafe { self.align_to_mut() }
--    }
--
-     /// Checks if the elements of this slice are sorted.
-     ///
-     /// That is, for each element `a` and its following element `b`, `a <= b` must hold. If the
 diff --git a/library/core/tests/lib.rs b/library/core/tests/lib.rs
 index 06c7be0..359e2e7 100644
 --- a/library/core/tests/lib.rs
@@ -188,41 +27,3 @@ index 06c7be0..359e2e7 100644
  mod slice;
  mod str;
  mod str_lossy;
-diff --git a/library/std/src/lib.rs b/library/std/src/lib.rs
-index 5dc586d..b6fc48f 100644
---- a/library/std/src/lib.rs
-+++ b/library/std/src/lib.rs
-@@ -312,6 +312,5 @@
- #![feature(panic_can_unwind)]
- #![feature(panic_unwind)]
- #![feature(platform_intrinsics)]
--#![feature(portable_simd)]
- #![feature(prelude_import)]
- #![feature(ptr_as_uninit)]
-@@ -508,23 +508,6 @@ pub mod time;
- #[unstable(feature = "once_cell", issue = "74465")]
- pub mod lazy;
- 
--// Pull in `std_float` crate  into libstd. The contents of
--// `std_float` are in a different repository: rust-lang/portable-simd.
--#[path = "../../portable-simd/crates/std_float/src/lib.rs"]
--#[allow(missing_debug_implementations, dead_code, unsafe_op_in_unsafe_fn, unused_unsafe)]
--#[allow(rustdoc::bare_urls)]
--#[unstable(feature = "portable_simd", issue = "86656")]
--mod std_float;
--
--#[doc = include_str!("../../portable-simd/crates/core_simd/src/core_simd_docs.md")]
--#[unstable(feature = "portable_simd", issue = "86656")]
--pub mod simd {
--    #[doc(inline)]
--    pub use crate::std_float::StdFloat;
--    #[doc(inline)]
--    pub use core::simd::*;
--}
--
- #[stable(feature = "futures_api", since = "1.36.0")]
- pub mod task {
-     //! Types and Traits for working with asynchronous tasks.
---
-2.26.2.7.g19db9cfb68
-

diff --git a/compiler/rustc_codegen_gcc/prepare.sh b/compiler/rustc_codegen_gcc/prepare.sh
index 503fa29b36269e451959d79f73faa2512c8040d6..e98f24c6e128db563f211db128a00e08e623ebbc 100755 (executable)
--- a/compiler/rustc_codegen_gcc/prepare.sh
+++ b/compiler/rustc_codegen_gcc/prepare.sh
@@ -1,10 +1,18 @@
-#!/bin/bash --verbose
+#!/usr/bin/env bash
 set -e
+set -v
 
 source prepare_build.sh
 
 cargo install hyperfine || echo "Skipping hyperfine install"
 
+git clone https://github.com/rust-random/rand.git || echo "rust-random/rand has already been cloned"
+pushd rand
+git checkout -- .
+git checkout 0f933f9c7176e53b2a3c7952ded484e1783f0bf1
+git am ../crate_patches/*-rand-*.patch
+popd
+
 git clone https://github.com/rust-lang/regex.git || echo "rust-lang/regex has already been cloned"
 pushd regex
 git checkout -- .

diff --git a/compiler/rustc_codegen_gcc/prepare_build.sh b/compiler/rustc_codegen_gcc/prepare_build.sh
index 3896775a0b9d27045c0dee3754bbade61027f28e..8194360da4bae4c6deffa35025af13075e7801dc 100755 (executable)
--- a/compiler/rustc_codegen_gcc/prepare_build.sh
+++ b/compiler/rustc_codegen_gcc/prepare_build.sh
@@ -1,4 +1,5 @@
-#!/bin/bash --verbose
+#!/usr/bin/env bash
 set -e
+set -v
 
 ./build_sysroot/prepare_sysroot_src.sh

diff --git a/compiler/rustc_codegen_gcc/rust-toolchain b/compiler/rustc_codegen_gcc/rust-toolchain
index db14ea2bebca557044f875a723bdae0fb54cd56e..b20aeb979ad78d5b17e00157b514974b8de5bc3f 100644 (file)
--- a/compiler/rustc_codegen_gcc/rust-toolchain
+++ b/compiler/rustc_codegen_gcc/rust-toolchain
@@ -1,3 +1,3 @@
 [toolchain]
-channel = "nightly-2022-03-26"
+channel = "nightly-2022-06-06"
 components = ["rust-src", "rustc-dev", "llvm-tools-preview"]

diff --git a/compiler/rustc_codegen_gcc/rustc_patches/compile_test.patch b/compiler/rustc_codegen_gcc/rustc_patches/compile_test.patch
new file mode 100644 (file)
index 0000000..59143ea
--- /dev/null
+++ b/compiler/rustc_codegen_gcc/rustc_patches/compile_test.patch
@@ -0,0 +1,14 @@
+diff --git a/src/tools/compiletest/src/header.rs b/src/tools/compiletest/src/header.rs
+index 887d27fd6dca4..2c2239f2b83d1 100644
+--- a/src/tools/compiletest/src/header.rs
++++ b/src/tools/compiletest/src/header.rs
+@@ -806,8 +806,8 @@ pub fn make_test_description<R: Read>(
+     cfg: Option<&str>,
+ ) -> test::TestDesc {
+     let mut ignore = false;
+     #[cfg(not(bootstrap))]
+-    let ignore_message: Option<String> = None;
++    let ignore_message: Option<&str> = None;
+     let mut should_fail = false;
+
+     let rustc_has_profiler_support = env::var_os("RUSTC_PROFILER_SUPPORT").is_some();

diff --git a/compiler/rustc_codegen_gcc/rustup.sh b/compiler/rustc_codegen_gcc/rustup.sh
index 11d39a122f559fbf7575f4dcd5fc1ca16ecf130d..041079bc9c6f79a9cd305dd7190fb0f5bd8b8001 100755 (executable)
--- a/compiler/rustc_codegen_gcc/rustup.sh
+++ b/compiler/rustc_codegen_gcc/rustup.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 set -e
 

diff --git a/compiler/rustc_codegen_gcc/src/asm.rs b/compiler/rustc_codegen_gcc/src/asm.rs
index 20d91b80e8c52821904c449c572e2fa681225c8c..52fd66af0659d624384ed5a924521d9d771658b9 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/asm.rs
+++ b/compiler/rustc_codegen_gcc/src/asm.rs
@@ -13,6 +13,7 @@
 use crate::builder::Builder;
 use crate::context::CodegenCx;
 use crate::type_of::LayoutGccExt;
+use crate::callee::get_fn;
 
 
 // Rust asm! and GCC Extended Asm semantics differ substantially.
@@ -116,7 +117,6 @@ fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_opera
         let asm_arch = self.tcx.sess.asm_arch.unwrap();
         let is_x86 = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64);
         let att_dialect = is_x86 && options.contains(InlineAsmOptions::ATT_SYNTAX);
-        let intel_dialect = is_x86 && !options.contains(InlineAsmOptions::ATT_SYNTAX);
 
         // GCC index of an output operand equals its position in the array
         let mut outputs = vec![];
@@ -348,9 +348,24 @@ fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_opera
                     // processed in the previous pass
                 }
 
-                InlineAsmOperandRef::Const { .. }
-                | InlineAsmOperandRef::SymFn { .. }
-                | InlineAsmOperandRef::SymStatic { .. } => {
+                InlineAsmOperandRef::SymFn { instance } => {
+                    inputs.push(AsmInOperand {
+                        constraint: "X".into(),
+                        rust_idx,
+                        val: self.cx.rvalue_as_function(get_fn(self.cx, instance))
+                            .get_address(None),
+                    });
+                }
+
+                InlineAsmOperandRef::SymStatic { def_id } => {
+                    inputs.push(AsmInOperand {
+                        constraint: "X".into(),
+                        rust_idx,
+                        val: self.cx.get_static(def_id).get_address(None),
+                    });
+                }
+
+                InlineAsmOperandRef::Const { .. } => {
                     // processed in the previous pass
                 }
             }
@@ -359,7 +374,7 @@ fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_opera
         // 3. Build the template string
 
         let mut template_str = String::with_capacity(estimate_template_length(template, constants_len, att_dialect));
-        if !intel_dialect {
+        if att_dialect {
             template_str.push_str(ATT_SYNTAX_INS);
         }
 
@@ -444,7 +459,7 @@ fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], rust_opera
             }
         }
 
-        if !intel_dialect {
+        if att_dialect {
             template_str.push_str(INTEL_SYNTAX_INS);
         }
 
@@ -588,7 +603,7 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
             InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
             | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",
             InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
-            InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => unimplemented!(),
+            InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "Yk",
             InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg0) => unimplemented!(),
             InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => unimplemented!(),
             InlineAsmRegClass::X86(
@@ -672,8 +687,8 @@ fn codegen_global_asm(&self, template: &[InlineAsmTemplatePiece], operands: &[Gl
         let asm_arch = self.tcx.sess.asm_arch.unwrap();
 
         // Default to Intel syntax on x86
-        let intel_syntax = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64)
-            && !options.contains(InlineAsmOptions::ATT_SYNTAX);
+        let att_dialect = matches!(asm_arch, InlineAsmArch::X86 | InlineAsmArch::X86_64)
+            && options.contains(InlineAsmOptions::ATT_SYNTAX);
 
         // Build the template string
         let mut template_str = String::new();
@@ -723,11 +738,11 @@ fn codegen_global_asm(&self, template: &[InlineAsmTemplatePiece], operands: &[Gl
         }
 
         let template_str =
-            if intel_syntax {
-                format!("{}\n\t.intel_syntax noprefix", template_str)
+            if att_dialect {
+                format!(".att_syntax\n\t{}\n\t.intel_syntax noprefix", template_str)
             }
             else {
-                format!(".att_syntax\n\t{}\n\t.intel_syntax noprefix", template_str)
+                template_str
             };
         // NOTE: seems like gcc will put the asm in the wrong section, so set it to .text manually.
         let template_str = format!(".pushsection .text\n{}\n.popsection", template_str);

diff --git a/compiler/rustc_codegen_gcc/src/base.rs b/compiler/rustc_codegen_gcc/src/base.rs
index f5aca35cdcbc4e3bc90398e76af00ed514bbfe07..e4ecbd46f0c428c2657ac3fcf55681f390eea023 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/base.rs
+++ b/compiler/rustc_codegen_gcc/src/base.rs
@@ -78,9 +78,19 @@ fn module_codegen(tcx: TyCtxt<'_>, (cgu_name, supports_128bit_integers): (Symbol
         let context = Context::default();
         // TODO(antoyo): only set on x86 platforms.
         context.add_command_line_option("-masm=intel");
+        // TODO(antoyo): only add the following cli argument if the feature is supported.
+        context.add_command_line_option("-msse2");
+        context.add_command_line_option("-mavx2");
+        context.add_command_line_option("-msha");
+        context.add_command_line_option("-mpclmul");
+        // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU.
+        // Only add if the CPU supports it.
+        //context.add_command_line_option("-mavx512f");
         for arg in &tcx.sess.opts.cg.llvm_args {
             context.add_command_line_option(arg);
         }
+        // NOTE: This is needed to compile the file src/intrinsic/archs.rs during a bootstrap of rustc.
+        context.add_command_line_option("-fno-var-tracking-assignments");
         // NOTE: an optimization (https://github.com/rust-lang/rustc_codegen_gcc/issues/53).
         context.add_command_line_option("-fno-semantic-interposition");
         // NOTE: Rust relies on LLVM not doing TBAA (https://github.com/rust-lang/unsafe-code-guidelines/issues/292).

diff --git a/compiler/rustc_codegen_gcc/src/builder.rs b/compiler/rustc_codegen_gcc/src/builder.rs
index 479328a557cfaf8a4b3b836c447f5ce70706bb43..fa490fe3f222ebdd8801020d150036e714ed2227 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/builder.rs
+++ b/compiler/rustc_codegen_gcc/src/builder.rs
@@ -3,11 +3,11 @@
 use std::convert::TryFrom;
 use std::ops::Deref;
 
-use gccjit::FunctionType;
 use gccjit::{
     BinaryOp,
     Block,
     ComparisonOp,
+    Context,
     Function,
     LValue,
     RValue,
@@ -48,6 +48,7 @@
 
 use crate::common::{SignType, TypeReflection, type_is_pointer};
 use crate::context::CodegenCx;
+use crate::intrinsic::llvm;
 use crate::type_of::LayoutGccExt;
 
 // TODO(antoyo)
@@ -199,17 +200,28 @@ fn check_ptr_call<'b>(&mut self, _typ: &str, func_ptr: RValue<'gcc>, args: &'b [
             return Cow::Borrowed(args);
         }
 
+        let func_name = format!("{:?}", func_ptr);
+
         let casted_args: Vec<_> = param_types
             .into_iter()
             .zip(args.iter())
             .enumerate()
             .map(|(index, (expected_ty, &actual_val))| {
+                if llvm::ignore_arg_cast(&func_name, index, args.len()) {
+                    return actual_val;
+                }
+
                 let actual_ty = actual_val.get_type();
                 if expected_ty != actual_ty {
-                    if on_stack_param_indices.contains(&index) {
+                    if !actual_ty.is_vector() && !expected_ty.is_vector() && actual_ty.is_integral() && expected_ty.is_integral() && actual_ty.get_size() != expected_ty.get_size() {
+                        self.context.new_cast(None, actual_val, expected_ty)
+                    }
+                    else if on_stack_param_indices.contains(&index) {
                         actual_val.dereference(None).to_rvalue()
                     }
                     else {
+                        assert!(!((actual_ty.is_vector() && !expected_ty.is_vector()) || (!actual_ty.is_vector() && expected_ty.is_vector())), "{:?} ({}) -> {:?} ({}), index: {:?}[{}]", actual_ty, actual_ty.is_vector(), expected_ty, expected_ty.is_vector(), func_ptr, index);
+                        // TODO(antoyo): perhaps use __builtin_convertvector for vector casting.
                         self.bitcast(actual_val, expected_ty)
                     }
                 }
@@ -268,22 +280,20 @@ fn function_ptr_call(&mut self, func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _
         // gccjit requires to use the result of functions, even when it's not used.
         // That's why we assign the result to a local or call add_eval().
         let gcc_func = func_ptr.get_type().dyncast_function_ptr_type().expect("function ptr");
-        let mut return_type = gcc_func.get_return_type();
+        let return_type = gcc_func.get_return_type();
         let void_type = self.context.new_type::<()>();
         let current_func = self.block.get_function();
 
-        // FIXME(antoyo): As a temporary workaround for unsupported LLVM intrinsics.
-        if gcc_func.get_param_count() == 0 && format!("{:?}", func_ptr) == "__builtin_ia32_pmovmskb128" {
-            return_type = self.int_type;
-        }
-
         if return_type != void_type {
             unsafe { RETURN_VALUE_COUNT += 1 };
             let result = current_func.new_local(None, return_type, &format!("ptrReturnValue{}", unsafe { RETURN_VALUE_COUNT }));
+            let func_name = format!("{:?}", func_ptr);
+            let args = llvm::adjust_intrinsic_arguments(&self, gcc_func, args, &func_name);
             self.block.add_assignment(None, result, self.cx.context.new_call_through_ptr(None, func_ptr, &args));
             result.to_rvalue()
         }
         else {
+            #[cfg(not(feature="master"))]
             if gcc_func.get_param_count() == 0 {
                 // FIXME(antoyo): As a temporary workaround for unsupported LLVM intrinsics.
                 self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &[]));
@@ -291,6 +301,8 @@ fn function_ptr_call(&mut self, func_ptr: RValue<'gcc>, args: &[RValue<'gcc>], _
             else {
                 self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &args));
             }
+            #[cfg(feature="master")]
+            self.block.add_eval(None, self.cx.context.new_call_through_ptr(None, func_ptr, &args));
             // Return dummy value when not having return value.
             let result = current_func.new_local(None, self.isize_type, "dummyValueThatShouldNeverBeUsed");
             self.block.add_assignment(None, result, self.context.new_rvalue_from_long(self.isize_type, 0));
@@ -480,8 +492,11 @@ fn udiv(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> {
     }
 
     fn exactudiv(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> {
-        // TODO(antoyo): convert the arguments to unsigned?
         // TODO(antoyo): poison if not exact.
+        let a_type = a.get_type().to_unsigned(self);
+        let a = self.gcc_int_cast(a, a_type);
+        let b_type = b.get_type().to_unsigned(self);
+        let b = self.gcc_int_cast(b, b_type);
         a / b
     }
 
@@ -511,12 +526,12 @@ fn srem(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> {
     }
 
     fn frem(&mut self, a: RValue<'gcc>, b: RValue<'gcc>) -> RValue<'gcc> {
-        if a.get_type() == self.cx.float_type {
+        if a.get_type().is_compatible_with(self.cx.float_type) {
             let fmodf = self.context.get_builtin_function("fmodf");
             // FIXME(antoyo): this seems to produce the wrong result.
             return self.context.new_call(None, fmodf, &[a, b]);
         }
-        assert_eq!(a.get_type(), self.cx.double_type);
+        assert_eq!(a.get_type().unqualified(), self.cx.double_type);
 
         let fmod = self.context.get_builtin_function("fmod");
         return self.context.new_call(None, fmod, &[a, b]);
@@ -632,18 +647,17 @@ fn array_alloca(&mut self, _ty: Type<'gcc>, _len: RValue<'gcc>, _align: Align) -
         unimplemented!();
     }
 
-    fn load(&mut self, _ty: Type<'gcc>, ptr: RValue<'gcc>, _align: Align) -> RValue<'gcc> {
-        // TODO(antoyo): use ty.
+    fn load(&mut self, pointee_ty: Type<'gcc>, ptr: RValue<'gcc>, _align: Align) -> RValue<'gcc> {
         let block = self.llbb();
         let function = block.get_function();
         // NOTE: instead of returning the dereference here, we have to assign it to a variable in
         // the current basic block. Otherwise, it could be used in another basic block, causing a
         // dereference after a drop, for instance.
-        // TODO(antoyo): handle align.
+        // TODO(antoyo): handle align of the load instruction.
+        let ptr = self.context.new_cast(None, ptr, pointee_ty.make_pointer());
         let deref = ptr.dereference(None).to_rvalue();
-        let value_type = deref.get_type();
         unsafe { RETURN_VALUE_COUNT += 1 };
-        let loaded_value = function.new_local(None, value_type, &format!("loadedValue{}", unsafe { RETURN_VALUE_COUNT }));
+        let loaded_value = function.new_local(None, pointee_ty, &format!("loadedValue{}", unsafe { RETURN_VALUE_COUNT }));
         block.add_assignment(None, loaded_value, deref);
         loaded_value.to_rvalue()
     }
@@ -695,7 +709,11 @@ fn scalar_load_metadata<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, load:
                 OperandValue::Ref(place.llval, Some(llextra), place.align)
             }
             else if place.layout.is_gcc_immediate() {
-                let load = self.load(place.llval.get_type(), place.llval, place.align);
+                let load = self.load(
+                    place.layout.gcc_type(self, false),
+                    place.llval,
+                    place.align,
+                );
                 if let abi::Abi::Scalar(ref scalar) = place.layout.abi {
                     scalar_load_metadata(self, load, scalar);
                 }
@@ -707,7 +725,8 @@ fn scalar_load_metadata<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, load:
 
                 let mut load = |i, scalar: &abi::Scalar, align| {
                     let llptr = self.struct_gep(pair_type, place.llval, i as u64);
-                    let load = self.load(llptr.get_type(), llptr, align);
+                    let llty = place.layout.scalar_pair_element_gcc_type(self, i, false);
+                    let load = self.load(llty, llptr, align);
                     scalar_load_metadata(self, load, scalar);
                     if scalar.is_bool() { self.trunc(load, self.type_i1()) } else { load }
                 };
@@ -779,9 +798,16 @@ fn store(&mut self, val: RValue<'gcc>, ptr: RValue<'gcc>, align: Align) -> RValu
         self.store_with_flags(val, ptr, align, MemFlags::empty())
     }
 
-    fn store_with_flags(&mut self, val: RValue<'gcc>, ptr: RValue<'gcc>, _align: Align, _flags: MemFlags) -> RValue<'gcc> {
+    fn store_with_flags(&mut self, val: RValue<'gcc>, ptr: RValue<'gcc>, align: Align, _flags: MemFlags) -> RValue<'gcc> {
         let ptr = self.check_store(val, ptr);
-        self.llbb().add_assignment(None, ptr.dereference(None), val);
+        let destination = ptr.dereference(None);
+        // NOTE: libgccjit does not support specifying the alignment on the assignment, so we cast
+        // to type so it gets the proper alignment.
+        let destination_type = destination.to_rvalue().get_type().unqualified();
+        let aligned_type = destination_type.get_aligned(align.bytes()).make_pointer();
+        let aligned_destination = self.cx.context.new_bitcast(None, ptr, aligned_type);
+        let aligned_destination = aligned_destination.dereference(None);
+        self.llbb().add_assignment(None, aligned_destination, val);
         // TODO(antoyo): handle align and flags.
         // NOTE: dummy value here since it's never used. FIXME(antoyo): API should not return a value here?
         self.cx.context.new_rvalue_zero(self.type_i32())
@@ -953,7 +979,7 @@ fn memcpy(&mut self, dst: RValue<'gcc>, _dst_align: Align, src: RValue<'gcc>, _s
     fn memmove(&mut self, dst: RValue<'gcc>, dst_align: Align, src: RValue<'gcc>, src_align: Align, size: RValue<'gcc>, flags: MemFlags) {
         if flags.contains(MemFlags::NONTEMPORAL) {
             // HACK(nox): This is inefficient but there is no nontemporal memmove.
-            let val = self.load(src.get_type(), src, src_align);
+            let val = self.load(src.get_type().get_pointee().expect("get_pointee"), src, src_align);
             let ptr = self.pointercast(dst, self.type_ptr_to(self.val_ty(val)));
             self.store_with_flags(val, ptr, dst_align, flags);
             return;
@@ -1269,16 +1295,183 @@ fn instrprof_increment(&mut self, _fn_name: RValue<'gcc>, _hash: RValue<'gcc>, _
 }
 
 impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
+    #[cfg(feature="master")]
     pub fn shuffle_vector(&mut self, v1: RValue<'gcc>, v2: RValue<'gcc>, mask: RValue<'gcc>) -> RValue<'gcc> {
-        let return_type = v1.get_type();
-        let params = [
-            self.context.new_parameter(None, return_type, "v1"),
-            self.context.new_parameter(None, return_type, "v2"),
-            self.context.new_parameter(None, mask.get_type(), "mask"),
-        ];
-        let shuffle = self.context.new_function(None, FunctionType::Extern, return_type, &params, "_mm_shuffle_epi8", false);
-        self.context.new_call(None, shuffle, &[v1, v2, mask])
+        let struct_type = mask.get_type().is_struct().expect("mask of struct type");
+
+        // TODO(antoyo): use a recursive unqualified() here.
+        let vector_type = v1.get_type().unqualified().dyncast_vector().expect("vector type");
+        let element_type = vector_type.get_element_type();
+        let vec_num_units = vector_type.get_num_units();
+
+        let mask_num_units = struct_type.get_field_count();
+        let mut vector_elements = vec![];
+        let mask_element_type =
+            if element_type.is_integral() {
+                element_type
+            }
+            else {
+                #[cfg(feature="master")]
+                {
+                    self.cx.type_ix(element_type.get_size() as u64 * 8)
+                }
+                #[cfg(not(feature="master"))]
+                self.int_type
+            };
+        for i in 0..mask_num_units {
+            let field = struct_type.get_field(i as i32);
+            vector_elements.push(self.context.new_cast(None, mask.access_field(None, field).to_rvalue(), mask_element_type));
+        }
+
+        // NOTE: the mask needs to be the same length as the input vectors, so add the missing
+        // elements in the mask if needed.
+        for _ in mask_num_units..vec_num_units {
+            vector_elements.push(self.context.new_rvalue_zero(mask_element_type));
+        }
+
+        let array_type = self.context.new_array_type(None, element_type, vec_num_units as i32);
+        let result_type = self.context.new_vector_type(element_type, mask_num_units as u64);
+        let (v1, v2) =
+            if vec_num_units < mask_num_units {
+                // NOTE: the mask needs to be the same length as the input vectors, so join the 2
+                // vectors and create a dummy second vector.
+                // TODO(antoyo): switch to using new_vector_access.
+                let array = self.context.new_bitcast(None, v1, array_type);
+                let mut elements = vec![];
+                for i in 0..vec_num_units {
+                    elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue());
+                }
+                // TODO(antoyo): switch to using new_vector_access.
+                let array = self.context.new_bitcast(None, v2, array_type);
+                for i in 0..(mask_num_units - vec_num_units) {
+                    elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue());
+                }
+                let v1 = self.context.new_rvalue_from_vector(None, result_type, &elements);
+                let zero = self.context.new_rvalue_zero(element_type);
+                let v2 = self.context.new_rvalue_from_vector(None, result_type, &vec![zero; mask_num_units]);
+                (v1, v2)
+            }
+            else {
+                (v1, v2)
+            };
+
+        let new_mask_num_units = std::cmp::max(mask_num_units, vec_num_units);
+        let mask_type = self.context.new_vector_type(mask_element_type, new_mask_num_units as u64);
+        let mask = self.context.new_rvalue_from_vector(None, mask_type, &vector_elements);
+        let result = self.context.new_rvalue_vector_perm(None, v1, v2, mask);
+
+        if vec_num_units != mask_num_units {
+            // NOTE: if padding was added, only select the number of elements of the masks to
+            // remove that padding in the result.
+            let mut elements = vec![];
+            // TODO(antoyo): switch to using new_vector_access.
+            let array = self.context.new_bitcast(None, result, array_type);
+            for i in 0..mask_num_units {
+                elements.push(self.context.new_array_access(None, array, self.context.new_rvalue_from_int(self.int_type, i as i32)).to_rvalue());
+            }
+            self.context.new_rvalue_from_vector(None, result_type, &elements)
+        }
+        else {
+            result
+        }
+    }
+
+    #[cfg(not(feature="master"))]
+    pub fn shuffle_vector(&mut self, _v1: RValue<'gcc>, _v2: RValue<'gcc>, _mask: RValue<'gcc>) -> RValue<'gcc> {
+        unimplemented!();
     }
+
+    #[cfg(feature="master")]
+    pub fn vector_reduce<F>(&mut self, src: RValue<'gcc>, op: F) -> RValue<'gcc>
+    where F: Fn(RValue<'gcc>, RValue<'gcc>, &'gcc Context<'gcc>) -> RValue<'gcc>
+    {
+        let vector_type = src.get_type().unqualified().dyncast_vector().expect("vector type");
+        let element_count = vector_type.get_num_units();
+        let mut vector_elements = vec![];
+        for i in 0..element_count {
+            vector_elements.push(i);
+        }
+        let mask_type = self.context.new_vector_type(self.int_type, element_count as u64);
+        let mut shift = 1;
+        let mut res = src;
+        while shift < element_count {
+            let vector_elements: Vec<_> =
+                vector_elements.iter()
+                    .map(|i| self.context.new_rvalue_from_int(self.int_type, ((i + shift) % element_count) as i32))
+                    .collect();
+            let mask = self.context.new_rvalue_from_vector(None, mask_type, &vector_elements);
+            let shifted = self.context.new_rvalue_vector_perm(None, res, res, mask);
+            shift *= 2;
+            res = op(res, shifted, &self.context);
+        }
+        self.context.new_vector_access(None, res, self.context.new_rvalue_zero(self.int_type))
+            .to_rvalue()
+    }
+
+    #[cfg(not(feature="master"))]
+    pub fn vector_reduce<F>(&mut self, src: RValue<'gcc>, op: F) -> RValue<'gcc>
+    where F: Fn(RValue<'gcc>, RValue<'gcc>, &'gcc Context<'gcc>) -> RValue<'gcc>
+    {
+        unimplemented!();
+    }
+
+    pub fn vector_reduce_op(&mut self, src: RValue<'gcc>, op: BinaryOp) -> RValue<'gcc> {
+        self.vector_reduce(src, |a, b, context| context.new_binary_op(None, op, a.get_type(), a, b))
+    }
+
+    pub fn vector_reduce_fadd_fast(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> {
+        unimplemented!();
+    }
+
+    pub fn vector_reduce_fmul_fast(&mut self, _acc: RValue<'gcc>, _src: RValue<'gcc>) -> RValue<'gcc> {
+        unimplemented!();
+    }
+
+    // Inspired by Hacker's Delight min implementation.
+    pub fn vector_reduce_min(&mut self, src: RValue<'gcc>) -> RValue<'gcc> {
+        self.vector_reduce(src, |a, b, context| {
+            let differences_or_zeros = difference_or_zero(a, b, context);
+            context.new_binary_op(None, BinaryOp::Minus, a.get_type(), a, differences_or_zeros)
+        })
+    }
+
+    // Inspired by Hacker's Delight max implementation.
+    pub fn vector_reduce_max(&mut self, src: RValue<'gcc>) -> RValue<'gcc> {
+        self.vector_reduce(src, |a, b, context| {
+            let differences_or_zeros = difference_or_zero(a, b, context);
+            context.new_binary_op(None, BinaryOp::Plus, b.get_type(), b, differences_or_zeros)
+        })
+    }
+
+    pub fn vector_select(&mut self, cond: RValue<'gcc>, then_val: RValue<'gcc>, else_val: RValue<'gcc>) -> RValue<'gcc> {
+        // cond is a vector of integers, not of bools.
+        let cond_type = cond.get_type();
+        let vector_type = cond_type.unqualified().dyncast_vector().expect("vector type");
+        let num_units = vector_type.get_num_units();
+        let element_type = vector_type.get_element_type();
+        let zeros = vec![self.context.new_rvalue_zero(element_type); num_units];
+        let zeros = self.context.new_rvalue_from_vector(None, cond_type, &zeros);
+
+        let masks = self.context.new_comparison(None, ComparisonOp::NotEquals, cond, zeros);
+        let then_vals = masks & then_val;
+
+        let ones = vec![self.context.new_rvalue_one(element_type); num_units];
+        let ones = self.context.new_rvalue_from_vector(None, cond_type, &ones);
+        let inverted_masks = masks + ones;
+        // NOTE: sometimes, the type of else_val can be different than the type of then_val in
+        // libgccjit (vector of int vs vector of int32_t), but they should be the same for the AND
+        // operation to work.
+        let else_val = self.context.new_bitcast(None, else_val, then_val.get_type());
+        let else_vals = inverted_masks & else_val;
+
+        then_vals | else_vals
+    }
+}
+
+fn difference_or_zero<'gcc>(a: RValue<'gcc>, b: RValue<'gcc>, context: &'gcc Context<'gcc>) -> RValue<'gcc> {
+    let difference = a - b;
+    let masks = context.new_comparison(None, ComparisonOp::GreaterThanEquals, b, a);
+    difference & masks
 }
 
 impl<'a, 'gcc, 'tcx> StaticBuilderMethods for Builder<'a, 'gcc, 'tcx> {

diff --git a/compiler/rustc_codegen_gcc/src/common.rs b/compiler/rustc_codegen_gcc/src/common.rs
index b056b6d473042de78afd61ac952554c2a871dcf6..ce341406eaf4561a2d6aefa29283e8ecb28837dc 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/common.rs
+++ b/compiler/rustc_codegen_gcc/src/common.rs
@@ -121,8 +121,8 @@ fn const_u8(&self, _i: u8) -> RValue<'gcc> {
         unimplemented!();
     }
 
-    fn const_real(&self, _t: Type<'gcc>, _val: f64) -> RValue<'gcc> {
-        unimplemented!();
+    fn const_real(&self, typ: Type<'gcc>, val: f64) -> RValue<'gcc> {
+        self.context.new_rvalue_from_double(typ, val)
     }
 
     fn const_str(&self, s: Symbol) -> (RValue<'gcc>, RValue<'gcc>) {
@@ -279,6 +279,21 @@ fn to_signed(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Type<'gcc> {
         else if self.is_u128(cx) {
             cx.i128_type
         }
+        else if self.is_uchar(cx) {
+            cx.char_type
+        }
+        else if self.is_ushort(cx) {
+            cx.short_type
+        }
+        else if self.is_uint(cx) {
+            cx.int_type
+        }
+        else if self.is_ulong(cx) {
+            cx.long_type
+        }
+        else if self.is_ulonglong(cx) {
+            cx.longlong_type
+        }
         else {
             self.clone()
         }
@@ -300,6 +315,21 @@ fn to_unsigned(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Type<'gcc> {
         else if self.is_i128(cx) {
             cx.u128_type
         }
+        else if self.is_char(cx) {
+            cx.uchar_type
+        }
+        else if self.is_short(cx) {
+            cx.ushort_type
+        }
+        else if self.is_int(cx) {
+            cx.uint_type
+        }
+        else if self.is_long(cx) {
+            cx.ulong_type
+        }
+        else if self.is_longlong(cx) {
+            cx.ulonglong_type
+        }
         else {
             self.clone()
         }
@@ -312,6 +342,11 @@ pub trait TypeReflection<'gcc, 'tcx>  {
     fn is_uint(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
     fn is_ulong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
     fn is_ulonglong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
+    fn is_char(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
+    fn is_short(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
+    fn is_int(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
+    fn is_long(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
+    fn is_longlong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
 
     fn is_i8(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
     fn is_u8(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
@@ -326,15 +361,17 @@ pub trait TypeReflection<'gcc, 'tcx>  {
 
     fn is_f32(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
     fn is_f64(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool;
+
+    fn is_vector(&self) -> bool;
 }
 
 impl<'gcc, 'tcx> TypeReflection<'gcc, 'tcx> for Type<'gcc> {
     fn is_uchar(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
-        self.unqualified() == cx.u8_type
+        self.unqualified() == cx.uchar_type
     }
 
     fn is_ushort(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
-        self.unqualified() == cx.u16_type
+        self.unqualified() == cx.ushort_type
     }
 
     fn is_uint(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
@@ -349,6 +386,26 @@ fn is_ulonglong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
         self.unqualified() == cx.ulonglong_type
     }
 
+    fn is_char(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
+        self.unqualified() == cx.char_type
+    }
+
+    fn is_short(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
+        self.unqualified() == cx.short_type
+    }
+
+    fn is_int(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
+        self.unqualified() == cx.int_type
+    }
+
+    fn is_long(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
+        self.unqualified() == cx.long_type
+    }
+
+    fn is_longlong(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
+        self.unqualified() == cx.longlong_type
+    }
+
     fn is_i8(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
         self.unqualified() == cx.i8_type
     }
@@ -396,4 +453,21 @@ fn is_f32(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
     fn is_f64(&self, cx: &CodegenCx<'gcc, 'tcx>) -> bool {
         self.unqualified() == cx.context.new_type::<f64>()
     }
+
+    fn is_vector(&self) -> bool {
+        let mut typ = self.clone();
+        loop {
+            if typ.dyncast_vector().is_some() {
+                return true;
+            }
+
+            let old_type = typ;
+            typ = typ.unqualified();
+            if old_type == typ {
+                break;
+            }
+        }
+
+        false
+    }
 }

diff --git a/compiler/rustc_codegen_gcc/src/consts.rs b/compiler/rustc_codegen_gcc/src/consts.rs
index 3dc456f1aa0e98452eab5f54e8b5b7eed28297af..c0b8d21818f854cbbea2529ed6cf81ec3efe863f 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/consts.rs
+++ b/compiler/rustc_codegen_gcc/src/consts.rs
@@ -25,7 +25,9 @@ pub fn const_bitcast(&self, value: RValue<'gcc>, typ: Type<'gcc>) -> RValue<'gcc
                 }
             }
         }
-        self.context.new_bitcast(None, value, typ)
+        // NOTE: since bitcast makes a value non-constant, don't bitcast if not necessary as some
+        // SIMD builtins require a constant value.
+        self.bitcast_if_needed(value, typ)
     }
 }
 
@@ -45,7 +47,10 @@ fn static_addr_of(&self, cv: RValue<'gcc>, align: Align, kind: Option<&str>) ->
             }
         }
         let global_value = self.static_addr_of_mut(cv, align, kind);
-        // TODO(antoyo): set global constant.
+        #[cfg(feature = "master")]
+        self.global_lvalues.borrow().get(&global_value)
+            .expect("`static_addr_of_mut` did not add the global to `self.global_lvalues`")
+            .global_set_readonly();
         self.const_globals.borrow_mut().insert(cv, global_value);
         global_value
     }
@@ -79,20 +84,15 @@ fn codegen_static(&self, def_id: DefId, is_mutable: bool) {
 
         // TODO(antoyo): set alignment.
 
-        let value =
-            if value.get_type() != gcc_type {
-                self.context.new_bitcast(None, value, gcc_type)
-            }
-            else {
-                value
-            };
+        let value = self.bitcast_if_needed(value, gcc_type);
         global.global_set_initializer_rvalue(value);
 
         // As an optimization, all shared statics which do not have interior
         // mutability are placed into read-only memory.
         if !is_mutable {
             if self.type_is_freeze(ty) {
-                // TODO(antoyo): set global constant.
+                #[cfg(feature = "master")]
+                global.global_set_readonly();
             }
         }
 
@@ -171,8 +171,9 @@ pub fn static_addr_of_mut(&self, cv: RValue<'gcc>, align: Align, kind: Option<&s
                 Some(kind) if !self.tcx.sess.fewer_names() => {
                     let name = self.generate_local_symbol_name(kind);
                     // TODO(antoyo): check if it's okay that no link_section is set.
-                    // TODO(antoyo): set alignment here as well.
-                    let global = self.declare_private_global(&name[..], self.val_ty(cv));
+
+                    let typ = self.val_ty(cv).get_aligned(align.bytes());
+                    let global = self.declare_private_global(&name[..], typ);
                     global
                 }
                 _ => {

diff --git a/compiler/rustc_codegen_gcc/src/context.rs b/compiler/rustc_codegen_gcc/src/context.rs
index edbe7122bddbbc9e46699a028c0174398486bf0e..44f36cfa4cad4388e11f8ec333deea71c4291f19 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/context.rs
+++ b/compiler/rustc_codegen_gcc/src/context.rs
@@ -35,6 +35,7 @@ pub struct CodegenCx<'gcc, 'tcx> {
     pub normal_function_addresses: RefCell<FxHashSet<RValue<'gcc>>>,
 
     pub functions: RefCell<FxHashMap<String, Function<'gcc>>>,
+    pub intrinsics: RefCell<FxHashMap<String, Function<'gcc>>>,
 
     pub tls_model: gccjit::TlsModel,
 
@@ -53,10 +54,15 @@ pub struct CodegenCx<'gcc, 'tcx> {
     pub u128_type: Type<'gcc>,
     pub usize_type: Type<'gcc>,
 
+    pub char_type: Type<'gcc>,
+    pub uchar_type: Type<'gcc>,
+    pub short_type: Type<'gcc>,
+    pub ushort_type: Type<'gcc>,
     pub int_type: Type<'gcc>,
     pub uint_type: Type<'gcc>,
     pub long_type: Type<'gcc>,
     pub ulong_type: Type<'gcc>,
+    pub longlong_type: Type<'gcc>,
     pub ulonglong_type: Type<'gcc>,
     pub sizet_type: Type<'gcc>,
 
@@ -145,10 +151,15 @@ pub fn new(context: &'gcc Context<'gcc>, codegen_unit: &'tcx CodegenUnit<'tcx>,
         let float_type = context.new_type::<f32>();
         let double_type = context.new_type::<f64>();
 
+        let char_type = context.new_c_type(CType::Char);
+        let uchar_type = context.new_c_type(CType::UChar);
+        let short_type = context.new_c_type(CType::Short);
+        let ushort_type = context.new_c_type(CType::UShort);
         let int_type = context.new_c_type(CType::Int);
         let uint_type = context.new_c_type(CType::UInt);
         let long_type = context.new_c_type(CType::Long);
         let ulong_type = context.new_c_type(CType::ULong);
+        let longlong_type = context.new_c_type(CType::LongLong);
         let ulonglong_type = context.new_c_type(CType::ULongLong);
         let sizet_type = context.new_c_type(CType::SizeT);
 
@@ -184,6 +195,7 @@ pub fn new(context: &'gcc Context<'gcc>, codegen_unit: &'tcx CodegenUnit<'tcx>,
             current_func: RefCell::new(None),
             normal_function_addresses: Default::default(),
             functions: RefCell::new(functions),
+            intrinsics: RefCell::new(FxHashMap::default()),
 
             tls_model,
 
@@ -200,10 +212,15 @@ pub fn new(context: &'gcc Context<'gcc>, codegen_unit: &'tcx CodegenUnit<'tcx>,
             u32_type,
             u64_type,
             u128_type,
+            char_type,
+            uchar_type,
+            short_type,
+            ushort_type,
             int_type,
             uint_type,
             long_type,
             ulong_type,
+            longlong_type,
             ulonglong_type,
             sizet_type,
 
@@ -269,16 +286,25 @@ pub fn is_non_native_int_type(&self, typ: Type<'gcc>) -> bool {
     }
 
     pub fn is_native_int_type_or_bool(&self, typ: Type<'gcc>) -> bool {
-        self.is_native_int_type(typ) || typ == self.bool_type
+        self.is_native_int_type(typ) || typ.is_compatible_with(self.bool_type)
     }
 
     pub fn is_int_type_or_bool(&self, typ: Type<'gcc>) -> bool {
-        self.is_native_int_type(typ) || self.is_non_native_int_type(typ) || typ == self.bool_type
+        self.is_native_int_type(typ) || self.is_non_native_int_type(typ) || typ.is_compatible_with(self.bool_type)
     }
 
     pub fn sess(&self) -> &Session {
         &self.tcx.sess
     }
+
+    pub fn bitcast_if_needed(&self, value: RValue<'gcc>, expected_type: Type<'gcc>) -> RValue<'gcc> {
+        if value.get_type() != expected_type {
+            self.context.new_bitcast(None, value, expected_type)
+        }
+        else {
+            value
+        }
+    }
 }
 
 impl<'gcc, 'tcx> BackendTypes for CodegenCx<'gcc, 'tcx> {
@@ -306,8 +332,16 @@ fn get_fn(&self, instance: Instance<'tcx>) -> RValue<'gcc> {
     }
 
     fn get_fn_addr(&self, instance: Instance<'tcx>) -> RValue<'gcc> {
-        let func = get_fn(self, instance);
-        let func = self.rvalue_as_function(func);
+        let func_name = self.tcx.symbol_name(instance).name;
+
+        let func =
+            if self.intrinsics.borrow().contains_key(func_name) {
+                self.intrinsics.borrow()[func_name].clone()
+            }
+            else {
+                let func = get_fn(self, instance);
+                self.rvalue_as_function(func)
+            };
         let ptr = func.get_address(None);
 
         // TODO(antoyo): don't do this twice: i.e. in declare_fn and here.

diff --git a/compiler/rustc_codegen_gcc/src/declare.rs b/compiler/rustc_codegen_gcc/src/declare.rs
index 43017376916dca5e7f48aa94b4fd5c14f3f4a2d9..a619e2f77125243a062ca7617c098f7a2ca562c7 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/declare.rs
+++ b/compiler/rustc_codegen_gcc/src/declare.rs
@@ -11,7 +11,7 @@
 impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> {
     pub fn get_or_insert_global(&self, name: &str, ty: Type<'gcc>, is_tls: bool, link_section: Option<Symbol>) -> LValue<'gcc> {
         if self.globals.borrow().contains_key(name) {
-            let typ = self.globals.borrow().get(name).expect("global").get_type();
+            let typ = self.globals.borrow()[name].get_type();
             let global = self.context.new_global(None, GlobalKind::Imported, typ, name);
             if is_tls {
                 global.set_tls_model(self.tls_model);
@@ -103,11 +103,13 @@ pub fn get_declared_value(&self, name: &str) -> Option<RValue<'gcc>> {
 /// update the declaration and return existing Value instead.
 fn declare_raw_fn<'gcc>(cx: &CodegenCx<'gcc, '_>, name: &str, _callconv: () /*llvm::CallConv*/, return_type: Type<'gcc>, param_types: &[Type<'gcc>], variadic: bool) -> Function<'gcc> {
     if name.starts_with("llvm.") {
-        return llvm::intrinsic(name, cx);
+        let intrinsic = llvm::intrinsic(name, cx);
+        cx.intrinsics.borrow_mut().insert(name.to_string(), intrinsic);
+        return intrinsic;
     }
     let func =
         if cx.functions.borrow().contains_key(name) {
-            *cx.functions.borrow().get(name).expect("function")
+            cx.functions.borrow()[name]
         }
         else {
             let params: Vec<_> = param_types.into_iter().enumerate()

diff --git a/compiler/rustc_codegen_gcc/src/int.rs b/compiler/rustc_codegen_gcc/src/int.rs
index c3ed71ff730368f9bbda3473cf9ccfe8a550163b..0c5dab0046684bc9e48e504d6ded2ec2b083ba94 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/int.rs
+++ b/compiler/rustc_codegen_gcc/src/int.rs
@@ -153,8 +153,15 @@ fn additive_operation(&self, operation: BinaryOp, a: RValue<'gcc>, mut b: RValue
         let a_type = a.get_type();
         let b_type = b.get_type();
         if self.is_native_int_type_or_bool(a_type) && self.is_native_int_type_or_bool(b_type) {
-            if a.get_type() != b.get_type() {
-                b = self.context.new_cast(None, b, a.get_type());
+            if a_type != b_type {
+                if a_type.is_vector() {
+                    // Vector types need to be bitcast.
+                    // TODO(antoyo): perhaps use __builtin_convertvector for vector casting.
+                    b = self.context.new_bitcast(None, b, a.get_type());
+                }
+                else {
+                    b = self.context.new_cast(None, b, a.get_type());
+                }
             }
             self.context.new_binary_op(None, operation, a_type, a, b)
         }
@@ -593,7 +600,10 @@ fn bitwise_operation(&self, operation: BinaryOp, a: RValue<'gcc>, mut b: RValue<
         let b_type = b.get_type();
         let a_native = self.is_native_int_type_or_bool(a_type);
         let b_native = self.is_native_int_type_or_bool(b_type);
-        if a_native && b_native {
+        if a_type.is_vector() && b_type.is_vector() {
+            self.context.new_binary_op(None, operation, a_type, a, b)
+        }
+        else if a_native && b_native {
             if a_type != b_type {
                 b = self.context.new_cast(None, b, a_type);
             }
@@ -639,6 +649,8 @@ pub fn gcc_int_cast(&self, value: RValue<'gcc>, dest_typ: Type<'gcc>) -> RValue<
         else {
             // Since u128 and i128 are the only types that can be unsupported, we know the type of
             // value and the destination type have the same size, so a bitcast is fine.
+
+            // TODO(antoyo): perhaps use __builtin_convertvector for vector casting.
             self.context.new_bitcast(None, value, dest_typ)
         }
     }

diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/archs.rs b/compiler/rustc_codegen_gcc/src/intrinsic/archs.rs
new file mode 100644 (file)
index 0000000..fb6c38f
--- /dev/null
+++ b/compiler/rustc_codegen_gcc/src/intrinsic/archs.rs
@@ -0,0 +1,5722 @@
+// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py`
+// DO NOT EDIT IT!
+match name {
+    // AMDGPU
+    "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup",
+    "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup",
+    "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup",
+    "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup",
+    "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas",
+    "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas",
+    "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas",
+    "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas",
+    "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp",
+    "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp",
+    "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp",
+    "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp",
+    "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp",
+    "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp",
+    "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp",
+    "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp",
+    "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped",
+    "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped",
+    "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped",
+    "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped",
+    "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq",
+    "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq",
+    "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq",
+    "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq",
+    "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop",
+    "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop",
+    "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop",
+    "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop",
+    // aarch64
+    "llvm.aarch64.dmb" => "__builtin_arm_dmb",
+    "llvm.aarch64.dsb" => "__builtin_arm_dsb",
+    "llvm.aarch64.isb" => "__builtin_arm_isb",
+    "llvm.aarch64.sve.aesd" => "__builtin_sve_svaesd_u8",
+    "llvm.aarch64.sve.aese" => "__builtin_sve_svaese_u8",
+    "llvm.aarch64.sve.aesimc" => "__builtin_sve_svaesimc_u8",
+    "llvm.aarch64.sve.aesmc" => "__builtin_sve_svaesmc_u8",
+    "llvm.aarch64.sve.rax1" => "__builtin_sve_svrax1_u64",
+    "llvm.aarch64.sve.rdffr" => "__builtin_sve_svrdffr",
+    "llvm.aarch64.sve.rdffr.z" => "__builtin_sve_svrdffr_z",
+    "llvm.aarch64.sve.setffr" => "__builtin_sve_svsetffr",
+    "llvm.aarch64.sve.sm4e" => "__builtin_sve_svsm4e_u32",
+    "llvm.aarch64.sve.sm4ekey" => "__builtin_sve_svsm4ekey_u32",
+    "llvm.aarch64.sve.wrffr" => "__builtin_sve_svwrffr",
+    "llvm.aarch64.tcancel" => "__builtin_arm_tcancel",
+    "llvm.aarch64.tcommit" => "__builtin_arm_tcommit",
+    "llvm.aarch64.tstart" => "__builtin_arm_tstart",
+    "llvm.aarch64.ttest" => "__builtin_arm_ttest",
+    // amdgcn
+    "llvm.amdgcn.alignbyte" => "__builtin_amdgcn_alignbyte",
+    "llvm.amdgcn.buffer.wbinvl1" => "__builtin_amdgcn_buffer_wbinvl1",
+    "llvm.amdgcn.buffer.wbinvl1.sc" => "__builtin_amdgcn_buffer_wbinvl1_sc",
+    "llvm.amdgcn.buffer.wbinvl1.vol" => "__builtin_amdgcn_buffer_wbinvl1_vol",
+    "llvm.amdgcn.cubeid" => "__builtin_amdgcn_cubeid",
+    "llvm.amdgcn.cubema" => "__builtin_amdgcn_cubema",
+    "llvm.amdgcn.cubesc" => "__builtin_amdgcn_cubesc",
+    "llvm.amdgcn.cubetc" => "__builtin_amdgcn_cubetc",
+    "llvm.amdgcn.cvt.pk.i16" => "__builtin_amdgcn_cvt_pk_i16",
+    "llvm.amdgcn.cvt.pk.u16" => "__builtin_amdgcn_cvt_pk_u16",
+    "llvm.amdgcn.cvt.pk.u8.f32" => "__builtin_amdgcn_cvt_pk_u8_f32",
+    "llvm.amdgcn.cvt.pknorm.i16" => "__builtin_amdgcn_cvt_pknorm_i16",
+    "llvm.amdgcn.cvt.pknorm.u16" => "__builtin_amdgcn_cvt_pknorm_u16",
+    "llvm.amdgcn.cvt.pkrtz" => "__builtin_amdgcn_cvt_pkrtz",
+    "llvm.amdgcn.dispatch.id" => "__builtin_amdgcn_dispatch_id",
+    "llvm.amdgcn.ds.bpermute" => "__builtin_amdgcn_ds_bpermute",
+    "llvm.amdgcn.ds.fadd.v2bf16" => "__builtin_amdgcn_ds_atomic_fadd_v2bf16",
+    "llvm.amdgcn.ds.gws.barrier" => "__builtin_amdgcn_ds_gws_barrier",
+    "llvm.amdgcn.ds.gws.init" => "__builtin_amdgcn_ds_gws_init",
+    "llvm.amdgcn.ds.gws.sema.br" => "__builtin_amdgcn_ds_gws_sema_br",
+    "llvm.amdgcn.ds.gws.sema.p" => "__builtin_amdgcn_ds_gws_sema_p",
+    "llvm.amdgcn.ds.gws.sema.release.all" => "__builtin_amdgcn_ds_gws_sema_release_all",
+    "llvm.amdgcn.ds.gws.sema.v" => "__builtin_amdgcn_ds_gws_sema_v",
+    "llvm.amdgcn.ds.permute" => "__builtin_amdgcn_ds_permute",
+    "llvm.amdgcn.ds.swizzle" => "__builtin_amdgcn_ds_swizzle",
+    "llvm.amdgcn.endpgm" => "__builtin_amdgcn_endpgm",
+    "llvm.amdgcn.fdot2" => "__builtin_amdgcn_fdot2",
+    "llvm.amdgcn.fmed3" => "__builtin_amdgcn_fmed3",
+    "llvm.amdgcn.fmul.legacy" => "__builtin_amdgcn_fmul_legacy",
+    "llvm.amdgcn.groupstaticsize" => "__builtin_amdgcn_groupstaticsize",
+    "llvm.amdgcn.implicit.buffer.ptr" => "__builtin_amdgcn_implicit_buffer_ptr",
+    "llvm.amdgcn.implicitarg.ptr" => "__builtin_amdgcn_implicitarg_ptr",
+    "llvm.amdgcn.interp.mov" => "__builtin_amdgcn_interp_mov",
+    "llvm.amdgcn.interp.p1" => "__builtin_amdgcn_interp_p1",
+    "llvm.amdgcn.interp.p1.f16" => "__builtin_amdgcn_interp_p1_f16",
+    "llvm.amdgcn.interp.p2" => "__builtin_amdgcn_interp_p2",
+    "llvm.amdgcn.interp.p2.f16" => "__builtin_amdgcn_interp_p2_f16",
+    "llvm.amdgcn.is.private" => "__builtin_amdgcn_is_private",
+    "llvm.amdgcn.is.shared" => "__builtin_amdgcn_is_shared",
+    "llvm.amdgcn.kernarg.segment.ptr" => "__builtin_amdgcn_kernarg_segment_ptr",
+    "llvm.amdgcn.lerp" => "__builtin_amdgcn_lerp",
+    "llvm.amdgcn.mbcnt.hi" => "__builtin_amdgcn_mbcnt_hi",
+    "llvm.amdgcn.mbcnt.lo" => "__builtin_amdgcn_mbcnt_lo",
+    "llvm.amdgcn.mqsad.pk.u16.u8" => "__builtin_amdgcn_mqsad_pk_u16_u8",
+    "llvm.amdgcn.mqsad.u32.u8" => "__builtin_amdgcn_mqsad_u32_u8",
+    "llvm.amdgcn.msad.u8" => "__builtin_amdgcn_msad_u8",
+    "llvm.amdgcn.perm" => "__builtin_amdgcn_perm",
+    "llvm.amdgcn.permlane16" => "__builtin_amdgcn_permlane16",
+    "llvm.amdgcn.permlanex16" => "__builtin_amdgcn_permlanex16",
+    "llvm.amdgcn.qsad.pk.u16.u8" => "__builtin_amdgcn_qsad_pk_u16_u8",
+    "llvm.amdgcn.queue.ptr" => "__builtin_amdgcn_queue_ptr",
+    "llvm.amdgcn.rcp.legacy" => "__builtin_amdgcn_rcp_legacy",
+    "llvm.amdgcn.readfirstlane" => "__builtin_amdgcn_readfirstlane",
+    "llvm.amdgcn.readlane" => "__builtin_amdgcn_readlane",
+    "llvm.amdgcn.rsq.legacy" => "__builtin_amdgcn_rsq_legacy",
+    "llvm.amdgcn.s.barrier" => "__builtin_amdgcn_s_barrier",
+    "llvm.amdgcn.s.dcache.inv" => "__builtin_amdgcn_s_dcache_inv",
+    "llvm.amdgcn.s.dcache.inv.vol" => "__builtin_amdgcn_s_dcache_inv_vol",
+    "llvm.amdgcn.s.dcache.wb" => "__builtin_amdgcn_s_dcache_wb",
+    "llvm.amdgcn.s.dcache.wb.vol" => "__builtin_amdgcn_s_dcache_wb_vol",
+    "llvm.amdgcn.s.decperflevel" => "__builtin_amdgcn_s_decperflevel",
+    "llvm.amdgcn.s.get.waveid.in.workgroup" => "__builtin_amdgcn_s_get_waveid_in_workgroup",
+    "llvm.amdgcn.s.getpc" => "__builtin_amdgcn_s_getpc",
+    "llvm.amdgcn.s.getreg" => "__builtin_amdgcn_s_getreg",
+    "llvm.amdgcn.s.incperflevel" => "__builtin_amdgcn_s_incperflevel",
+    "llvm.amdgcn.s.memrealtime" => "__builtin_amdgcn_s_memrealtime",
+    "llvm.amdgcn.s.memtime" => "__builtin_amdgcn_s_memtime",
+    "llvm.amdgcn.s.sendmsg" => "__builtin_amdgcn_s_sendmsg",
+    "llvm.amdgcn.s.sendmsghalt" => "__builtin_amdgcn_s_sendmsghalt",
+    "llvm.amdgcn.s.setprio" => "__builtin_amdgcn_s_setprio",
+    "llvm.amdgcn.s.setreg" => "__builtin_amdgcn_s_setreg",
+    "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep",
+    "llvm.amdgcn.s.waitcnt" => "__builtin_amdgcn_s_waitcnt",
+    "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8",
+    "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16",
+    "llvm.amdgcn.sad.u8" => "__builtin_amdgcn_sad_u8",
+    "llvm.amdgcn.sched.barrier" => "__builtin_amdgcn_sched_barrier",
+    "llvm.amdgcn.sdot2" => "__builtin_amdgcn_sdot2",
+    "llvm.amdgcn.sdot4" => "__builtin_amdgcn_sdot4",
+    "llvm.amdgcn.sdot8" => "__builtin_amdgcn_sdot8",
+    "llvm.amdgcn.udot2" => "__builtin_amdgcn_udot2",
+    "llvm.amdgcn.udot4" => "__builtin_amdgcn_udot4",
+    "llvm.amdgcn.udot8" => "__builtin_amdgcn_udot8",
+    "llvm.amdgcn.wave.barrier" => "__builtin_amdgcn_wave_barrier",
+    "llvm.amdgcn.wavefrontsize" => "__builtin_amdgcn_wavefrontsize",
+    "llvm.amdgcn.writelane" => "__builtin_amdgcn_writelane",
+    // arm
+    "llvm.arm.cdp" => "__builtin_arm_cdp",
+    "llvm.arm.cdp2" => "__builtin_arm_cdp2",
+    "llvm.arm.cmse.tt" => "__builtin_arm_cmse_TT",
+    "llvm.arm.cmse.tta" => "__builtin_arm_cmse_TTA",
+    "llvm.arm.cmse.ttat" => "__builtin_arm_cmse_TTAT",
+    "llvm.arm.cmse.ttt" => "__builtin_arm_cmse_TTT",
+    "llvm.arm.dmb" => "__builtin_arm_dmb",
+    "llvm.arm.dsb" => "__builtin_arm_dsb",
+    "llvm.arm.get.fpscr" => "__builtin_arm_get_fpscr",
+    "llvm.arm.isb" => "__builtin_arm_isb",
+    "llvm.arm.ldc" => "__builtin_arm_ldc",
+    "llvm.arm.ldc2" => "__builtin_arm_ldc2",
+    "llvm.arm.ldc2l" => "__builtin_arm_ldc2l",
+    "llvm.arm.ldcl" => "__builtin_arm_ldcl",
+    "llvm.arm.mcr" => "__builtin_arm_mcr",
+    "llvm.arm.mcr2" => "__builtin_arm_mcr2",
+    "llvm.arm.mcrr" => "__builtin_arm_mcrr",
+    "llvm.arm.mcrr2" => "__builtin_arm_mcrr2",
+    "llvm.arm.mrc" => "__builtin_arm_mrc",
+    "llvm.arm.mrc2" => "__builtin_arm_mrc2",
+    "llvm.arm.qadd" => "__builtin_arm_qadd",
+    "llvm.arm.qadd16" => "__builtin_arm_qadd16",
+    "llvm.arm.qadd8" => "__builtin_arm_qadd8",
+    "llvm.arm.qasx" => "__builtin_arm_qasx",
+    "llvm.arm.qsax" => "__builtin_arm_qsax",
+    "llvm.arm.qsub" => "__builtin_arm_qsub",
+    "llvm.arm.qsub16" => "__builtin_arm_qsub16",
+    "llvm.arm.qsub8" => "__builtin_arm_qsub8",
+    "llvm.arm.sadd16" => "__builtin_arm_sadd16",
+    "llvm.arm.sadd8" => "__builtin_arm_sadd8",
+    "llvm.arm.sasx" => "__builtin_arm_sasx",
+    "llvm.arm.sel" => "__builtin_arm_sel",
+    "llvm.arm.set.fpscr" => "__builtin_arm_set_fpscr",
+    "llvm.arm.shadd16" => "__builtin_arm_shadd16",
+    "llvm.arm.shadd8" => "__builtin_arm_shadd8",
+    "llvm.arm.shasx" => "__builtin_arm_shasx",
+    "llvm.arm.shsax" => "__builtin_arm_shsax",
+    "llvm.arm.shsub16" => "__builtin_arm_shsub16",
+    "llvm.arm.shsub8" => "__builtin_arm_shsub8",
+    "llvm.arm.smlabb" => "__builtin_arm_smlabb",
+    "llvm.arm.smlabt" => "__builtin_arm_smlabt",
+    "llvm.arm.smlad" => "__builtin_arm_smlad",
+    "llvm.arm.smladx" => "__builtin_arm_smladx",
+    "llvm.arm.smlald" => "__builtin_arm_smlald",
+    "llvm.arm.smlaldx" => "__builtin_arm_smlaldx",
+    "llvm.arm.smlatb" => "__builtin_arm_smlatb",
+    "llvm.arm.smlatt" => "__builtin_arm_smlatt",
+    "llvm.arm.smlawb" => "__builtin_arm_smlawb",
+    "llvm.arm.smlawt" => "__builtin_arm_smlawt",
+    "llvm.arm.smlsd" => "__builtin_arm_smlsd",
+    "llvm.arm.smlsdx" => "__builtin_arm_smlsdx",
+    "llvm.arm.smlsld" => "__builtin_arm_smlsld",
+    "llvm.arm.smlsldx" => "__builtin_arm_smlsldx",
+    "llvm.arm.smuad" => "__builtin_arm_smuad",
+    "llvm.arm.smuadx" => "__builtin_arm_smuadx",
+    "llvm.arm.smulbb" => "__builtin_arm_smulbb",
+    "llvm.arm.smulbt" => "__builtin_arm_smulbt",
+    "llvm.arm.smultb" => "__builtin_arm_smultb",
+    "llvm.arm.smultt" => "__builtin_arm_smultt",
+    "llvm.arm.smulwb" => "__builtin_arm_smulwb",
+    "llvm.arm.smulwt" => "__builtin_arm_smulwt",
+    "llvm.arm.smusd" => "__builtin_arm_smusd",
+    "llvm.arm.smusdx" => "__builtin_arm_smusdx",
+    "llvm.arm.ssat" => "__builtin_arm_ssat",
+    "llvm.arm.ssat16" => "__builtin_arm_ssat16",
+    "llvm.arm.ssax" => "__builtin_arm_ssax",
+    "llvm.arm.ssub16" => "__builtin_arm_ssub16",
+    "llvm.arm.ssub8" => "__builtin_arm_ssub8",
+    "llvm.arm.stc" => "__builtin_arm_stc",
+    "llvm.arm.stc2" => "__builtin_arm_stc2",
+    "llvm.arm.stc2l" => "__builtin_arm_stc2l",
+    "llvm.arm.stcl" => "__builtin_arm_stcl",
+    "llvm.arm.sxtab16" => "__builtin_arm_sxtab16",
+    "llvm.arm.sxtb16" => "__builtin_arm_sxtb16",
+    "llvm.arm.thread.pointer" => "__builtin_thread_pointer",
+    "llvm.arm.uadd16" => "__builtin_arm_uadd16",
+    "llvm.arm.uadd8" => "__builtin_arm_uadd8",
+    "llvm.arm.uasx" => "__builtin_arm_uasx",
+    "llvm.arm.uhadd16" => "__builtin_arm_uhadd16",
+    "llvm.arm.uhadd8" => "__builtin_arm_uhadd8",
+    "llvm.arm.uhasx" => "__builtin_arm_uhasx",
+    "llvm.arm.uhsax" => "__builtin_arm_uhsax",
+    "llvm.arm.uhsub16" => "__builtin_arm_uhsub16",
+    "llvm.arm.uhsub8" => "__builtin_arm_uhsub8",
+    "llvm.arm.uqadd16" => "__builtin_arm_uqadd16",
+    "llvm.arm.uqadd8" => "__builtin_arm_uqadd8",
+    "llvm.arm.uqasx" => "__builtin_arm_uqasx",
+    "llvm.arm.uqsax" => "__builtin_arm_uqsax",
+    "llvm.arm.uqsub16" => "__builtin_arm_uqsub16",
+    "llvm.arm.uqsub8" => "__builtin_arm_uqsub8",
+    "llvm.arm.usad8" => "__builtin_arm_usad8",
+    "llvm.arm.usada8" => "__builtin_arm_usada8",
+    "llvm.arm.usat" => "__builtin_arm_usat",
+    "llvm.arm.usat16" => "__builtin_arm_usat16",
+    "llvm.arm.usax" => "__builtin_arm_usax",
+    "llvm.arm.usub16" => "__builtin_arm_usub16",
+    "llvm.arm.usub8" => "__builtin_arm_usub8",
+    "llvm.arm.uxtab16" => "__builtin_arm_uxtab16",
+    "llvm.arm.uxtb16" => "__builtin_arm_uxtb16",
+    // bpf
+    "llvm.bpf.btf.type.id" => "__builtin_bpf_btf_type_id",
+    "llvm.bpf.compare" => "__builtin_bpf_compare",
+    "llvm.bpf.load.byte" => "__builtin_bpf_load_byte",
+    "llvm.bpf.load.half" => "__builtin_bpf_load_half",
+    "llvm.bpf.load.word" => "__builtin_bpf_load_word",
+    "llvm.bpf.passthrough" => "__builtin_bpf_passthrough",
+    "llvm.bpf.preserve.enum.value" => "__builtin_bpf_preserve_enum_value",
+    "llvm.bpf.preserve.field.info" => "__builtin_bpf_preserve_field_info",
+    "llvm.bpf.preserve.type.info" => "__builtin_bpf_preserve_type_info",
+    "llvm.bpf.pseudo" => "__builtin_bpf_pseudo",
+    // cuda
+    "llvm.cuda.syncthreads" => "__syncthreads",
+    // hexagon
+    "llvm.hexagon.A2.abs" => "__builtin_HEXAGON_A2_abs",
+    "llvm.hexagon.A2.absp" => "__builtin_HEXAGON_A2_absp",
+    "llvm.hexagon.A2.abssat" => "__builtin_HEXAGON_A2_abssat",
+    "llvm.hexagon.A2.add" => "__builtin_HEXAGON_A2_add",
+    "llvm.hexagon.A2.addh.h16.hh" => "__builtin_HEXAGON_A2_addh_h16_hh",
+    "llvm.hexagon.A2.addh.h16.hl" => "__builtin_HEXAGON_A2_addh_h16_hl",
+    "llvm.hexagon.A2.addh.h16.lh" => "__builtin_HEXAGON_A2_addh_h16_lh",
+    "llvm.hexagon.A2.addh.h16.ll" => "__builtin_HEXAGON_A2_addh_h16_ll",
+    "llvm.hexagon.A2.addh.h16.sat.hh" => "__builtin_HEXAGON_A2_addh_h16_sat_hh",
+    "llvm.hexagon.A2.addh.h16.sat.hl" => "__builtin_HEXAGON_A2_addh_h16_sat_hl",
+    "llvm.hexagon.A2.addh.h16.sat.lh" => "__builtin_HEXAGON_A2_addh_h16_sat_lh",
+    "llvm.hexagon.A2.addh.h16.sat.ll" => "__builtin_HEXAGON_A2_addh_h16_sat_ll",
+    "llvm.hexagon.A2.addh.l16.hl" => "__builtin_HEXAGON_A2_addh_l16_hl",
+    "llvm.hexagon.A2.addh.l16.ll" => "__builtin_HEXAGON_A2_addh_l16_ll",
+    "llvm.hexagon.A2.addh.l16.sat.hl" => "__builtin_HEXAGON_A2_addh_l16_sat_hl",
+    "llvm.hexagon.A2.addh.l16.sat.ll" => "__builtin_HEXAGON_A2_addh_l16_sat_ll",
+    "llvm.hexagon.A2.addi" => "__builtin_HEXAGON_A2_addi",
+    "llvm.hexagon.A2.addp" => "__builtin_HEXAGON_A2_addp",
+    "llvm.hexagon.A2.addpsat" => "__builtin_HEXAGON_A2_addpsat",
+    "llvm.hexagon.A2.addsat" => "__builtin_HEXAGON_A2_addsat",
+    "llvm.hexagon.A2.addsp" => "__builtin_HEXAGON_A2_addsp",
+    "llvm.hexagon.A2.and" => "__builtin_HEXAGON_A2_and",
+    "llvm.hexagon.A2.andir" => "__builtin_HEXAGON_A2_andir",
+    "llvm.hexagon.A2.andp" => "__builtin_HEXAGON_A2_andp",
+    "llvm.hexagon.A2.aslh" => "__builtin_HEXAGON_A2_aslh",
+    "llvm.hexagon.A2.asrh" => "__builtin_HEXAGON_A2_asrh",
+    "llvm.hexagon.A2.combine.hh" => "__builtin_HEXAGON_A2_combine_hh",
+    "llvm.hexagon.A2.combine.hl" => "__builtin_HEXAGON_A2_combine_hl",
+    "llvm.hexagon.A2.combine.lh" => "__builtin_HEXAGON_A2_combine_lh",
+    "llvm.hexagon.A2.combine.ll" => "__builtin_HEXAGON_A2_combine_ll",
+    "llvm.hexagon.A2.combineii" => "__builtin_HEXAGON_A2_combineii",
+    "llvm.hexagon.A2.combinew" => "__builtin_HEXAGON_A2_combinew",
+    "llvm.hexagon.A2.max" => "__builtin_HEXAGON_A2_max",
+    "llvm.hexagon.A2.maxp" => "__builtin_HEXAGON_A2_maxp",
+    "llvm.hexagon.A2.maxu" => "__builtin_HEXAGON_A2_maxu",
+    "llvm.hexagon.A2.maxup" => "__builtin_HEXAGON_A2_maxup",
+    "llvm.hexagon.A2.min" => "__builtin_HEXAGON_A2_min",
+    "llvm.hexagon.A2.minp" => "__builtin_HEXAGON_A2_minp",
+    "llvm.hexagon.A2.minu" => "__builtin_HEXAGON_A2_minu",
+    "llvm.hexagon.A2.minup" => "__builtin_HEXAGON_A2_minup",
+    "llvm.hexagon.A2.neg" => "__builtin_HEXAGON_A2_neg",
+    "llvm.hexagon.A2.negp" => "__builtin_HEXAGON_A2_negp",
+    "llvm.hexagon.A2.negsat" => "__builtin_HEXAGON_A2_negsat",
+    "llvm.hexagon.A2.not" => "__builtin_HEXAGON_A2_not",
+    "llvm.hexagon.A2.notp" => "__builtin_HEXAGON_A2_notp",
+    "llvm.hexagon.A2.or" => "__builtin_HEXAGON_A2_or",
+    "llvm.hexagon.A2.orir" => "__builtin_HEXAGON_A2_orir",
+    "llvm.hexagon.A2.orp" => "__builtin_HEXAGON_A2_orp",
+    "llvm.hexagon.A2.roundsat" => "__builtin_HEXAGON_A2_roundsat",
+    "llvm.hexagon.A2.sat" => "__builtin_HEXAGON_A2_sat",
+    "llvm.hexagon.A2.satb" => "__builtin_HEXAGON_A2_satb",
+    "llvm.hexagon.A2.sath" => "__builtin_HEXAGON_A2_sath",
+    "llvm.hexagon.A2.satub" => "__builtin_HEXAGON_A2_satub",
+    "llvm.hexagon.A2.satuh" => "__builtin_HEXAGON_A2_satuh",
+    "llvm.hexagon.A2.sub" => "__builtin_HEXAGON_A2_sub",
+    "llvm.hexagon.A2.subh.h16.hh" => "__builtin_HEXAGON_A2_subh_h16_hh",
+    "llvm.hexagon.A2.subh.h16.hl" => "__builtin_HEXAGON_A2_subh_h16_hl",
+    "llvm.hexagon.A2.subh.h16.lh" => "__builtin_HEXAGON_A2_subh_h16_lh",
+    "llvm.hexagon.A2.subh.h16.ll" => "__builtin_HEXAGON_A2_subh_h16_ll",
+    "llvm.hexagon.A2.subh.h16.sat.hh" => "__builtin_HEXAGON_A2_subh_h16_sat_hh",
+    "llvm.hexagon.A2.subh.h16.sat.hl" => "__builtin_HEXAGON_A2_subh_h16_sat_hl",
+    "llvm.hexagon.A2.subh.h16.sat.lh" => "__builtin_HEXAGON_A2_subh_h16_sat_lh",
+    "llvm.hexagon.A2.subh.h16.sat.ll" => "__builtin_HEXAGON_A2_subh_h16_sat_ll",
+    "llvm.hexagon.A2.subh.l16.hl" => "__builtin_HEXAGON_A2_subh_l16_hl",
+    "llvm.hexagon.A2.subh.l16.ll" => "__builtin_HEXAGON_A2_subh_l16_ll",
+    "llvm.hexagon.A2.subh.l16.sat.hl" => "__builtin_HEXAGON_A2_subh_l16_sat_hl",
+    "llvm.hexagon.A2.subh.l16.sat.ll" => "__builtin_HEXAGON_A2_subh_l16_sat_ll",
+    "llvm.hexagon.A2.subp" => "__builtin_HEXAGON_A2_subp",
+    "llvm.hexagon.A2.subri" => "__builtin_HEXAGON_A2_subri",
+    "llvm.hexagon.A2.subsat" => "__builtin_HEXAGON_A2_subsat",
+    "llvm.hexagon.A2.svaddh" => "__builtin_HEXAGON_A2_svaddh",
+    "llvm.hexagon.A2.svaddhs" => "__builtin_HEXAGON_A2_svaddhs",
+    "llvm.hexagon.A2.svadduhs" => "__builtin_HEXAGON_A2_svadduhs",
+    "llvm.hexagon.A2.svavgh" => "__builtin_HEXAGON_A2_svavgh",
+    "llvm.hexagon.A2.svavghs" => "__builtin_HEXAGON_A2_svavghs",
+    "llvm.hexagon.A2.svnavgh" => "__builtin_HEXAGON_A2_svnavgh",
+    "llvm.hexagon.A2.svsubh" => "__builtin_HEXAGON_A2_svsubh",
+    "llvm.hexagon.A2.svsubhs" => "__builtin_HEXAGON_A2_svsubhs",
+    "llvm.hexagon.A2.svsubuhs" => "__builtin_HEXAGON_A2_svsubuhs",
+    "llvm.hexagon.A2.swiz" => "__builtin_HEXAGON_A2_swiz",
+    "llvm.hexagon.A2.sxtb" => "__builtin_HEXAGON_A2_sxtb",
+    "llvm.hexagon.A2.sxth" => "__builtin_HEXAGON_A2_sxth",
+    "llvm.hexagon.A2.sxtw" => "__builtin_HEXAGON_A2_sxtw",
+    "llvm.hexagon.A2.tfr" => "__builtin_HEXAGON_A2_tfr",
+    "llvm.hexagon.A2.tfrih" => "__builtin_HEXAGON_A2_tfrih",
+    "llvm.hexagon.A2.tfril" => "__builtin_HEXAGON_A2_tfril",
+    "llvm.hexagon.A2.tfrp" => "__builtin_HEXAGON_A2_tfrp",
+    "llvm.hexagon.A2.tfrpi" => "__builtin_HEXAGON_A2_tfrpi",
+    "llvm.hexagon.A2.tfrsi" => "__builtin_HEXAGON_A2_tfrsi",
+    "llvm.hexagon.A2.vabsh" => "__builtin_HEXAGON_A2_vabsh",
+    "llvm.hexagon.A2.vabshsat" => "__builtin_HEXAGON_A2_vabshsat",
+    "llvm.hexagon.A2.vabsw" => "__builtin_HEXAGON_A2_vabsw",
+    "llvm.hexagon.A2.vabswsat" => "__builtin_HEXAGON_A2_vabswsat",
+    "llvm.hexagon.A2.vaddb.map" => "__builtin_HEXAGON_A2_vaddb_map",
+    "llvm.hexagon.A2.vaddh" => "__builtin_HEXAGON_A2_vaddh",
+    "llvm.hexagon.A2.vaddhs" => "__builtin_HEXAGON_A2_vaddhs",
+    "llvm.hexagon.A2.vaddub" => "__builtin_HEXAGON_A2_vaddub",
+    "llvm.hexagon.A2.vaddubs" => "__builtin_HEXAGON_A2_vaddubs",
+    "llvm.hexagon.A2.vadduhs" => "__builtin_HEXAGON_A2_vadduhs",
+    "llvm.hexagon.A2.vaddw" => "__builtin_HEXAGON_A2_vaddw",
+    "llvm.hexagon.A2.vaddws" => "__builtin_HEXAGON_A2_vaddws",
+    "llvm.hexagon.A2.vavgh" => "__builtin_HEXAGON_A2_vavgh",
+    "llvm.hexagon.A2.vavghcr" => "__builtin_HEXAGON_A2_vavghcr",
+    "llvm.hexagon.A2.vavghr" => "__builtin_HEXAGON_A2_vavghr",
+    "llvm.hexagon.A2.vavgub" => "__builtin_HEXAGON_A2_vavgub",
+    "llvm.hexagon.A2.vavgubr" => "__builtin_HEXAGON_A2_vavgubr",
+    "llvm.hexagon.A2.vavguh" => "__builtin_HEXAGON_A2_vavguh",
+    "llvm.hexagon.A2.vavguhr" => "__builtin_HEXAGON_A2_vavguhr",
+    "llvm.hexagon.A2.vavguw" => "__builtin_HEXAGON_A2_vavguw",
+    "llvm.hexagon.A2.vavguwr" => "__builtin_HEXAGON_A2_vavguwr",
+    "llvm.hexagon.A2.vavgw" => "__builtin_HEXAGON_A2_vavgw",
+    "llvm.hexagon.A2.vavgwcr" => "__builtin_HEXAGON_A2_vavgwcr",
+    "llvm.hexagon.A2.vavgwr" => "__builtin_HEXAGON_A2_vavgwr",
+    "llvm.hexagon.A2.vcmpbeq" => "__builtin_HEXAGON_A2_vcmpbeq",
+    "llvm.hexagon.A2.vcmpbgtu" => "__builtin_HEXAGON_A2_vcmpbgtu",
+    "llvm.hexagon.A2.vcmpheq" => "__builtin_HEXAGON_A2_vcmpheq",
+    "llvm.hexagon.A2.vcmphgt" => "__builtin_HEXAGON_A2_vcmphgt",
+    "llvm.hexagon.A2.vcmphgtu" => "__builtin_HEXAGON_A2_vcmphgtu",
+    "llvm.hexagon.A2.vcmpweq" => "__builtin_HEXAGON_A2_vcmpweq",
+    "llvm.hexagon.A2.vcmpwgt" => "__builtin_HEXAGON_A2_vcmpwgt",
+    "llvm.hexagon.A2.vcmpwgtu" => "__builtin_HEXAGON_A2_vcmpwgtu",
+    "llvm.hexagon.A2.vconj" => "__builtin_HEXAGON_A2_vconj",
+    "llvm.hexagon.A2.vmaxb" => "__builtin_HEXAGON_A2_vmaxb",
+    "llvm.hexagon.A2.vmaxh" => "__builtin_HEXAGON_A2_vmaxh",
+    "llvm.hexagon.A2.vmaxub" => "__builtin_HEXAGON_A2_vmaxub",
+    "llvm.hexagon.A2.vmaxuh" => "__builtin_HEXAGON_A2_vmaxuh",
+    "llvm.hexagon.A2.vmaxuw" => "__builtin_HEXAGON_A2_vmaxuw",
+    "llvm.hexagon.A2.vmaxw" => "__builtin_HEXAGON_A2_vmaxw",
+    "llvm.hexagon.A2.vminb" => "__builtin_HEXAGON_A2_vminb",
+    "llvm.hexagon.A2.vminh" => "__builtin_HEXAGON_A2_vminh",
+    "llvm.hexagon.A2.vminub" => "__builtin_HEXAGON_A2_vminub",
+    "llvm.hexagon.A2.vminuh" => "__builtin_HEXAGON_A2_vminuh",
+    "llvm.hexagon.A2.vminuw" => "__builtin_HEXAGON_A2_vminuw",
+    "llvm.hexagon.A2.vminw" => "__builtin_HEXAGON_A2_vminw",
+    "llvm.hexagon.A2.vnavgh" => "__builtin_HEXAGON_A2_vnavgh",
+    "llvm.hexagon.A2.vnavghcr" => "__builtin_HEXAGON_A2_vnavghcr",
+    "llvm.hexagon.A2.vnavghr" => "__builtin_HEXAGON_A2_vnavghr",
+    "llvm.hexagon.A2.vnavgw" => "__builtin_HEXAGON_A2_vnavgw",
+    "llvm.hexagon.A2.vnavgwcr" => "__builtin_HEXAGON_A2_vnavgwcr",
+    "llvm.hexagon.A2.vnavgwr" => "__builtin_HEXAGON_A2_vnavgwr",
+    "llvm.hexagon.A2.vraddub" => "__builtin_HEXAGON_A2_vraddub",
+    "llvm.hexagon.A2.vraddub.acc" => "__builtin_HEXAGON_A2_vraddub_acc",
+    "llvm.hexagon.A2.vrsadub" => "__builtin_HEXAGON_A2_vrsadub",
+    "llvm.hexagon.A2.vrsadub.acc" => "__builtin_HEXAGON_A2_vrsadub_acc",
+    "llvm.hexagon.A2.vsubb.map" => "__builtin_HEXAGON_A2_vsubb_map",
+    "llvm.hexagon.A2.vsubh" => "__builtin_HEXAGON_A2_vsubh",
+    "llvm.hexagon.A2.vsubhs" => "__builtin_HEXAGON_A2_vsubhs",
+    "llvm.hexagon.A2.vsubub" => "__builtin_HEXAGON_A2_vsubub",
+    "llvm.hexagon.A2.vsububs" => "__builtin_HEXAGON_A2_vsububs",
+    "llvm.hexagon.A2.vsubuhs" => "__builtin_HEXAGON_A2_vsubuhs",
+    "llvm.hexagon.A2.vsubw" => "__builtin_HEXAGON_A2_vsubw",
+    "llvm.hexagon.A2.vsubws" => "__builtin_HEXAGON_A2_vsubws",
+    "llvm.hexagon.A2.xor" => "__builtin_HEXAGON_A2_xor",
+    "llvm.hexagon.A2.xorp" => "__builtin_HEXAGON_A2_xorp",
+    "llvm.hexagon.A2.zxtb" => "__builtin_HEXAGON_A2_zxtb",
+    "llvm.hexagon.A2.zxth" => "__builtin_HEXAGON_A2_zxth",
+    "llvm.hexagon.A4.andn" => "__builtin_HEXAGON_A4_andn",
+    "llvm.hexagon.A4.andnp" => "__builtin_HEXAGON_A4_andnp",
+    "llvm.hexagon.A4.bitsplit" => "__builtin_HEXAGON_A4_bitsplit",
+    "llvm.hexagon.A4.bitspliti" => "__builtin_HEXAGON_A4_bitspliti",
+    "llvm.hexagon.A4.boundscheck" => "__builtin_HEXAGON_A4_boundscheck",
+    "llvm.hexagon.A4.cmpbeq" => "__builtin_HEXAGON_A4_cmpbeq",
+    "llvm.hexagon.A4.cmpbeqi" => "__builtin_HEXAGON_A4_cmpbeqi",
+    "llvm.hexagon.A4.cmpbgt" => "__builtin_HEXAGON_A4_cmpbgt",
+    "llvm.hexagon.A4.cmpbgti" => "__builtin_HEXAGON_A4_cmpbgti",
+    "llvm.hexagon.A4.cmpbgtu" => "__builtin_HEXAGON_A4_cmpbgtu",
+    "llvm.hexagon.A4.cmpbgtui" => "__builtin_HEXAGON_A4_cmpbgtui",
+    "llvm.hexagon.A4.cmpheq" => "__builtin_HEXAGON_A4_cmpheq",
+    "llvm.hexagon.A4.cmpheqi" => "__builtin_HEXAGON_A4_cmpheqi",
+    "llvm.hexagon.A4.cmphgt" => "__builtin_HEXAGON_A4_cmphgt",
+    "llvm.hexagon.A4.cmphgti" => "__builtin_HEXAGON_A4_cmphgti",
+    "llvm.hexagon.A4.cmphgtu" => "__builtin_HEXAGON_A4_cmphgtu",
+    "llvm.hexagon.A4.cmphgtui" => "__builtin_HEXAGON_A4_cmphgtui",
+    "llvm.hexagon.A4.combineir" => "__builtin_HEXAGON_A4_combineir",
+    "llvm.hexagon.A4.combineri" => "__builtin_HEXAGON_A4_combineri",
+    "llvm.hexagon.A4.cround.ri" => "__builtin_HEXAGON_A4_cround_ri",
+    "llvm.hexagon.A4.cround.rr" => "__builtin_HEXAGON_A4_cround_rr",
+    "llvm.hexagon.A4.modwrapu" => "__builtin_HEXAGON_A4_modwrapu",
+    "llvm.hexagon.A4.orn" => "__builtin_HEXAGON_A4_orn",
+    "llvm.hexagon.A4.ornp" => "__builtin_HEXAGON_A4_ornp",
+    "llvm.hexagon.A4.rcmpeq" => "__builtin_HEXAGON_A4_rcmpeq",
+    "llvm.hexagon.A4.rcmpeqi" => "__builtin_HEXAGON_A4_rcmpeqi",
+    "llvm.hexagon.A4.rcmpneq" => "__builtin_HEXAGON_A4_rcmpneq",
+    "llvm.hexagon.A4.rcmpneqi" => "__builtin_HEXAGON_A4_rcmpneqi",
+    "llvm.hexagon.A4.round.ri" => "__builtin_HEXAGON_A4_round_ri",
+    "llvm.hexagon.A4.round.ri.sat" => "__builtin_HEXAGON_A4_round_ri_sat",
+    "llvm.hexagon.A4.round.rr" => "__builtin_HEXAGON_A4_round_rr",
+    "llvm.hexagon.A4.round.rr.sat" => "__builtin_HEXAGON_A4_round_rr_sat",
+    "llvm.hexagon.A4.tlbmatch" => "__builtin_HEXAGON_A4_tlbmatch",
+    "llvm.hexagon.A4.vcmpbeq.any" => "__builtin_HEXAGON_A4_vcmpbeq_any",
+    "llvm.hexagon.A4.vcmpbeqi" => "__builtin_HEXAGON_A4_vcmpbeqi",
+    "llvm.hexagon.A4.vcmpbgt" => "__builtin_HEXAGON_A4_vcmpbgt",
+    "llvm.hexagon.A4.vcmpbgti" => "__builtin_HEXAGON_A4_vcmpbgti",
+    "llvm.hexagon.A4.vcmpbgtui" => "__builtin_HEXAGON_A4_vcmpbgtui",
+    "llvm.hexagon.A4.vcmpheqi" => "__builtin_HEXAGON_A4_vcmpheqi",
+    "llvm.hexagon.A4.vcmphgti" => "__builtin_HEXAGON_A4_vcmphgti",
+    "llvm.hexagon.A4.vcmphgtui" => "__builtin_HEXAGON_A4_vcmphgtui",
+    "llvm.hexagon.A4.vcmpweqi" => "__builtin_HEXAGON_A4_vcmpweqi",
+    "llvm.hexagon.A4.vcmpwgti" => "__builtin_HEXAGON_A4_vcmpwgti",
+    "llvm.hexagon.A4.vcmpwgtui" => "__builtin_HEXAGON_A4_vcmpwgtui",
+    "llvm.hexagon.A4.vrmaxh" => "__builtin_HEXAGON_A4_vrmaxh",
+    "llvm.hexagon.A4.vrmaxuh" => "__builtin_HEXAGON_A4_vrmaxuh",
+    "llvm.hexagon.A4.vrmaxuw" => "__builtin_HEXAGON_A4_vrmaxuw",
+    "llvm.hexagon.A4.vrmaxw" => "__builtin_HEXAGON_A4_vrmaxw",
+    "llvm.hexagon.A4.vrminh" => "__builtin_HEXAGON_A4_vrminh",
+    "llvm.hexagon.A4.vrminuh" => "__builtin_HEXAGON_A4_vrminuh",
+    "llvm.hexagon.A4.vrminuw" => "__builtin_HEXAGON_A4_vrminuw",
+    "llvm.hexagon.A4.vrminw" => "__builtin_HEXAGON_A4_vrminw",
+    "llvm.hexagon.A5.vaddhubs" => "__builtin_HEXAGON_A5_vaddhubs",
+    "llvm.hexagon.C2.all8" => "__builtin_HEXAGON_C2_all8",
+    "llvm.hexagon.C2.and" => "__builtin_HEXAGON_C2_and",
+    "llvm.hexagon.C2.andn" => "__builtin_HEXAGON_C2_andn",
+    "llvm.hexagon.C2.any8" => "__builtin_HEXAGON_C2_any8",
+    "llvm.hexagon.C2.bitsclr" => "__builtin_HEXAGON_C2_bitsclr",
+    "llvm.hexagon.C2.bitsclri" => "__builtin_HEXAGON_C2_bitsclri",
+    "llvm.hexagon.C2.bitsset" => "__builtin_HEXAGON_C2_bitsset",
+    "llvm.hexagon.C2.cmpeq" => "__builtin_HEXAGON_C2_cmpeq",
+    "llvm.hexagon.C2.cmpeqi" => "__builtin_HEXAGON_C2_cmpeqi",
+    "llvm.hexagon.C2.cmpeqp" => "__builtin_HEXAGON_C2_cmpeqp",
+    "llvm.hexagon.C2.cmpgei" => "__builtin_HEXAGON_C2_cmpgei",
+    "llvm.hexagon.C2.cmpgeui" => "__builtin_HEXAGON_C2_cmpgeui",
+    "llvm.hexagon.C2.cmpgt" => "__builtin_HEXAGON_C2_cmpgt",
+    "llvm.hexagon.C2.cmpgti" => "__builtin_HEXAGON_C2_cmpgti",
+    "llvm.hexagon.C2.cmpgtp" => "__builtin_HEXAGON_C2_cmpgtp",
+    "llvm.hexagon.C2.cmpgtu" => "__builtin_HEXAGON_C2_cmpgtu",
+    "llvm.hexagon.C2.cmpgtui" => "__builtin_HEXAGON_C2_cmpgtui",
+    "llvm.hexagon.C2.cmpgtup" => "__builtin_HEXAGON_C2_cmpgtup",
+    "llvm.hexagon.C2.cmplt" => "__builtin_HEXAGON_C2_cmplt",
+    "llvm.hexagon.C2.cmpltu" => "__builtin_HEXAGON_C2_cmpltu",
+    "llvm.hexagon.C2.mask" => "__builtin_HEXAGON_C2_mask",
+    "llvm.hexagon.C2.mux" => "__builtin_HEXAGON_C2_mux",
+    "llvm.hexagon.C2.muxii" => "__builtin_HEXAGON_C2_muxii",
+    "llvm.hexagon.C2.muxir" => "__builtin_HEXAGON_C2_muxir",
+    "llvm.hexagon.C2.muxri" => "__builtin_HEXAGON_C2_muxri",
+    "llvm.hexagon.C2.not" => "__builtin_HEXAGON_C2_not",
+    "llvm.hexagon.C2.or" => "__builtin_HEXAGON_C2_or",
+    "llvm.hexagon.C2.orn" => "__builtin_HEXAGON_C2_orn",
+    "llvm.hexagon.C2.pxfer.map" => "__builtin_HEXAGON_C2_pxfer_map",
+    "llvm.hexagon.C2.tfrpr" => "__builtin_HEXAGON_C2_tfrpr",
+    "llvm.hexagon.C2.tfrrp" => "__builtin_HEXAGON_C2_tfrrp",
+    "llvm.hexagon.C2.vitpack" => "__builtin_HEXAGON_C2_vitpack",
+    "llvm.hexagon.C2.vmux" => "__builtin_HEXAGON_C2_vmux",
+    "llvm.hexagon.C2.xor" => "__builtin_HEXAGON_C2_xor",
+    "llvm.hexagon.C4.and.and" => "__builtin_HEXAGON_C4_and_and",
+    "llvm.hexagon.C4.and.andn" => "__builtin_HEXAGON_C4_and_andn",
+    "llvm.hexagon.C4.and.or" => "__builtin_HEXAGON_C4_and_or",
+    "llvm.hexagon.C4.and.orn" => "__builtin_HEXAGON_C4_and_orn",
+    "llvm.hexagon.C4.cmplte" => "__builtin_HEXAGON_C4_cmplte",
+    "llvm.hexagon.C4.cmpltei" => "__builtin_HEXAGON_C4_cmpltei",
+    "llvm.hexagon.C4.cmplteu" => "__builtin_HEXAGON_C4_cmplteu",
+    "llvm.hexagon.C4.cmplteui" => "__builtin_HEXAGON_C4_cmplteui",
+    "llvm.hexagon.C4.cmpneq" => "__builtin_HEXAGON_C4_cmpneq",
+    "llvm.hexagon.C4.cmpneqi" => "__builtin_HEXAGON_C4_cmpneqi",
+    "llvm.hexagon.C4.fastcorner9" => "__builtin_HEXAGON_C4_fastcorner9",
+    "llvm.hexagon.C4.fastcorner9.not" => "__builtin_HEXAGON_C4_fastcorner9_not",
+    "llvm.hexagon.C4.nbitsclr" => "__builtin_HEXAGON_C4_nbitsclr",
+    "llvm.hexagon.C4.nbitsclri" => "__builtin_HEXAGON_C4_nbitsclri",
+    "llvm.hexagon.C4.nbitsset" => "__builtin_HEXAGON_C4_nbitsset",
+    "llvm.hexagon.C4.or.and" => "__builtin_HEXAGON_C4_or_and",
+    "llvm.hexagon.C4.or.andn" => "__builtin_HEXAGON_C4_or_andn",
+    "llvm.hexagon.C4.or.or" => "__builtin_HEXAGON_C4_or_or",
+    "llvm.hexagon.C4.or.orn" => "__builtin_HEXAGON_C4_or_orn",
+    "llvm.hexagon.F2.conv.d2df" => "__builtin_HEXAGON_F2_conv_d2df",
+    "llvm.hexagon.F2.conv.d2sf" => "__builtin_HEXAGON_F2_conv_d2sf",
+    "llvm.hexagon.F2.conv.df2d" => "__builtin_HEXAGON_F2_conv_df2d",
+    "llvm.hexagon.F2.conv.df2d.chop" => "__builtin_HEXAGON_F2_conv_df2d_chop",
+    "llvm.hexagon.F2.conv.df2sf" => "__builtin_HEXAGON_F2_conv_df2sf",
+    "llvm.hexagon.F2.conv.df2ud" => "__builtin_HEXAGON_F2_conv_df2ud",
+    "llvm.hexagon.F2.conv.df2ud.chop" => "__builtin_HEXAGON_F2_conv_df2ud_chop",
+    "llvm.hexagon.F2.conv.df2uw" => "__builtin_HEXAGON_F2_conv_df2uw",
+    "llvm.hexagon.F2.conv.df2uw.chop" => "__builtin_HEXAGON_F2_conv_df2uw_chop",
+    "llvm.hexagon.F2.conv.df2w" => "__builtin_HEXAGON_F2_conv_df2w",
+    "llvm.hexagon.F2.conv.df2w.chop" => "__builtin_HEXAGON_F2_conv_df2w_chop",
+    "llvm.hexagon.F2.conv.sf2d" => "__builtin_HEXAGON_F2_conv_sf2d",
+    "llvm.hexagon.F2.conv.sf2d.chop" => "__builtin_HEXAGON_F2_conv_sf2d_chop",
+    "llvm.hexagon.F2.conv.sf2df" => "__builtin_HEXAGON_F2_conv_sf2df",
+    "llvm.hexagon.F2.conv.sf2ud" => "__builtin_HEXAGON_F2_conv_sf2ud",
+    "llvm.hexagon.F2.conv.sf2ud.chop" => "__builtin_HEXAGON_F2_conv_sf2ud_chop",
+    "llvm.hexagon.F2.conv.sf2uw" => "__builtin_HEXAGON_F2_conv_sf2uw",
+    "llvm.hexagon.F2.conv.sf2uw.chop" => "__builtin_HEXAGON_F2_conv_sf2uw_chop",
+    "llvm.hexagon.F2.conv.sf2w" => "__builtin_HEXAGON_F2_conv_sf2w",
+    "llvm.hexagon.F2.conv.sf2w.chop" => "__builtin_HEXAGON_F2_conv_sf2w_chop",
+    "llvm.hexagon.F2.conv.ud2df" => "__builtin_HEXAGON_F2_conv_ud2df",
+    "llvm.hexagon.F2.conv.ud2sf" => "__builtin_HEXAGON_F2_conv_ud2sf",
+    "llvm.hexagon.F2.conv.uw2df" => "__builtin_HEXAGON_F2_conv_uw2df",
+    "llvm.hexagon.F2.conv.uw2sf" => "__builtin_HEXAGON_F2_conv_uw2sf",
+    "llvm.hexagon.F2.conv.w2df" => "__builtin_HEXAGON_F2_conv_w2df",
+    "llvm.hexagon.F2.conv.w2sf" => "__builtin_HEXAGON_F2_conv_w2sf",
+    "llvm.hexagon.F2.dfadd" => "__builtin_HEXAGON_F2_dfadd",
+    "llvm.hexagon.F2.dfclass" => "__builtin_HEXAGON_F2_dfclass",
+    "llvm.hexagon.F2.dfcmpeq" => "__builtin_HEXAGON_F2_dfcmpeq",
+    "llvm.hexagon.F2.dfcmpge" => "__builtin_HEXAGON_F2_dfcmpge",
+    "llvm.hexagon.F2.dfcmpgt" => "__builtin_HEXAGON_F2_dfcmpgt",
+    "llvm.hexagon.F2.dfcmpuo" => "__builtin_HEXAGON_F2_dfcmpuo",
+    "llvm.hexagon.F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd",
+    "llvm.hexagon.F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn",
+    "llvm.hexagon.F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr",
+    "llvm.hexagon.F2.dffma" => "__builtin_HEXAGON_F2_dffma",
+    "llvm.hexagon.F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib",
+    "llvm.hexagon.F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc",
+    "llvm.hexagon.F2.dffms" => "__builtin_HEXAGON_F2_dffms",
+    "llvm.hexagon.F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib",
+    "llvm.hexagon.F2.dfimm.n" => "__builtin_HEXAGON_F2_dfimm_n",
+    "llvm.hexagon.F2.dfimm.p" => "__builtin_HEXAGON_F2_dfimm_p",
+    "llvm.hexagon.F2.dfmax" => "__builtin_HEXAGON_F2_dfmax",
+    "llvm.hexagon.F2.dfmin" => "__builtin_HEXAGON_F2_dfmin",
+    "llvm.hexagon.F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy",
+    "llvm.hexagon.F2.dfsub" => "__builtin_HEXAGON_F2_dfsub",
+    "llvm.hexagon.F2.sfadd" => "__builtin_HEXAGON_F2_sfadd",
+    "llvm.hexagon.F2.sfclass" => "__builtin_HEXAGON_F2_sfclass",
+    "llvm.hexagon.F2.sfcmpeq" => "__builtin_HEXAGON_F2_sfcmpeq",
+    "llvm.hexagon.F2.sfcmpge" => "__builtin_HEXAGON_F2_sfcmpge",
+    "llvm.hexagon.F2.sfcmpgt" => "__builtin_HEXAGON_F2_sfcmpgt",
+    "llvm.hexagon.F2.sfcmpuo" => "__builtin_HEXAGON_F2_sfcmpuo",
+    "llvm.hexagon.F2.sffixupd" => "__builtin_HEXAGON_F2_sffixupd",
+    "llvm.hexagon.F2.sffixupn" => "__builtin_HEXAGON_F2_sffixupn",
+    "llvm.hexagon.F2.sffixupr" => "__builtin_HEXAGON_F2_sffixupr",
+    "llvm.hexagon.F2.sffma" => "__builtin_HEXAGON_F2_sffma",
+    "llvm.hexagon.F2.sffma.lib" => "__builtin_HEXAGON_F2_sffma_lib",
+    "llvm.hexagon.F2.sffma.sc" => "__builtin_HEXAGON_F2_sffma_sc",
+    "llvm.hexagon.F2.sffms" => "__builtin_HEXAGON_F2_sffms",
+    "llvm.hexagon.F2.sffms.lib" => "__builtin_HEXAGON_F2_sffms_lib",
+    "llvm.hexagon.F2.sfimm.n" => "__builtin_HEXAGON_F2_sfimm_n",
+    "llvm.hexagon.F2.sfimm.p" => "__builtin_HEXAGON_F2_sfimm_p",
+    "llvm.hexagon.F2.sfmax" => "__builtin_HEXAGON_F2_sfmax",
+    "llvm.hexagon.F2.sfmin" => "__builtin_HEXAGON_F2_sfmin",
+    "llvm.hexagon.F2.sfmpy" => "__builtin_HEXAGON_F2_sfmpy",
+    "llvm.hexagon.F2.sfsub" => "__builtin_HEXAGON_F2_sfsub",
+    "llvm.hexagon.M2.acci" => "__builtin_HEXAGON_M2_acci",
+    "llvm.hexagon.M2.accii" => "__builtin_HEXAGON_M2_accii",
+    "llvm.hexagon.M2.cmaci.s0" => "__builtin_HEXAGON_M2_cmaci_s0",
+    "llvm.hexagon.M2.cmacr.s0" => "__builtin_HEXAGON_M2_cmacr_s0",
+    "llvm.hexagon.M2.cmacs.s0" => "__builtin_HEXAGON_M2_cmacs_s0",
+    "llvm.hexagon.M2.cmacs.s1" => "__builtin_HEXAGON_M2_cmacs_s1",
+    "llvm.hexagon.M2.cmacsc.s0" => "__builtin_HEXAGON_M2_cmacsc_s0",
+    "llvm.hexagon.M2.cmacsc.s1" => "__builtin_HEXAGON_M2_cmacsc_s1",
+    "llvm.hexagon.M2.cmpyi.s0" => "__builtin_HEXAGON_M2_cmpyi_s0",
+    "llvm.hexagon.M2.cmpyr.s0" => "__builtin_HEXAGON_M2_cmpyr_s0",
+    "llvm.hexagon.M2.cmpyrs.s0" => "__builtin_HEXAGON_M2_cmpyrs_s0",
+    "llvm.hexagon.M2.cmpyrs.s1" => "__builtin_HEXAGON_M2_cmpyrs_s1",
+    "llvm.hexagon.M2.cmpyrsc.s0" => "__builtin_HEXAGON_M2_cmpyrsc_s0",
+    "llvm.hexagon.M2.cmpyrsc.s1" => "__builtin_HEXAGON_M2_cmpyrsc_s1",
+    "llvm.hexagon.M2.cmpys.s0" => "__builtin_HEXAGON_M2_cmpys_s0",
+    "llvm.hexagon.M2.cmpys.s1" => "__builtin_HEXAGON_M2_cmpys_s1",
+    "llvm.hexagon.M2.cmpysc.s0" => "__builtin_HEXAGON_M2_cmpysc_s0",
+    "llvm.hexagon.M2.cmpysc.s1" => "__builtin_HEXAGON_M2_cmpysc_s1",
+    "llvm.hexagon.M2.cnacs.s0" => "__builtin_HEXAGON_M2_cnacs_s0",
+    "llvm.hexagon.M2.cnacs.s1" => "__builtin_HEXAGON_M2_cnacs_s1",
+    "llvm.hexagon.M2.cnacsc.s0" => "__builtin_HEXAGON_M2_cnacsc_s0",
+    "llvm.hexagon.M2.cnacsc.s1" => "__builtin_HEXAGON_M2_cnacsc_s1",
+    "llvm.hexagon.M2.dpmpyss.acc.s0" => "__builtin_HEXAGON_M2_dpmpyss_acc_s0",
+    "llvm.hexagon.M2.dpmpyss.nac.s0" => "__builtin_HEXAGON_M2_dpmpyss_nac_s0",
+    "llvm.hexagon.M2.dpmpyss.rnd.s0" => "__builtin_HEXAGON_M2_dpmpyss_rnd_s0",
+    "llvm.hexagon.M2.dpmpyss.s0" => "__builtin_HEXAGON_M2_dpmpyss_s0",
+    "llvm.hexagon.M2.dpmpyuu.acc.s0" => "__builtin_HEXAGON_M2_dpmpyuu_acc_s0",
+    "llvm.hexagon.M2.dpmpyuu.nac.s0" => "__builtin_HEXAGON_M2_dpmpyuu_nac_s0",
+    "llvm.hexagon.M2.dpmpyuu.s0" => "__builtin_HEXAGON_M2_dpmpyuu_s0",
+    "llvm.hexagon.M2.hmmpyh.rs1" => "__builtin_HEXAGON_M2_hmmpyh_rs1",
+    "llvm.hexagon.M2.hmmpyh.s1" => "__builtin_HEXAGON_M2_hmmpyh_s1",
+    "llvm.hexagon.M2.hmmpyl.rs1" => "__builtin_HEXAGON_M2_hmmpyl_rs1",
+    "llvm.hexagon.M2.hmmpyl.s1" => "__builtin_HEXAGON_M2_hmmpyl_s1",
+    "llvm.hexagon.M2.maci" => "__builtin_HEXAGON_M2_maci",
+    "llvm.hexagon.M2.macsin" => "__builtin_HEXAGON_M2_macsin",
+    "llvm.hexagon.M2.macsip" => "__builtin_HEXAGON_M2_macsip",
+    "llvm.hexagon.M2.mmachs.rs0" => "__builtin_HEXAGON_M2_mmachs_rs0",
+    "llvm.hexagon.M2.mmachs.rs1" => "__builtin_HEXAGON_M2_mmachs_rs1",
+    "llvm.hexagon.M2.mmachs.s0" => "__builtin_HEXAGON_M2_mmachs_s0",
+    "llvm.hexagon.M2.mmachs.s1" => "__builtin_HEXAGON_M2_mmachs_s1",
+    "llvm.hexagon.M2.mmacls.rs0" => "__builtin_HEXAGON_M2_mmacls_rs0",
+    "llvm.hexagon.M2.mmacls.rs1" => "__builtin_HEXAGON_M2_mmacls_rs1",
+    "llvm.hexagon.M2.mmacls.s0" => "__builtin_HEXAGON_M2_mmacls_s0",
+    "llvm.hexagon.M2.mmacls.s1" => "__builtin_HEXAGON_M2_mmacls_s1",
+    "llvm.hexagon.M2.mmacuhs.rs0" => "__builtin_HEXAGON_M2_mmacuhs_rs0",
+    "llvm.hexagon.M2.mmacuhs.rs1" => "__builtin_HEXAGON_M2_mmacuhs_rs1",
+    "llvm.hexagon.M2.mmacuhs.s0" => "__builtin_HEXAGON_M2_mmacuhs_s0",
+    "llvm.hexagon.M2.mmacuhs.s1" => "__builtin_HEXAGON_M2_mmacuhs_s1",
+    "llvm.hexagon.M2.mmaculs.rs0" => "__builtin_HEXAGON_M2_mmaculs_rs0",
+    "llvm.hexagon.M2.mmaculs.rs1" => "__builtin_HEXAGON_M2_mmaculs_rs1",
+    "llvm.hexagon.M2.mmaculs.s0" => "__builtin_HEXAGON_M2_mmaculs_s0",
+    "llvm.hexagon.M2.mmaculs.s1" => "__builtin_HEXAGON_M2_mmaculs_s1",
+    "llvm.hexagon.M2.mmpyh.rs0" => "__builtin_HEXAGON_M2_mmpyh_rs0",
+    "llvm.hexagon.M2.mmpyh.rs1" => "__builtin_HEXAGON_M2_mmpyh_rs1",
+    "llvm.hexagon.M2.mmpyh.s0" => "__builtin_HEXAGON_M2_mmpyh_s0",
+    "llvm.hexagon.M2.mmpyh.s1" => "__builtin_HEXAGON_M2_mmpyh_s1",
+    "llvm.hexagon.M2.mmpyl.rs0" => "__builtin_HEXAGON_M2_mmpyl_rs0",
+    "llvm.hexagon.M2.mmpyl.rs1" => "__builtin_HEXAGON_M2_mmpyl_rs1",
+    "llvm.hexagon.M2.mmpyl.s0" => "__builtin_HEXAGON_M2_mmpyl_s0",
+    "llvm.hexagon.M2.mmpyl.s1" => "__builtin_HEXAGON_M2_mmpyl_s1",
+    "llvm.hexagon.M2.mmpyuh.rs0" => "__builtin_HEXAGON_M2_mmpyuh_rs0",
+    "llvm.hexagon.M2.mmpyuh.rs1" => "__builtin_HEXAGON_M2_mmpyuh_rs1",
+    "llvm.hexagon.M2.mmpyuh.s0" => "__builtin_HEXAGON_M2_mmpyuh_s0",
+    "llvm.hexagon.M2.mmpyuh.s1" => "__builtin_HEXAGON_M2_mmpyuh_s1",
+    "llvm.hexagon.M2.mmpyul.rs0" => "__builtin_HEXAGON_M2_mmpyul_rs0",
+    "llvm.hexagon.M2.mmpyul.rs1" => "__builtin_HEXAGON_M2_mmpyul_rs1",
+    "llvm.hexagon.M2.mmpyul.s0" => "__builtin_HEXAGON_M2_mmpyul_s0",
+    "llvm.hexagon.M2.mmpyul.s1" => "__builtin_HEXAGON_M2_mmpyul_s1",
+    "llvm.hexagon.M2.mpy.acc.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_hh_s0",
+    "llvm.hexagon.M2.mpy.acc.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_hh_s1",
+    "llvm.hexagon.M2.mpy.acc.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_hl_s0",
+    "llvm.hexagon.M2.mpy.acc.hl.s1" => "__builtin_HEXAGON_M2_mpy_acc_hl_s1",
+    "llvm.hexagon.M2.mpy.acc.lh.s0" => "__builtin_HEXAGON_M2_mpy_acc_lh_s0",
+    "llvm.hexagon.M2.mpy.acc.lh.s1" => "__builtin_HEXAGON_M2_mpy_acc_lh_s1",
+    "llvm.hexagon.M2.mpy.acc.ll.s0" => "__builtin_HEXAGON_M2_mpy_acc_ll_s0",
+    "llvm.hexagon.M2.mpy.acc.ll.s1" => "__builtin_HEXAGON_M2_mpy_acc_ll_s1",
+    "llvm.hexagon.M2.mpy.acc.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0",
+    "llvm.hexagon.M2.mpy.acc.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1",
+    "llvm.hexagon.M2.mpy.acc.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0",
+    "llvm.hexagon.M2.mpy.acc.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1",
+    "llvm.hexagon.M2.mpy.acc.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0",
+    "llvm.hexagon.M2.mpy.acc.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1",
+    "llvm.hexagon.M2.mpy.acc.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0",
+    "llvm.hexagon.M2.mpy.acc.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1",
+    "llvm.hexagon.M2.mpy.hh.s0" => "__builtin_HEXAGON_M2_mpy_hh_s0",
+    "llvm.hexagon.M2.mpy.hh.s1" => "__builtin_HEXAGON_M2_mpy_hh_s1",
+    "llvm.hexagon.M2.mpy.hl.s0" => "__builtin_HEXAGON_M2_mpy_hl_s0",
+    "llvm.hexagon.M2.mpy.hl.s1" => "__builtin_HEXAGON_M2_mpy_hl_s1",
+    "llvm.hexagon.M2.mpy.lh.s0" => "__builtin_HEXAGON_M2_mpy_lh_s0",
+    "llvm.hexagon.M2.mpy.lh.s1" => "__builtin_HEXAGON_M2_mpy_lh_s1",
+    "llvm.hexagon.M2.mpy.ll.s0" => "__builtin_HEXAGON_M2_mpy_ll_s0",
+    "llvm.hexagon.M2.mpy.ll.s1" => "__builtin_HEXAGON_M2_mpy_ll_s1",
+    "llvm.hexagon.M2.mpy.nac.hh.s0" => "__builtin_HEXAGON_M2_mpy_nac_hh_s0",
+    "llvm.hexagon.M2.mpy.nac.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_hh_s1",
+    "llvm.hexagon.M2.mpy.nac.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_hl_s0",
+    "llvm.hexagon.M2.mpy.nac.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_hl_s1",
+    "llvm.hexagon.M2.mpy.nac.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_lh_s0",
+    "llvm.hexagon.M2.mpy.nac.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_lh_s1",
+    "llvm.hexagon.M2.mpy.nac.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_ll_s0",
+    "llvm.hexagon.M2.mpy.nac.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_ll_s1",
+    "llvm.hexagon.M2.mpy.nac.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0",
+    "llvm.hexagon.M2.mpy.nac.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1",
+    "llvm.hexagon.M2.mpy.nac.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0",
+    "llvm.hexagon.M2.mpy.nac.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1",
+    "llvm.hexagon.M2.mpy.nac.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0",
+    "llvm.hexagon.M2.mpy.nac.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1",
+    "llvm.hexagon.M2.mpy.nac.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0",
+    "llvm.hexagon.M2.mpy.nac.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1",
+    "llvm.hexagon.M2.mpy.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s0",
+    "llvm.hexagon.M2.mpy.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s1",
+    "llvm.hexagon.M2.mpy.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s0",
+    "llvm.hexagon.M2.mpy.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s1",
+    "llvm.hexagon.M2.mpy.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s0",
+    "llvm.hexagon.M2.mpy.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s1",
+    "llvm.hexagon.M2.mpy.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s0",
+    "llvm.hexagon.M2.mpy.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s1",
+    "llvm.hexagon.M2.mpy.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_hh_s0",
+    "llvm.hexagon.M2.mpy.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_hh_s1",
+    "llvm.hexagon.M2.mpy.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_hl_s0",
+    "llvm.hexagon.M2.mpy.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_hl_s1",
+    "llvm.hexagon.M2.mpy.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_lh_s0",
+    "llvm.hexagon.M2.mpy.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_lh_s1",
+    "llvm.hexagon.M2.mpy.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_ll_s0",
+    "llvm.hexagon.M2.mpy.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_ll_s1",
+    "llvm.hexagon.M2.mpy.sat.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0",
+    "llvm.hexagon.M2.mpy.sat.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1",
+    "llvm.hexagon.M2.mpy.sat.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0",
+    "llvm.hexagon.M2.mpy.sat.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1",
+    "llvm.hexagon.M2.mpy.sat.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0",
+    "llvm.hexagon.M2.mpy.sat.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1",
+    "llvm.hexagon.M2.mpy.sat.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0",
+    "llvm.hexagon.M2.mpy.sat.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1",
+    "llvm.hexagon.M2.mpy.up" => "__builtin_HEXAGON_M2_mpy_up",
+    "llvm.hexagon.M2.mpy.up.s1" => "__builtin_HEXAGON_M2_mpy_up_s1",
+    "llvm.hexagon.M2.mpy.up.s1.sat" => "__builtin_HEXAGON_M2_mpy_up_s1_sat",
+    "llvm.hexagon.M2.mpyd.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s0",
+    "llvm.hexagon.M2.mpyd.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s1",
+    "llvm.hexagon.M2.mpyd.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s0",
+    "llvm.hexagon.M2.mpyd.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s1",
+    "llvm.hexagon.M2.mpyd.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s0",
+    "llvm.hexagon.M2.mpyd.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s1",
+    "llvm.hexagon.M2.mpyd.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s0",
+    "llvm.hexagon.M2.mpyd.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s1",
+    "llvm.hexagon.M2.mpyd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_hh_s0",
+    "llvm.hexagon.M2.mpyd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_hh_s1",
+    "llvm.hexagon.M2.mpyd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_hl_s0",
+    "llvm.hexagon.M2.mpyd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_hl_s1",
+    "llvm.hexagon.M2.mpyd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_lh_s0",
+    "llvm.hexagon.M2.mpyd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_lh_s1",
+    "llvm.hexagon.M2.mpyd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_ll_s0",
+    "llvm.hexagon.M2.mpyd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_ll_s1",
+    "llvm.hexagon.M2.mpyd.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s0",
+    "llvm.hexagon.M2.mpyd.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s1",
+    "llvm.hexagon.M2.mpyd.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s0",
+    "llvm.hexagon.M2.mpyd.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s1",
+    "llvm.hexagon.M2.mpyd.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s0",
+    "llvm.hexagon.M2.mpyd.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s1",
+    "llvm.hexagon.M2.mpyd.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s0",
+    "llvm.hexagon.M2.mpyd.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s1",
+    "llvm.hexagon.M2.mpyd.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s0",
+    "llvm.hexagon.M2.mpyd.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s1",
+    "llvm.hexagon.M2.mpyd.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s0",
+    "llvm.hexagon.M2.mpyd.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s1",
+    "llvm.hexagon.M2.mpyd.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s0",
+    "llvm.hexagon.M2.mpyd.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s1",
+    "llvm.hexagon.M2.mpyd.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s0",
+    "llvm.hexagon.M2.mpyd.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s1",
+    "llvm.hexagon.M2.mpyi" => "__builtin_HEXAGON_M2_mpyi",
+    "llvm.hexagon.M2.mpysmi" => "__builtin_HEXAGON_M2_mpysmi",
+    "llvm.hexagon.M2.mpysu.up" => "__builtin_HEXAGON_M2_mpysu_up",
+    "llvm.hexagon.M2.mpyu.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s0",
+    "llvm.hexagon.M2.mpyu.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s1",
+    "llvm.hexagon.M2.mpyu.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s0",
+    "llvm.hexagon.M2.mpyu.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s1",
+    "llvm.hexagon.M2.mpyu.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s0",
+    "llvm.hexagon.M2.mpyu.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s1",
+    "llvm.hexagon.M2.mpyu.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s0",
+    "llvm.hexagon.M2.mpyu.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s1",
+    "llvm.hexagon.M2.mpyu.hh.s0" => "__builtin_HEXAGON_M2_mpyu_hh_s0",
+    "llvm.hexagon.M2.mpyu.hh.s1" => "__builtin_HEXAGON_M2_mpyu_hh_s1",
+    "llvm.hexagon.M2.mpyu.hl.s0" => "__builtin_HEXAGON_M2_mpyu_hl_s0",
+    "llvm.hexagon.M2.mpyu.hl.s1" => "__builtin_HEXAGON_M2_mpyu_hl_s1",
+    "llvm.hexagon.M2.mpyu.lh.s0" => "__builtin_HEXAGON_M2_mpyu_lh_s0",
+    "llvm.hexagon.M2.mpyu.lh.s1" => "__builtin_HEXAGON_M2_mpyu_lh_s1",
+    "llvm.hexagon.M2.mpyu.ll.s0" => "__builtin_HEXAGON_M2_mpyu_ll_s0",
+    "llvm.hexagon.M2.mpyu.ll.s1" => "__builtin_HEXAGON_M2_mpyu_ll_s1",
+    "llvm.hexagon.M2.mpyu.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s0",
+    "llvm.hexagon.M2.mpyu.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s1",
+    "llvm.hexagon.M2.mpyu.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s0",
+    "llvm.hexagon.M2.mpyu.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s1",
+    "llvm.hexagon.M2.mpyu.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s0",
+    "llvm.hexagon.M2.mpyu.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s1",
+    "llvm.hexagon.M2.mpyu.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s0",
+    "llvm.hexagon.M2.mpyu.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s1",
+    "llvm.hexagon.M2.mpyu.up" => "__builtin_HEXAGON_M2_mpyu_up",
+    "llvm.hexagon.M2.mpyud.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s0",
+    "llvm.hexagon.M2.mpyud.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s1",
+    "llvm.hexagon.M2.mpyud.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s0",
+    "llvm.hexagon.M2.mpyud.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s1",
+    "llvm.hexagon.M2.mpyud.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s0",
+    "llvm.hexagon.M2.mpyud.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s1",
+    "llvm.hexagon.M2.mpyud.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s0",
+    "llvm.hexagon.M2.mpyud.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s1",
+    "llvm.hexagon.M2.mpyud.hh.s0" => "__builtin_HEXAGON_M2_mpyud_hh_s0",
+    "llvm.hexagon.M2.mpyud.hh.s1" => "__builtin_HEXAGON_M2_mpyud_hh_s1",
+    "llvm.hexagon.M2.mpyud.hl.s0" => "__builtin_HEXAGON_M2_mpyud_hl_s0",
+    "llvm.hexagon.M2.mpyud.hl.s1" => "__builtin_HEXAGON_M2_mpyud_hl_s1",
+    "llvm.hexagon.M2.mpyud.lh.s0" => "__builtin_HEXAGON_M2_mpyud_lh_s0",
+    "llvm.hexagon.M2.mpyud.lh.s1" => "__builtin_HEXAGON_M2_mpyud_lh_s1",
+    "llvm.hexagon.M2.mpyud.ll.s0" => "__builtin_HEXAGON_M2_mpyud_ll_s0",
+    "llvm.hexagon.M2.mpyud.ll.s1" => "__builtin_HEXAGON_M2_mpyud_ll_s1",
+    "llvm.hexagon.M2.mpyud.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s0",
+    "llvm.hexagon.M2.mpyud.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s1",
+    "llvm.hexagon.M2.mpyud.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s0",
+    "llvm.hexagon.M2.mpyud.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s1",
+    "llvm.hexagon.M2.mpyud.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s0",
+    "llvm.hexagon.M2.mpyud.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s1",
+    "llvm.hexagon.M2.mpyud.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s0",
+    "llvm.hexagon.M2.mpyud.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s1",
+    "llvm.hexagon.M2.mpyui" => "__builtin_HEXAGON_M2_mpyui",
+    "llvm.hexagon.M2.nacci" => "__builtin_HEXAGON_M2_nacci",
+    "llvm.hexagon.M2.naccii" => "__builtin_HEXAGON_M2_naccii",
+    "llvm.hexagon.M2.subacc" => "__builtin_HEXAGON_M2_subacc",
+    "llvm.hexagon.M2.vabsdiffh" => "__builtin_HEXAGON_M2_vabsdiffh",
+    "llvm.hexagon.M2.vabsdiffw" => "__builtin_HEXAGON_M2_vabsdiffw",
+    "llvm.hexagon.M2.vcmac.s0.sat.i" => "__builtin_HEXAGON_M2_vcmac_s0_sat_i",
+    "llvm.hexagon.M2.vcmac.s0.sat.r" => "__builtin_HEXAGON_M2_vcmac_s0_sat_r",
+    "llvm.hexagon.M2.vcmpy.s0.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_i",
+    "llvm.hexagon.M2.vcmpy.s0.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_r",
+    "llvm.hexagon.M2.vcmpy.s1.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_i",
+    "llvm.hexagon.M2.vcmpy.s1.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_r",
+    "llvm.hexagon.M2.vdmacs.s0" => "__builtin_HEXAGON_M2_vdmacs_s0",
+    "llvm.hexagon.M2.vdmacs.s1" => "__builtin_HEXAGON_M2_vdmacs_s1",
+    "llvm.hexagon.M2.vdmpyrs.s0" => "__builtin_HEXAGON_M2_vdmpyrs_s0",
+    "llvm.hexagon.M2.vdmpyrs.s1" => "__builtin_HEXAGON_M2_vdmpyrs_s1",
+    "llvm.hexagon.M2.vdmpys.s0" => "__builtin_HEXAGON_M2_vdmpys_s0",
+    "llvm.hexagon.M2.vdmpys.s1" => "__builtin_HEXAGON_M2_vdmpys_s1",
+    "llvm.hexagon.M2.vmac2" => "__builtin_HEXAGON_M2_vmac2",
+    "llvm.hexagon.M2.vmac2es" => "__builtin_HEXAGON_M2_vmac2es",
+    "llvm.hexagon.M2.vmac2es.s0" => "__builtin_HEXAGON_M2_vmac2es_s0",
+    "llvm.hexagon.M2.vmac2es.s1" => "__builtin_HEXAGON_M2_vmac2es_s1",
+    "llvm.hexagon.M2.vmac2s.s0" => "__builtin_HEXAGON_M2_vmac2s_s0",
+    "llvm.hexagon.M2.vmac2s.s1" => "__builtin_HEXAGON_M2_vmac2s_s1",
+    "llvm.hexagon.M2.vmac2su.s0" => "__builtin_HEXAGON_M2_vmac2su_s0",
+    "llvm.hexagon.M2.vmac2su.s1" => "__builtin_HEXAGON_M2_vmac2su_s1",
+    "llvm.hexagon.M2.vmpy2es.s0" => "__builtin_HEXAGON_M2_vmpy2es_s0",
+    "llvm.hexagon.M2.vmpy2es.s1" => "__builtin_HEXAGON_M2_vmpy2es_s1",
+    "llvm.hexagon.M2.vmpy2s.s0" => "__builtin_HEXAGON_M2_vmpy2s_s0",
+    "llvm.hexagon.M2.vmpy2s.s0pack" => "__builtin_HEXAGON_M2_vmpy2s_s0pack",
+    "llvm.hexagon.M2.vmpy2s.s1" => "__builtin_HEXAGON_M2_vmpy2s_s1",
+    "llvm.hexagon.M2.vmpy2s.s1pack" => "__builtin_HEXAGON_M2_vmpy2s_s1pack",
+    "llvm.hexagon.M2.vmpy2su.s0" => "__builtin_HEXAGON_M2_vmpy2su_s0",
+    "llvm.hexagon.M2.vmpy2su.s1" => "__builtin_HEXAGON_M2_vmpy2su_s1",
+    "llvm.hexagon.M2.vraddh" => "__builtin_HEXAGON_M2_vraddh",
+    "llvm.hexagon.M2.vradduh" => "__builtin_HEXAGON_M2_vradduh",
+    "llvm.hexagon.M2.vrcmaci.s0" => "__builtin_HEXAGON_M2_vrcmaci_s0",
+    "llvm.hexagon.M2.vrcmaci.s0c" => "__builtin_HEXAGON_M2_vrcmaci_s0c",
+    "llvm.hexagon.M2.vrcmacr.s0" => "__builtin_HEXAGON_M2_vrcmacr_s0",
+    "llvm.hexagon.M2.vrcmacr.s0c" => "__builtin_HEXAGON_M2_vrcmacr_s0c",
+    "llvm.hexagon.M2.vrcmpyi.s0" => "__builtin_HEXAGON_M2_vrcmpyi_s0",
+    "llvm.hexagon.M2.vrcmpyi.s0c" => "__builtin_HEXAGON_M2_vrcmpyi_s0c",
+    "llvm.hexagon.M2.vrcmpyr.s0" => "__builtin_HEXAGON_M2_vrcmpyr_s0",
+    "llvm.hexagon.M2.vrcmpyr.s0c" => "__builtin_HEXAGON_M2_vrcmpyr_s0c",
+    "llvm.hexagon.M2.vrcmpys.acc.s1" => "__builtin_HEXAGON_M2_vrcmpys_acc_s1",
+    "llvm.hexagon.M2.vrcmpys.s1" => "__builtin_HEXAGON_M2_vrcmpys_s1",
+    "llvm.hexagon.M2.vrcmpys.s1rp" => "__builtin_HEXAGON_M2_vrcmpys_s1rp",
+    "llvm.hexagon.M2.vrmac.s0" => "__builtin_HEXAGON_M2_vrmac_s0",
+    "llvm.hexagon.M2.vrmpy.s0" => "__builtin_HEXAGON_M2_vrmpy_s0",
+    "llvm.hexagon.M2.xor.xacc" => "__builtin_HEXAGON_M2_xor_xacc",
+    "llvm.hexagon.M4.and.and" => "__builtin_HEXAGON_M4_and_and",
+    "llvm.hexagon.M4.and.andn" => "__builtin_HEXAGON_M4_and_andn",
+    "llvm.hexagon.M4.and.or" => "__builtin_HEXAGON_M4_and_or",
+    "llvm.hexagon.M4.and.xor" => "__builtin_HEXAGON_M4_and_xor",
+    "llvm.hexagon.M4.cmpyi.wh" => "__builtin_HEXAGON_M4_cmpyi_wh",
+    "llvm.hexagon.M4.cmpyi.whc" => "__builtin_HEXAGON_M4_cmpyi_whc",
+    "llvm.hexagon.M4.cmpyr.wh" => "__builtin_HEXAGON_M4_cmpyr_wh",
+    "llvm.hexagon.M4.cmpyr.whc" => "__builtin_HEXAGON_M4_cmpyr_whc",
+    "llvm.hexagon.M4.mac.up.s1.sat" => "__builtin_HEXAGON_M4_mac_up_s1_sat",
+    "llvm.hexagon.M4.mpyri.addi" => "__builtin_HEXAGON_M4_mpyri_addi",
+    "llvm.hexagon.M4.mpyri.addr" => "__builtin_HEXAGON_M4_mpyri_addr",
+    "llvm.hexagon.M4.mpyri.addr.u2" => "__builtin_HEXAGON_M4_mpyri_addr_u2",
+    "llvm.hexagon.M4.mpyrr.addi" => "__builtin_HEXAGON_M4_mpyrr_addi",
+    "llvm.hexagon.M4.mpyrr.addr" => "__builtin_HEXAGON_M4_mpyrr_addr",
+    "llvm.hexagon.M4.nac.up.s1.sat" => "__builtin_HEXAGON_M4_nac_up_s1_sat",
+    "llvm.hexagon.M4.or.and" => "__builtin_HEXAGON_M4_or_and",
+    "llvm.hexagon.M4.or.andn" => "__builtin_HEXAGON_M4_or_andn",
+    "llvm.hexagon.M4.or.or" => "__builtin_HEXAGON_M4_or_or",
+    "llvm.hexagon.M4.or.xor" => "__builtin_HEXAGON_M4_or_xor",
+    "llvm.hexagon.M4.pmpyw" => "__builtin_HEXAGON_M4_pmpyw",
+    "llvm.hexagon.M4.pmpyw.acc" => "__builtin_HEXAGON_M4_pmpyw_acc",
+    "llvm.hexagon.M4.vpmpyh" => "__builtin_HEXAGON_M4_vpmpyh",
+    "llvm.hexagon.M4.vpmpyh.acc" => "__builtin_HEXAGON_M4_vpmpyh_acc",
+    "llvm.hexagon.M4.vrmpyeh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s0",
+    "llvm.hexagon.M4.vrmpyeh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s1",
+    "llvm.hexagon.M4.vrmpyeh.s0" => "__builtin_HEXAGON_M4_vrmpyeh_s0",
+    "llvm.hexagon.M4.vrmpyeh.s1" => "__builtin_HEXAGON_M4_vrmpyeh_s1",
+    "llvm.hexagon.M4.vrmpyoh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s0",
+    "llvm.hexagon.M4.vrmpyoh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s1",
+    "llvm.hexagon.M4.vrmpyoh.s0" => "__builtin_HEXAGON_M4_vrmpyoh_s0",
+    "llvm.hexagon.M4.vrmpyoh.s1" => "__builtin_HEXAGON_M4_vrmpyoh_s1",
+    "llvm.hexagon.M4.xor.and" => "__builtin_HEXAGON_M4_xor_and",
+    "llvm.hexagon.M4.xor.andn" => "__builtin_HEXAGON_M4_xor_andn",
+    "llvm.hexagon.M4.xor.or" => "__builtin_HEXAGON_M4_xor_or",
+    "llvm.hexagon.M4.xor.xacc" => "__builtin_HEXAGON_M4_xor_xacc",
+    "llvm.hexagon.M5.vdmacbsu" => "__builtin_HEXAGON_M5_vdmacbsu",
+    "llvm.hexagon.M5.vdmpybsu" => "__builtin_HEXAGON_M5_vdmpybsu",
+    "llvm.hexagon.M5.vmacbsu" => "__builtin_HEXAGON_M5_vmacbsu",
+    "llvm.hexagon.M5.vmacbuu" => "__builtin_HEXAGON_M5_vmacbuu",
+    "llvm.hexagon.M5.vmpybsu" => "__builtin_HEXAGON_M5_vmpybsu",
+    "llvm.hexagon.M5.vmpybuu" => "__builtin_HEXAGON_M5_vmpybuu",
+    "llvm.hexagon.M5.vrmacbsu" => "__builtin_HEXAGON_M5_vrmacbsu",
+    "llvm.hexagon.M5.vrmacbuu" => "__builtin_HEXAGON_M5_vrmacbuu",
+    "llvm.hexagon.M5.vrmpybsu" => "__builtin_HEXAGON_M5_vrmpybsu",
+    "llvm.hexagon.M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu",
+    "llvm.hexagon.M6.vabsdiffb" => "__builtin_HEXAGON_M6_vabsdiffb",
+    "llvm.hexagon.M6.vabsdiffub" => "__builtin_HEXAGON_M6_vabsdiffub",
+    "llvm.hexagon.S2.addasl.rrri" => "__builtin_HEXAGON_S2_addasl_rrri",
+    "llvm.hexagon.S2.asl.i.p" => "__builtin_HEXAGON_S2_asl_i_p",
+    "llvm.hexagon.S2.asl.i.p.acc" => "__builtin_HEXAGON_S2_asl_i_p_acc",
+    "llvm.hexagon.S2.asl.i.p.and" => "__builtin_HEXAGON_S2_asl_i_p_and",
+    "llvm.hexagon.S2.asl.i.p.nac" => "__builtin_HEXAGON_S2_asl_i_p_nac",
+    "llvm.hexagon.S2.asl.i.p.or" => "__builtin_HEXAGON_S2_asl_i_p_or",
+    "llvm.hexagon.S2.asl.i.p.xacc" => "__builtin_HEXAGON_S2_asl_i_p_xacc",
+    "llvm.hexagon.S2.asl.i.r" => "__builtin_HEXAGON_S2_asl_i_r",
+    "llvm.hexagon.S2.asl.i.r.acc" => "__builtin_HEXAGON_S2_asl_i_r_acc",
+    "llvm.hexagon.S2.asl.i.r.and" => "__builtin_HEXAGON_S2_asl_i_r_and",
+    "llvm.hexagon.S2.asl.i.r.nac" => "__builtin_HEXAGON_S2_asl_i_r_nac",
+    "llvm.hexagon.S2.asl.i.r.or" => "__builtin_HEXAGON_S2_asl_i_r_or",
+    "llvm.hexagon.S2.asl.i.r.sat" => "__builtin_HEXAGON_S2_asl_i_r_sat",
+    "llvm.hexagon.S2.asl.i.r.xacc" => "__builtin_HEXAGON_S2_asl_i_r_xacc",
+    "llvm.hexagon.S2.asl.i.vh" => "__builtin_HEXAGON_S2_asl_i_vh",
+    "llvm.hexagon.S2.asl.i.vw" => "__builtin_HEXAGON_S2_asl_i_vw",
+    "llvm.hexagon.S2.asl.r.p" => "__builtin_HEXAGON_S2_asl_r_p",
+    "llvm.hexagon.S2.asl.r.p.acc" => "__builtin_HEXAGON_S2_asl_r_p_acc",
+    "llvm.hexagon.S2.asl.r.p.and" => "__builtin_HEXAGON_S2_asl_r_p_and",
+    "llvm.hexagon.S2.asl.r.p.nac" => "__builtin_HEXAGON_S2_asl_r_p_nac",
+    "llvm.hexagon.S2.asl.r.p.or" => "__builtin_HEXAGON_S2_asl_r_p_or",
+    "llvm.hexagon.S2.asl.r.p.xor" => "__builtin_HEXAGON_S2_asl_r_p_xor",
+    "llvm.hexagon.S2.asl.r.r" => "__builtin_HEXAGON_S2_asl_r_r",
+    "llvm.hexagon.S2.asl.r.r.acc" => "__builtin_HEXAGON_S2_asl_r_r_acc",
+    "llvm.hexagon.S2.asl.r.r.and" => "__builtin_HEXAGON_S2_asl_r_r_and",
+    "llvm.hexagon.S2.asl.r.r.nac" => "__builtin_HEXAGON_S2_asl_r_r_nac",
+    "llvm.hexagon.S2.asl.r.r.or" => "__builtin_HEXAGON_S2_asl_r_r_or",
+    "llvm.hexagon.S2.asl.r.r.sat" => "__builtin_HEXAGON_S2_asl_r_r_sat",
+    "llvm.hexagon.S2.asl.r.vh" => "__builtin_HEXAGON_S2_asl_r_vh",
+    "llvm.hexagon.S2.asl.r.vw" => "__builtin_HEXAGON_S2_asl_r_vw",
+    "llvm.hexagon.S2.asr.i.p" => "__builtin_HEXAGON_S2_asr_i_p",
+    "llvm.hexagon.S2.asr.i.p.acc" => "__builtin_HEXAGON_S2_asr_i_p_acc",
+    "llvm.hexagon.S2.asr.i.p.and" => "__builtin_HEXAGON_S2_asr_i_p_and",
+    "llvm.hexagon.S2.asr.i.p.nac" => "__builtin_HEXAGON_S2_asr_i_p_nac",
+    "llvm.hexagon.S2.asr.i.p.or" => "__builtin_HEXAGON_S2_asr_i_p_or",
+    "llvm.hexagon.S2.asr.i.p.rnd" => "__builtin_HEXAGON_S2_asr_i_p_rnd",
+    "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax",
+    "llvm.hexagon.S2.asr.i.r" => "__builtin_HEXAGON_S2_asr_i_r",
+    "llvm.hexagon.S2.asr.i.r.acc" => "__builtin_HEXAGON_S2_asr_i_r_acc",
+    "llvm.hexagon.S2.asr.i.r.and" => "__builtin_HEXAGON_S2_asr_i_r_and",
+    "llvm.hexagon.S2.asr.i.r.nac" => "__builtin_HEXAGON_S2_asr_i_r_nac",
+    "llvm.hexagon.S2.asr.i.r.or" => "__builtin_HEXAGON_S2_asr_i_r_or",
+    "llvm.hexagon.S2.asr.i.r.rnd" => "__builtin_HEXAGON_S2_asr_i_r_rnd",
+    "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax",
+    "llvm.hexagon.S2.asr.i.svw.trun" => "__builtin_HEXAGON_S2_asr_i_svw_trun",
+    "llvm.hexagon.S2.asr.i.vh" => "__builtin_HEXAGON_S2_asr_i_vh",
+    "llvm.hexagon.S2.asr.i.vw" => "__builtin_HEXAGON_S2_asr_i_vw",
+    "llvm.hexagon.S2.asr.r.p" => "__builtin_HEXAGON_S2_asr_r_p",
+    "llvm.hexagon.S2.asr.r.p.acc" => "__builtin_HEXAGON_S2_asr_r_p_acc",
+    "llvm.hexagon.S2.asr.r.p.and" => "__builtin_HEXAGON_S2_asr_r_p_and",
+    "llvm.hexagon.S2.asr.r.p.nac" => "__builtin_HEXAGON_S2_asr_r_p_nac",
+    "llvm.hexagon.S2.asr.r.p.or" => "__builtin_HEXAGON_S2_asr_r_p_or",
+    "llvm.hexagon.S2.asr.r.p.xor" => "__builtin_HEXAGON_S2_asr_r_p_xor",
+    "llvm.hexagon.S2.asr.r.r" => "__builtin_HEXAGON_S2_asr_r_r",
+    "llvm.hexagon.S2.asr.r.r.acc" => "__builtin_HEXAGON_S2_asr_r_r_acc",
+    "llvm.hexagon.S2.asr.r.r.and" => "__builtin_HEXAGON_S2_asr_r_r_and",
+    "llvm.hexagon.S2.asr.r.r.nac" => "__builtin_HEXAGON_S2_asr_r_r_nac",
+    "llvm.hexagon.S2.asr.r.r.or" => "__builtin_HEXAGON_S2_asr_r_r_or",
+    "llvm.hexagon.S2.asr.r.r.sat" => "__builtin_HEXAGON_S2_asr_r_r_sat",
+    "llvm.hexagon.S2.asr.r.svw.trun" => "__builtin_HEXAGON_S2_asr_r_svw_trun",
+    "llvm.hexagon.S2.asr.r.vh" => "__builtin_HEXAGON_S2_asr_r_vh",
+    "llvm.hexagon.S2.asr.r.vw" => "__builtin_HEXAGON_S2_asr_r_vw",
+    "llvm.hexagon.S2.brev" => "__builtin_HEXAGON_S2_brev",
+    "llvm.hexagon.S2.brevp" => "__builtin_HEXAGON_S2_brevp",
+    "llvm.hexagon.S2.cabacencbin" => "__builtin_HEXAGON_S2_cabacencbin",
+    "llvm.hexagon.S2.cl0" => "__builtin_HEXAGON_S2_cl0",
+    "llvm.hexagon.S2.cl0p" => "__builtin_HEXAGON_S2_cl0p",
+    "llvm.hexagon.S2.cl1" => "__builtin_HEXAGON_S2_cl1",
+    "llvm.hexagon.S2.cl1p" => "__builtin_HEXAGON_S2_cl1p",
+    "llvm.hexagon.S2.clb" => "__builtin_HEXAGON_S2_clb",
+    "llvm.hexagon.S2.clbnorm" => "__builtin_HEXAGON_S2_clbnorm",
+    "llvm.hexagon.S2.clbp" => "__builtin_HEXAGON_S2_clbp",
+    "llvm.hexagon.S2.clrbit.i" => "__builtin_HEXAGON_S2_clrbit_i",
+    "llvm.hexagon.S2.clrbit.r" => "__builtin_HEXAGON_S2_clrbit_r",
+    "llvm.hexagon.S2.ct0" => "__builtin_HEXAGON_S2_ct0",
+    "llvm.hexagon.S2.ct0p" => "__builtin_HEXAGON_S2_ct0p",
+    "llvm.hexagon.S2.ct1" => "__builtin_HEXAGON_S2_ct1",
+    "llvm.hexagon.S2.ct1p" => "__builtin_HEXAGON_S2_ct1p",
+    "llvm.hexagon.S2.deinterleave" => "__builtin_HEXAGON_S2_deinterleave",
+    "llvm.hexagon.S2.extractu" => "__builtin_HEXAGON_S2_extractu",
+    "llvm.hexagon.S2.extractu.rp" => "__builtin_HEXAGON_S2_extractu_rp",
+    "llvm.hexagon.S2.extractup" => "__builtin_HEXAGON_S2_extractup",
+    "llvm.hexagon.S2.extractup.rp" => "__builtin_HEXAGON_S2_extractup_rp",
+    "llvm.hexagon.S2.insert" => "__builtin_HEXAGON_S2_insert",
+    "llvm.hexagon.S2.insert.rp" => "__builtin_HEXAGON_S2_insert_rp",
+    "llvm.hexagon.S2.insertp" => "__builtin_HEXAGON_S2_insertp",
+    "llvm.hexagon.S2.insertp.rp" => "__builtin_HEXAGON_S2_insertp_rp",
+    "llvm.hexagon.S2.interleave" => "__builtin_HEXAGON_S2_interleave",
+    "llvm.hexagon.S2.lfsp" => "__builtin_HEXAGON_S2_lfsp",
+    "llvm.hexagon.S2.lsl.r.p" => "__builtin_HEXAGON_S2_lsl_r_p",
+    "llvm.hexagon.S2.lsl.r.p.acc" => "__builtin_HEXAGON_S2_lsl_r_p_acc",
+    "llvm.hexagon.S2.lsl.r.p.and" => "__builtin_HEXAGON_S2_lsl_r_p_and",
+    "llvm.hexagon.S2.lsl.r.p.nac" => "__builtin_HEXAGON_S2_lsl_r_p_nac",
+    "llvm.hexagon.S2.lsl.r.p.or" => "__builtin_HEXAGON_S2_lsl_r_p_or",
+    "llvm.hexagon.S2.lsl.r.p.xor" => "__builtin_HEXAGON_S2_lsl_r_p_xor",
+    "llvm.hexagon.S2.lsl.r.r" => "__builtin_HEXAGON_S2_lsl_r_r",
+    "llvm.hexagon.S2.lsl.r.r.acc" => "__builtin_HEXAGON_S2_lsl_r_r_acc",
+    "llvm.hexagon.S2.lsl.r.r.and" => "__builtin_HEXAGON_S2_lsl_r_r_and",
+    "llvm.hexagon.S2.lsl.r.r.nac" => "__builtin_HEXAGON_S2_lsl_r_r_nac",
+    "llvm.hexagon.S2.lsl.r.r.or" => "__builtin_HEXAGON_S2_lsl_r_r_or",
+    "llvm.hexagon.S2.lsl.r.vh" => "__builtin_HEXAGON_S2_lsl_r_vh",
+    "llvm.hexagon.S2.lsl.r.vw" => "__builtin_HEXAGON_S2_lsl_r_vw",
+    "llvm.hexagon.S2.lsr.i.p" => "__builtin_HEXAGON_S2_lsr_i_p",
+    "llvm.hexagon.S2.lsr.i.p.acc" => "__builtin_HEXAGON_S2_lsr_i_p_acc",
+    "llvm.hexagon.S2.lsr.i.p.and" => "__builtin_HEXAGON_S2_lsr_i_p_and",
+    "llvm.hexagon.S2.lsr.i.p.nac" => "__builtin_HEXAGON_S2_lsr_i_p_nac",
+    "llvm.hexagon.S2.lsr.i.p.or" => "__builtin_HEXAGON_S2_lsr_i_p_or",
+    "llvm.hexagon.S2.lsr.i.p.xacc" => "__builtin_HEXAGON_S2_lsr_i_p_xacc",
+    "llvm.hexagon.S2.lsr.i.r" => "__builtin_HEXAGON_S2_lsr_i_r",
+    "llvm.hexagon.S2.lsr.i.r.acc" => "__builtin_HEXAGON_S2_lsr_i_r_acc",
+    "llvm.hexagon.S2.lsr.i.r.and" => "__builtin_HEXAGON_S2_lsr_i_r_and",
+    "llvm.hexagon.S2.lsr.i.r.nac" => "__builtin_HEXAGON_S2_lsr_i_r_nac",
+    "llvm.hexagon.S2.lsr.i.r.or" => "__builtin_HEXAGON_S2_lsr_i_r_or",
+    "llvm.hexagon.S2.lsr.i.r.xacc" => "__builtin_HEXAGON_S2_lsr_i_r_xacc",
+    "llvm.hexagon.S2.lsr.i.vh" => "__builtin_HEXAGON_S2_lsr_i_vh",
+    "llvm.hexagon.S2.lsr.i.vw" => "__builtin_HEXAGON_S2_lsr_i_vw",
+    "llvm.hexagon.S2.lsr.r.p" => "__builtin_HEXAGON_S2_lsr_r_p",
+    "llvm.hexagon.S2.lsr.r.p.acc" => "__builtin_HEXAGON_S2_lsr_r_p_acc",
+    "llvm.hexagon.S2.lsr.r.p.and" => "__builtin_HEXAGON_S2_lsr_r_p_and",
+    "llvm.hexagon.S2.lsr.r.p.nac" => "__builtin_HEXAGON_S2_lsr_r_p_nac",
+    "llvm.hexagon.S2.lsr.r.p.or" => "__builtin_HEXAGON_S2_lsr_r_p_or",
+    "llvm.hexagon.S2.lsr.r.p.xor" => "__builtin_HEXAGON_S2_lsr_r_p_xor",
+    "llvm.hexagon.S2.lsr.r.r" => "__builtin_HEXAGON_S2_lsr_r_r",
+    "llvm.hexagon.S2.lsr.r.r.acc" => "__builtin_HEXAGON_S2_lsr_r_r_acc",
+    "llvm.hexagon.S2.lsr.r.r.and" => "__builtin_HEXAGON_S2_lsr_r_r_and",
+    "llvm.hexagon.S2.lsr.r.r.nac" => "__builtin_HEXAGON_S2_lsr_r_r_nac",
+    "llvm.hexagon.S2.lsr.r.r.or" => "__builtin_HEXAGON_S2_lsr_r_r_or",
+    "llvm.hexagon.S2.lsr.r.vh" => "__builtin_HEXAGON_S2_lsr_r_vh",
+    "llvm.hexagon.S2.lsr.r.vw" => "__builtin_HEXAGON_S2_lsr_r_vw",
+    "llvm.hexagon.S2.packhl" => "__builtin_HEXAGON_S2_packhl",
+    "llvm.hexagon.S2.parityp" => "__builtin_HEXAGON_S2_parityp",
+    "llvm.hexagon.S2.setbit.i" => "__builtin_HEXAGON_S2_setbit_i",
+    "llvm.hexagon.S2.setbit.r" => "__builtin_HEXAGON_S2_setbit_r",
+    "llvm.hexagon.S2.shuffeb" => "__builtin_HEXAGON_S2_shuffeb",
+    "llvm.hexagon.S2.shuffeh" => "__builtin_HEXAGON_S2_shuffeh",
+    "llvm.hexagon.S2.shuffob" => "__builtin_HEXAGON_S2_shuffob",
+    "llvm.hexagon.S2.shuffoh" => "__builtin_HEXAGON_S2_shuffoh",
+    "llvm.hexagon.S2.svsathb" => "__builtin_HEXAGON_S2_svsathb",
+    "llvm.hexagon.S2.svsathub" => "__builtin_HEXAGON_S2_svsathub",
+    "llvm.hexagon.S2.tableidxb.goodsyntax" => "__builtin_HEXAGON_S2_tableidxb_goodsyntax",
+    "llvm.hexagon.S2.tableidxd.goodsyntax" => "__builtin_HEXAGON_S2_tableidxd_goodsyntax",
+    "llvm.hexagon.S2.tableidxh.goodsyntax" => "__builtin_HEXAGON_S2_tableidxh_goodsyntax",
+    "llvm.hexagon.S2.tableidxw.goodsyntax" => "__builtin_HEXAGON_S2_tableidxw_goodsyntax",
+    "llvm.hexagon.S2.togglebit.i" => "__builtin_HEXAGON_S2_togglebit_i",
+    "llvm.hexagon.S2.togglebit.r" => "__builtin_HEXAGON_S2_togglebit_r",
+    "llvm.hexagon.S2.tstbit.i" => "__builtin_HEXAGON_S2_tstbit_i",
+    "llvm.hexagon.S2.tstbit.r" => "__builtin_HEXAGON_S2_tstbit_r",
+    "llvm.hexagon.S2.valignib" => "__builtin_HEXAGON_S2_valignib",
+    "llvm.hexagon.S2.valignrb" => "__builtin_HEXAGON_S2_valignrb",
+    "llvm.hexagon.S2.vcnegh" => "__builtin_HEXAGON_S2_vcnegh",
+    "llvm.hexagon.S2.vcrotate" => "__builtin_HEXAGON_S2_vcrotate",
+    "llvm.hexagon.S2.vrcnegh" => "__builtin_HEXAGON_S2_vrcnegh",
+    "llvm.hexagon.S2.vrndpackwh" => "__builtin_HEXAGON_S2_vrndpackwh",
+    "llvm.hexagon.S2.vrndpackwhs" => "__builtin_HEXAGON_S2_vrndpackwhs",
+    "llvm.hexagon.S2.vsathb" => "__builtin_HEXAGON_S2_vsathb",
+    "llvm.hexagon.S2.vsathb.nopack" => "__builtin_HEXAGON_S2_vsathb_nopack",
+    "llvm.hexagon.S2.vsathub" => "__builtin_HEXAGON_S2_vsathub",
+    "llvm.hexagon.S2.vsathub.nopack" => "__builtin_HEXAGON_S2_vsathub_nopack",
+    "llvm.hexagon.S2.vsatwh" => "__builtin_HEXAGON_S2_vsatwh",
+    "llvm.hexagon.S2.vsatwh.nopack" => "__builtin_HEXAGON_S2_vsatwh_nopack",
+    "llvm.hexagon.S2.vsatwuh" => "__builtin_HEXAGON_S2_vsatwuh",
+    "llvm.hexagon.S2.vsatwuh.nopack" => "__builtin_HEXAGON_S2_vsatwuh_nopack",
+    "llvm.hexagon.S2.vsplatrb" => "__builtin_HEXAGON_S2_vsplatrb",
+    "llvm.hexagon.S2.vsplatrh" => "__builtin_HEXAGON_S2_vsplatrh",
+    "llvm.hexagon.S2.vspliceib" => "__builtin_HEXAGON_S2_vspliceib",
+    "llvm.hexagon.S2.vsplicerb" => "__builtin_HEXAGON_S2_vsplicerb",
+    "llvm.hexagon.S2.vsxtbh" => "__builtin_HEXAGON_S2_vsxtbh",
+    "llvm.hexagon.S2.vsxthw" => "__builtin_HEXAGON_S2_vsxthw",
+    "llvm.hexagon.S2.vtrunehb" => "__builtin_HEXAGON_S2_vtrunehb",
+    "llvm.hexagon.S2.vtrunewh" => "__builtin_HEXAGON_S2_vtrunewh",
+    "llvm.hexagon.S2.vtrunohb" => "__builtin_HEXAGON_S2_vtrunohb",
+    "llvm.hexagon.S2.vtrunowh" => "__builtin_HEXAGON_S2_vtrunowh",
+    "llvm.hexagon.S2.vzxtbh" => "__builtin_HEXAGON_S2_vzxtbh",
+    "llvm.hexagon.S2.vzxthw" => "__builtin_HEXAGON_S2_vzxthw",
+    "llvm.hexagon.S4.addaddi" => "__builtin_HEXAGON_S4_addaddi",
+    "llvm.hexagon.S4.addi.asl.ri" => "__builtin_HEXAGON_S4_addi_asl_ri",
+    "llvm.hexagon.S4.addi.lsr.ri" => "__builtin_HEXAGON_S4_addi_lsr_ri",
+    "llvm.hexagon.S4.andi.asl.ri" => "__builtin_HEXAGON_S4_andi_asl_ri",
+    "llvm.hexagon.S4.andi.lsr.ri" => "__builtin_HEXAGON_S4_andi_lsr_ri",
+    "llvm.hexagon.S4.clbaddi" => "__builtin_HEXAGON_S4_clbaddi",
+    "llvm.hexagon.S4.clbpaddi" => "__builtin_HEXAGON_S4_clbpaddi",
+    "llvm.hexagon.S4.clbpnorm" => "__builtin_HEXAGON_S4_clbpnorm",
+    "llvm.hexagon.S4.extract" => "__builtin_HEXAGON_S4_extract",
+    "llvm.hexagon.S4.extract.rp" => "__builtin_HEXAGON_S4_extract_rp",
+    "llvm.hexagon.S4.extractp" => "__builtin_HEXAGON_S4_extractp",
+    "llvm.hexagon.S4.extractp.rp" => "__builtin_HEXAGON_S4_extractp_rp",
+    "llvm.hexagon.S4.lsli" => "__builtin_HEXAGON_S4_lsli",
+    "llvm.hexagon.S4.ntstbit.i" => "__builtin_HEXAGON_S4_ntstbit_i",
+    "llvm.hexagon.S4.ntstbit.r" => "__builtin_HEXAGON_S4_ntstbit_r",
+    "llvm.hexagon.S4.or.andi" => "__builtin_HEXAGON_S4_or_andi",
+    "llvm.hexagon.S4.or.andix" => "__builtin_HEXAGON_S4_or_andix",
+    "llvm.hexagon.S4.or.ori" => "__builtin_HEXAGON_S4_or_ori",
+    "llvm.hexagon.S4.ori.asl.ri" => "__builtin_HEXAGON_S4_ori_asl_ri",
+    "llvm.hexagon.S4.ori.lsr.ri" => "__builtin_HEXAGON_S4_ori_lsr_ri",
+    "llvm.hexagon.S4.parity" => "__builtin_HEXAGON_S4_parity",
+    "llvm.hexagon.S4.subaddi" => "__builtin_HEXAGON_S4_subaddi",
+    "llvm.hexagon.S4.subi.asl.ri" => "__builtin_HEXAGON_S4_subi_asl_ri",
+    "llvm.hexagon.S4.subi.lsr.ri" => "__builtin_HEXAGON_S4_subi_lsr_ri",
+    "llvm.hexagon.S4.vrcrotate" => "__builtin_HEXAGON_S4_vrcrotate",
+    "llvm.hexagon.S4.vrcrotate.acc" => "__builtin_HEXAGON_S4_vrcrotate_acc",
+    "llvm.hexagon.S4.vxaddsubh" => "__builtin_HEXAGON_S4_vxaddsubh",
+    "llvm.hexagon.S4.vxaddsubhr" => "__builtin_HEXAGON_S4_vxaddsubhr",
+    "llvm.hexagon.S4.vxaddsubw" => "__builtin_HEXAGON_S4_vxaddsubw",
+    "llvm.hexagon.S4.vxsubaddh" => "__builtin_HEXAGON_S4_vxsubaddh",
+    "llvm.hexagon.S4.vxsubaddhr" => "__builtin_HEXAGON_S4_vxsubaddhr",
+    "llvm.hexagon.S4.vxsubaddw" => "__builtin_HEXAGON_S4_vxsubaddw",
+    "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax" => "__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax",
+    "llvm.hexagon.S5.asrhub.sat" => "__builtin_HEXAGON_S5_asrhub_sat",
+    "llvm.hexagon.S5.popcountp" => "__builtin_HEXAGON_S5_popcountp",
+    "llvm.hexagon.S5.vasrhrnd.goodsyntax" => "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax",
+    "llvm.hexagon.S6.rol.i.p" => "__builtin_HEXAGON_S6_rol_i_p",
+    "llvm.hexagon.S6.rol.i.p.acc" => "__builtin_HEXAGON_S6_rol_i_p_acc",
+    "llvm.hexagon.S6.rol.i.p.and" => "__builtin_HEXAGON_S6_rol_i_p_and",
+    "llvm.hexagon.S6.rol.i.p.nac" => "__builtin_HEXAGON_S6_rol_i_p_nac",
+    "llvm.hexagon.S6.rol.i.p.or" => "__builtin_HEXAGON_S6_rol_i_p_or",
+    "llvm.hexagon.S6.rol.i.p.xacc" => "__builtin_HEXAGON_S6_rol_i_p_xacc",
+    "llvm.hexagon.S6.rol.i.r" => "__builtin_HEXAGON_S6_rol_i_r",
+    "llvm.hexagon.S6.rol.i.r.acc" => "__builtin_HEXAGON_S6_rol_i_r_acc",
+    "llvm.hexagon.S6.rol.i.r.and" => "__builtin_HEXAGON_S6_rol_i_r_and",
+    "llvm.hexagon.S6.rol.i.r.nac" => "__builtin_HEXAGON_S6_rol_i_r_nac",
+    "llvm.hexagon.S6.rol.i.r.or" => "__builtin_HEXAGON_S6_rol_i_r_or",
+    "llvm.hexagon.S6.rol.i.r.xacc" => "__builtin_HEXAGON_S6_rol_i_r_xacc",
+    "llvm.hexagon.S6.vsplatrbp" => "__builtin_HEXAGON_S6_vsplatrbp",
+    "llvm.hexagon.S6.vtrunehb.ppp" => "__builtin_HEXAGON_S6_vtrunehb_ppp",
+    "llvm.hexagon.S6.vtrunohb.ppp" => "__builtin_HEXAGON_S6_vtrunohb_ppp",
+    "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh",
+    "llvm.hexagon.V6.extractw" => "__builtin_HEXAGON_V6_extractw",
+    "llvm.hexagon.V6.extractw.128B" => "__builtin_HEXAGON_V6_extractw_128B",
+    "llvm.hexagon.V6.hi" => "__builtin_HEXAGON_V6_hi",
+    "llvm.hexagon.V6.hi.128B" => "__builtin_HEXAGON_V6_hi_128B",
+    "llvm.hexagon.V6.lo" => "__builtin_HEXAGON_V6_lo",
+    "llvm.hexagon.V6.lo.128B" => "__builtin_HEXAGON_V6_lo_128B",
+    "llvm.hexagon.V6.lvsplatw" => "__builtin_HEXAGON_V6_lvsplatw",
+    "llvm.hexagon.V6.lvsplatw.128B" => "__builtin_HEXAGON_V6_lvsplatw_128B",
+    "llvm.hexagon.V6.vabsdiffh" => "__builtin_HEXAGON_V6_vabsdiffh",
+    "llvm.hexagon.V6.vabsdiffh.128B" => "__builtin_HEXAGON_V6_vabsdiffh_128B",
+    "llvm.hexagon.V6.vabsdiffub" => "__builtin_HEXAGON_V6_vabsdiffub",
+    "llvm.hexagon.V6.vabsdiffub.128B" => "__builtin_HEXAGON_V6_vabsdiffub_128B",
+    "llvm.hexagon.V6.vabsdiffuh" => "__builtin_HEXAGON_V6_vabsdiffuh",
+    "llvm.hexagon.V6.vabsdiffuh.128B" => "__builtin_HEXAGON_V6_vabsdiffuh_128B",
+    "llvm.hexagon.V6.vabsdiffw" => "__builtin_HEXAGON_V6_vabsdiffw",
+    "llvm.hexagon.V6.vabsdiffw.128B" => "__builtin_HEXAGON_V6_vabsdiffw_128B",
+    "llvm.hexagon.V6.vabsh" => "__builtin_HEXAGON_V6_vabsh",
+    "llvm.hexagon.V6.vabsh.128B" => "__builtin_HEXAGON_V6_vabsh_128B",
+    "llvm.hexagon.V6.vabsh.sat" => "__builtin_HEXAGON_V6_vabsh_sat",
+    "llvm.hexagon.V6.vabsh.sat.128B" => "__builtin_HEXAGON_V6_vabsh_sat_128B",
+    "llvm.hexagon.V6.vabsw" => "__builtin_HEXAGON_V6_vabsw",
+    "llvm.hexagon.V6.vabsw.128B" => "__builtin_HEXAGON_V6_vabsw_128B",
+    "llvm.hexagon.V6.vabsw.sat" => "__builtin_HEXAGON_V6_vabsw_sat",
+    "llvm.hexagon.V6.vabsw.sat.128B" => "__builtin_HEXAGON_V6_vabsw_sat_128B",
+    "llvm.hexagon.V6.vaddb" => "__builtin_HEXAGON_V6_vaddb",
+    "llvm.hexagon.V6.vaddb.128B" => "__builtin_HEXAGON_V6_vaddb_128B",
+    "llvm.hexagon.V6.vaddb.dv" => "__builtin_HEXAGON_V6_vaddb_dv",
+    "llvm.hexagon.V6.vaddb.dv.128B" => "__builtin_HEXAGON_V6_vaddb_dv_128B",
+    "llvm.hexagon.V6.vaddh" => "__builtin_HEXAGON_V6_vaddh",
+    "llvm.hexagon.V6.vaddh.128B" => "__builtin_HEXAGON_V6_vaddh_128B",
+    "llvm.hexagon.V6.vaddh.dv" => "__builtin_HEXAGON_V6_vaddh_dv",
+    "llvm.hexagon.V6.vaddh.dv.128B" => "__builtin_HEXAGON_V6_vaddh_dv_128B",
+    "llvm.hexagon.V6.vaddhsat" => "__builtin_HEXAGON_V6_vaddhsat",
+    "llvm.hexagon.V6.vaddhsat.128B" => "__builtin_HEXAGON_V6_vaddhsat_128B",
+    "llvm.hexagon.V6.vaddhsat.dv" => "__builtin_HEXAGON_V6_vaddhsat_dv",
+    "llvm.hexagon.V6.vaddhsat.dv.128B" => "__builtin_HEXAGON_V6_vaddhsat_dv_128B",
+    "llvm.hexagon.V6.vaddhw" => "__builtin_HEXAGON_V6_vaddhw",
+    "llvm.hexagon.V6.vaddhw.128B" => "__builtin_HEXAGON_V6_vaddhw_128B",
+    "llvm.hexagon.V6.vaddubh" => "__builtin_HEXAGON_V6_vaddubh",
+    "llvm.hexagon.V6.vaddubh.128B" => "__builtin_HEXAGON_V6_vaddubh_128B",
+    "llvm.hexagon.V6.vaddubsat" => "__builtin_HEXAGON_V6_vaddubsat",
+    "llvm.hexagon.V6.vaddubsat.128B" => "__builtin_HEXAGON_V6_vaddubsat_128B",
+    "llvm.hexagon.V6.vaddubsat.dv" => "__builtin_HEXAGON_V6_vaddubsat_dv",
+    "llvm.hexagon.V6.vaddubsat.dv.128B" => "__builtin_HEXAGON_V6_vaddubsat_dv_128B",
+    "llvm.hexagon.V6.vadduhsat" => "__builtin_HEXAGON_V6_vadduhsat",
+    "llvm.hexagon.V6.vadduhsat.128B" => "__builtin_HEXAGON_V6_vadduhsat_128B",
+    "llvm.hexagon.V6.vadduhsat.dv" => "__builtin_HEXAGON_V6_vadduhsat_dv",
+    "llvm.hexagon.V6.vadduhsat.dv.128B" => "__builtin_HEXAGON_V6_vadduhsat_dv_128B",
+    "llvm.hexagon.V6.vadduhw" => "__builtin_HEXAGON_V6_vadduhw",
+    "llvm.hexagon.V6.vadduhw.128B" => "__builtin_HEXAGON_V6_vadduhw_128B",
+    "llvm.hexagon.V6.vaddw" => "__builtin_HEXAGON_V6_vaddw",
+    "llvm.hexagon.V6.vaddw.128B" => "__builtin_HEXAGON_V6_vaddw_128B",
+    "llvm.hexagon.V6.vaddw.dv" => "__builtin_HEXAGON_V6_vaddw_dv",
+    "llvm.hexagon.V6.vaddw.dv.128B" => "__builtin_HEXAGON_V6_vaddw_dv_128B",
+    "llvm.hexagon.V6.vaddwsat" => "__builtin_HEXAGON_V6_vaddwsat",
+    "llvm.hexagon.V6.vaddwsat.128B" => "__builtin_HEXAGON_V6_vaddwsat_128B",
+    "llvm.hexagon.V6.vaddwsat.dv" => "__builtin_HEXAGON_V6_vaddwsat_dv",
+    "llvm.hexagon.V6.vaddwsat.dv.128B" => "__builtin_HEXAGON_V6_vaddwsat_dv_128B",
+    "llvm.hexagon.V6.valignb" => "__builtin_HEXAGON_V6_valignb",
+    "llvm.hexagon.V6.valignb.128B" => "__builtin_HEXAGON_V6_valignb_128B",
+    "llvm.hexagon.V6.valignbi" => "__builtin_HEXAGON_V6_valignbi",
+    "llvm.hexagon.V6.valignbi.128B" => "__builtin_HEXAGON_V6_valignbi_128B",
+    "llvm.hexagon.V6.vand" => "__builtin_HEXAGON_V6_vand",
+    "llvm.hexagon.V6.vand.128B" => "__builtin_HEXAGON_V6_vand_128B",
+    "llvm.hexagon.V6.vaslh" => "__builtin_HEXAGON_V6_vaslh",
+    "llvm.hexagon.V6.vaslh.128B" => "__builtin_HEXAGON_V6_vaslh_128B",
+    "llvm.hexagon.V6.vaslhv" => "__builtin_HEXAGON_V6_vaslhv",
+    "llvm.hexagon.V6.vaslhv.128B" => "__builtin_HEXAGON_V6_vaslhv_128B",
+    "llvm.hexagon.V6.vaslw" => "__builtin_HEXAGON_V6_vaslw",
+    "llvm.hexagon.V6.vaslw.128B" => "__builtin_HEXAGON_V6_vaslw_128B",
+    "llvm.hexagon.V6.vaslw.acc" => "__builtin_HEXAGON_V6_vaslw_acc",
+    "llvm.hexagon.V6.vaslw.acc.128B" => "__builtin_HEXAGON_V6_vaslw_acc_128B",
+    "llvm.hexagon.V6.vaslwv" => "__builtin_HEXAGON_V6_vaslwv",
+    "llvm.hexagon.V6.vaslwv.128B" => "__builtin_HEXAGON_V6_vaslwv_128B",
+    "llvm.hexagon.V6.vasrh" => "__builtin_HEXAGON_V6_vasrh",
+    "llvm.hexagon.V6.vasrh.128B" => "__builtin_HEXAGON_V6_vasrh_128B",
+    "llvm.hexagon.V6.vasrhbrndsat" => "__builtin_HEXAGON_V6_vasrhbrndsat",
+    "llvm.hexagon.V6.vasrhbrndsat.128B" => "__builtin_HEXAGON_V6_vasrhbrndsat_128B",
+    "llvm.hexagon.V6.vasrhubrndsat" => "__builtin_HEXAGON_V6_vasrhubrndsat",
+    "llvm.hexagon.V6.vasrhubrndsat.128B" => "__builtin_HEXAGON_V6_vasrhubrndsat_128B",
+    "llvm.hexagon.V6.vasrhubsat" => "__builtin_HEXAGON_V6_vasrhubsat",
+    "llvm.hexagon.V6.vasrhubsat.128B" => "__builtin_HEXAGON_V6_vasrhubsat_128B",
+    "llvm.hexagon.V6.vasrhv" => "__builtin_HEXAGON_V6_vasrhv",
+    "llvm.hexagon.V6.vasrhv.128B" => "__builtin_HEXAGON_V6_vasrhv_128B",
+    "llvm.hexagon.V6.vasrw" => "__builtin_HEXAGON_V6_vasrw",
+    "llvm.hexagon.V6.vasrw.128B" => "__builtin_HEXAGON_V6_vasrw_128B",
+    "llvm.hexagon.V6.vasrw.acc" => "__builtin_HEXAGON_V6_vasrw_acc",
+    "llvm.hexagon.V6.vasrw.acc.128B" => "__builtin_HEXAGON_V6_vasrw_acc_128B",
+    "llvm.hexagon.V6.vasrwh" => "__builtin_HEXAGON_V6_vasrwh",
+    "llvm.hexagon.V6.vasrwh.128B" => "__builtin_HEXAGON_V6_vasrwh_128B",
+    "llvm.hexagon.V6.vasrwhrndsat" => "__builtin_HEXAGON_V6_vasrwhrndsat",
+    "llvm.hexagon.V6.vasrwhrndsat.128B" => "__builtin_HEXAGON_V6_vasrwhrndsat_128B",
+    "llvm.hexagon.V6.vasrwhsat" => "__builtin_HEXAGON_V6_vasrwhsat",
+    "llvm.hexagon.V6.vasrwhsat.128B" => "__builtin_HEXAGON_V6_vasrwhsat_128B",
+    "llvm.hexagon.V6.vasrwuhsat" => "__builtin_HEXAGON_V6_vasrwuhsat",
+    "llvm.hexagon.V6.vasrwuhsat.128B" => "__builtin_HEXAGON_V6_vasrwuhsat_128B",
+    "llvm.hexagon.V6.vasrwv" => "__builtin_HEXAGON_V6_vasrwv",
+    "llvm.hexagon.V6.vasrwv.128B" => "__builtin_HEXAGON_V6_vasrwv_128B",
+    "llvm.hexagon.V6.vassign" => "__builtin_HEXAGON_V6_vassign",
+    "llvm.hexagon.V6.vassign.128B" => "__builtin_HEXAGON_V6_vassign_128B",
+    "llvm.hexagon.V6.vassignp" => "__builtin_HEXAGON_V6_vassignp",
+    "llvm.hexagon.V6.vassignp.128B" => "__builtin_HEXAGON_V6_vassignp_128B",
+    "llvm.hexagon.V6.vavgh" => "__builtin_HEXAGON_V6_vavgh",
+    "llvm.hexagon.V6.vavgh.128B" => "__builtin_HEXAGON_V6_vavgh_128B",
+    "llvm.hexagon.V6.vavghrnd" => "__builtin_HEXAGON_V6_vavghrnd",
+    "llvm.hexagon.V6.vavghrnd.128B" => "__builtin_HEXAGON_V6_vavghrnd_128B",
+    "llvm.hexagon.V6.vavgub" => "__builtin_HEXAGON_V6_vavgub",
+    "llvm.hexagon.V6.vavgub.128B" => "__builtin_HEXAGON_V6_vavgub_128B",
+    "llvm.hexagon.V6.vavgubrnd" => "__builtin_HEXAGON_V6_vavgubrnd",
+    "llvm.hexagon.V6.vavgubrnd.128B" => "__builtin_HEXAGON_V6_vavgubrnd_128B",
+    "llvm.hexagon.V6.vavguh" => "__builtin_HEXAGON_V6_vavguh",
+    "llvm.hexagon.V6.vavguh.128B" => "__builtin_HEXAGON_V6_vavguh_128B",
+    "llvm.hexagon.V6.vavguhrnd" => "__builtin_HEXAGON_V6_vavguhrnd",
+    "llvm.hexagon.V6.vavguhrnd.128B" => "__builtin_HEXAGON_V6_vavguhrnd_128B",
+    "llvm.hexagon.V6.vavgw" => "__builtin_HEXAGON_V6_vavgw",
+    "llvm.hexagon.V6.vavgw.128B" => "__builtin_HEXAGON_V6_vavgw_128B",
+    "llvm.hexagon.V6.vavgwrnd" => "__builtin_HEXAGON_V6_vavgwrnd",
+    "llvm.hexagon.V6.vavgwrnd.128B" => "__builtin_HEXAGON_V6_vavgwrnd_128B",
+    "llvm.hexagon.V6.vcl0h" => "__builtin_HEXAGON_V6_vcl0h",
+    "llvm.hexagon.V6.vcl0h.128B" => "__builtin_HEXAGON_V6_vcl0h_128B",
+    "llvm.hexagon.V6.vcl0w" => "__builtin_HEXAGON_V6_vcl0w",
+    "llvm.hexagon.V6.vcl0w.128B" => "__builtin_HEXAGON_V6_vcl0w_128B",
+    "llvm.hexagon.V6.vcombine" => "__builtin_HEXAGON_V6_vcombine",
+    "llvm.hexagon.V6.vcombine.128B" => "__builtin_HEXAGON_V6_vcombine_128B",
+    "llvm.hexagon.V6.vd0" => "__builtin_HEXAGON_V6_vd0",
+    "llvm.hexagon.V6.vd0.128B" => "__builtin_HEXAGON_V6_vd0_128B",
+    "llvm.hexagon.V6.vdealb" => "__builtin_HEXAGON_V6_vdealb",
+    "llvm.hexagon.V6.vdealb.128B" => "__builtin_HEXAGON_V6_vdealb_128B",
+    "llvm.hexagon.V6.vdealb4w" => "__builtin_HEXAGON_V6_vdealb4w",
+    "llvm.hexagon.V6.vdealb4w.128B" => "__builtin_HEXAGON_V6_vdealb4w_128B",
+    "llvm.hexagon.V6.vdealh" => "__builtin_HEXAGON_V6_vdealh",
+    "llvm.hexagon.V6.vdealh.128B" => "__builtin_HEXAGON_V6_vdealh_128B",
+    "llvm.hexagon.V6.vdealvdd" => "__builtin_HEXAGON_V6_vdealvdd",
+    "llvm.hexagon.V6.vdealvdd.128B" => "__builtin_HEXAGON_V6_vdealvdd_128B",
+    "llvm.hexagon.V6.vdelta" => "__builtin_HEXAGON_V6_vdelta",
+    "llvm.hexagon.V6.vdelta.128B" => "__builtin_HEXAGON_V6_vdelta_128B",
+    "llvm.hexagon.V6.vdmpybus" => "__builtin_HEXAGON_V6_vdmpybus",
+    "llvm.hexagon.V6.vdmpybus.128B" => "__builtin_HEXAGON_V6_vdmpybus_128B",
+    "llvm.hexagon.V6.vdmpybus.acc" => "__builtin_HEXAGON_V6_vdmpybus_acc",
+    "llvm.hexagon.V6.vdmpybus.acc.128B" => "__builtin_HEXAGON_V6_vdmpybus_acc_128B",
+    "llvm.hexagon.V6.vdmpybus.dv" => "__builtin_HEXAGON_V6_vdmpybus_dv",
+    "llvm.hexagon.V6.vdmpybus.dv.128B" => "__builtin_HEXAGON_V6_vdmpybus_dv_128B",
+    "llvm.hexagon.V6.vdmpybus.dv.acc" => "__builtin_HEXAGON_V6_vdmpybus_dv_acc",
+    "llvm.hexagon.V6.vdmpybus.dv.acc.128B" => "__builtin_HEXAGON_V6_vdmpybus_dv_acc_128B",
+    "llvm.hexagon.V6.vdmpyhb" => "__builtin_HEXAGON_V6_vdmpyhb",
+    "llvm.hexagon.V6.vdmpyhb.128B" => "__builtin_HEXAGON_V6_vdmpyhb_128B",
+    "llvm.hexagon.V6.vdmpyhb.acc" => "__builtin_HEXAGON_V6_vdmpyhb_acc",
+    "llvm.hexagon.V6.vdmpyhb.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhb_acc_128B",
+    "llvm.hexagon.V6.vdmpyhb.dv" => "__builtin_HEXAGON_V6_vdmpyhb_dv",
+    "llvm.hexagon.V6.vdmpyhb.dv.128B" => "__builtin_HEXAGON_V6_vdmpyhb_dv_128B",
+    "llvm.hexagon.V6.vdmpyhb.dv.acc" => "__builtin_HEXAGON_V6_vdmpyhb_dv_acc",
+    "llvm.hexagon.V6.vdmpyhb.dv.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhb_dv_acc_128B",
+    "llvm.hexagon.V6.vdmpyhisat" => "__builtin_HEXAGON_V6_vdmpyhisat",
+    "llvm.hexagon.V6.vdmpyhisat.128B" => "__builtin_HEXAGON_V6_vdmpyhisat_128B",
+    "llvm.hexagon.V6.vdmpyhisat.acc" => "__builtin_HEXAGON_V6_vdmpyhisat_acc",
+    "llvm.hexagon.V6.vdmpyhisat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhisat_acc_128B",
+    "llvm.hexagon.V6.vdmpyhsat" => "__builtin_HEXAGON_V6_vdmpyhsat",
+    "llvm.hexagon.V6.vdmpyhsat.128B" => "__builtin_HEXAGON_V6_vdmpyhsat_128B",
+    "llvm.hexagon.V6.vdmpyhsat.acc" => "__builtin_HEXAGON_V6_vdmpyhsat_acc",
+    "llvm.hexagon.V6.vdmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsat_acc_128B",
+    "llvm.hexagon.V6.vdmpyhsuisat" => "__builtin_HEXAGON_V6_vdmpyhsuisat",
+    "llvm.hexagon.V6.vdmpyhsuisat.128B" => "__builtin_HEXAGON_V6_vdmpyhsuisat_128B",
+    "llvm.hexagon.V6.vdmpyhsuisat.acc" => "__builtin_HEXAGON_V6_vdmpyhsuisat_acc",
+    "llvm.hexagon.V6.vdmpyhsuisat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsuisat_acc_128B",
+    "llvm.hexagon.V6.vdmpyhsusat" => "__builtin_HEXAGON_V6_vdmpyhsusat",
+    "llvm.hexagon.V6.vdmpyhsusat.128B" => "__builtin_HEXAGON_V6_vdmpyhsusat_128B",
+    "llvm.hexagon.V6.vdmpyhsusat.acc" => "__builtin_HEXAGON_V6_vdmpyhsusat_acc",
+    "llvm.hexagon.V6.vdmpyhsusat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhsusat_acc_128B",
+    "llvm.hexagon.V6.vdmpyhvsat" => "__builtin_HEXAGON_V6_vdmpyhvsat",
+    "llvm.hexagon.V6.vdmpyhvsat.128B" => "__builtin_HEXAGON_V6_vdmpyhvsat_128B",
+    "llvm.hexagon.V6.vdmpyhvsat.acc" => "__builtin_HEXAGON_V6_vdmpyhvsat_acc",
+    "llvm.hexagon.V6.vdmpyhvsat.acc.128B" => "__builtin_HEXAGON_V6_vdmpyhvsat_acc_128B",
+    "llvm.hexagon.V6.vdsaduh" => "__builtin_HEXAGON_V6_vdsaduh",
+    "llvm.hexagon.V6.vdsaduh.128B" => "__builtin_HEXAGON_V6_vdsaduh_128B",
+    "llvm.hexagon.V6.vdsaduh.acc" => "__builtin_HEXAGON_V6_vdsaduh_acc",
+    "llvm.hexagon.V6.vdsaduh.acc.128B" => "__builtin_HEXAGON_V6_vdsaduh_acc_128B",
+    "llvm.hexagon.V6.vinsertwr" => "__builtin_HEXAGON_V6_vinsertwr",
+    "llvm.hexagon.V6.vinsertwr.128B" => "__builtin_HEXAGON_V6_vinsertwr_128B",
+    "llvm.hexagon.V6.vlalignb" => "__builtin_HEXAGON_V6_vlalignb",
+    "llvm.hexagon.V6.vlalignb.128B" => "__builtin_HEXAGON_V6_vlalignb_128B",
+    "llvm.hexagon.V6.vlalignbi" => "__builtin_HEXAGON_V6_vlalignbi",
+    "llvm.hexagon.V6.vlalignbi.128B" => "__builtin_HEXAGON_V6_vlalignbi_128B",
+    "llvm.hexagon.V6.vlsrh" => "__builtin_HEXAGON_V6_vlsrh",
+    "llvm.hexagon.V6.vlsrh.128B" => "__builtin_HEXAGON_V6_vlsrh_128B",
+    "llvm.hexagon.V6.vlsrhv" => "__builtin_HEXAGON_V6_vlsrhv",
+    "llvm.hexagon.V6.vlsrhv.128B" => "__builtin_HEXAGON_V6_vlsrhv_128B",
+    "llvm.hexagon.V6.vlsrw" => "__builtin_HEXAGON_V6_vlsrw",
+    "llvm.hexagon.V6.vlsrw.128B" => "__builtin_HEXAGON_V6_vlsrw_128B",
+    "llvm.hexagon.V6.vlsrwv" => "__builtin_HEXAGON_V6_vlsrwv",
+    "llvm.hexagon.V6.vlsrwv.128B" => "__builtin_HEXAGON_V6_vlsrwv_128B",
+    "llvm.hexagon.V6.vlutb" => "__builtin_HEXAGON_V6_vlutb",
+    "llvm.hexagon.V6.vlutb.128B" => "__builtin_HEXAGON_V6_vlutb_128B",
+    "llvm.hexagon.V6.vlutb.acc" => "__builtin_HEXAGON_V6_vlutb_acc",
+    "llvm.hexagon.V6.vlutb.acc.128B" => "__builtin_HEXAGON_V6_vlutb_acc_128B",
+    "llvm.hexagon.V6.vlutb.dv" => "__builtin_HEXAGON_V6_vlutb_dv",
+    "llvm.hexagon.V6.vlutb.dv.128B" => "__builtin_HEXAGON_V6_vlutb_dv_128B",
+    "llvm.hexagon.V6.vlutb.dv.acc" => "__builtin_HEXAGON_V6_vlutb_dv_acc",
+    "llvm.hexagon.V6.vlutb.dv.acc.128B" => "__builtin_HEXAGON_V6_vlutb_dv_acc_128B",
+    "llvm.hexagon.V6.vlutvvb" => "__builtin_HEXAGON_V6_vlutvvb",
+    "llvm.hexagon.V6.vlutvvb.128B" => "__builtin_HEXAGON_V6_vlutvvb_128B",
+    "llvm.hexagon.V6.vlutvvb.oracc" => "__builtin_HEXAGON_V6_vlutvvb_oracc",
+    "llvm.hexagon.V6.vlutvvb.oracc.128B" => "__builtin_HEXAGON_V6_vlutvvb_oracc_128B",
+    "llvm.hexagon.V6.vlutvwh" => "__builtin_HEXAGON_V6_vlutvwh",
+    "llvm.hexagon.V6.vlutvwh.128B" => "__builtin_HEXAGON_V6_vlutvwh_128B",
+    "llvm.hexagon.V6.vlutvwh.oracc" => "__builtin_HEXAGON_V6_vlutvwh_oracc",
+    "llvm.hexagon.V6.vlutvwh.oracc.128B" => "__builtin_HEXAGON_V6_vlutvwh_oracc_128B",
+    "llvm.hexagon.V6.vmaxh" => "__builtin_HEXAGON_V6_vmaxh",
+    "llvm.hexagon.V6.vmaxh.128B" => "__builtin_HEXAGON_V6_vmaxh_128B",
+    "llvm.hexagon.V6.vmaxub" => "__builtin_HEXAGON_V6_vmaxub",
+    "llvm.hexagon.V6.vmaxub.128B" => "__builtin_HEXAGON_V6_vmaxub_128B",
+    "llvm.hexagon.V6.vmaxuh" => "__builtin_HEXAGON_V6_vmaxuh",
+    "llvm.hexagon.V6.vmaxuh.128B" => "__builtin_HEXAGON_V6_vmaxuh_128B",
+    "llvm.hexagon.V6.vmaxw" => "__builtin_HEXAGON_V6_vmaxw",
+    "llvm.hexagon.V6.vmaxw.128B" => "__builtin_HEXAGON_V6_vmaxw_128B",
+    "llvm.hexagon.V6.vminh" => "__builtin_HEXAGON_V6_vminh",
+    "llvm.hexagon.V6.vminh.128B" => "__builtin_HEXAGON_V6_vminh_128B",
+    "llvm.hexagon.V6.vminub" => "__builtin_HEXAGON_V6_vminub",
+    "llvm.hexagon.V6.vminub.128B" => "__builtin_HEXAGON_V6_vminub_128B",
+    "llvm.hexagon.V6.vminuh" => "__builtin_HEXAGON_V6_vminuh",
+    "llvm.hexagon.V6.vminuh.128B" => "__builtin_HEXAGON_V6_vminuh_128B",
+    "llvm.hexagon.V6.vminw" => "__builtin_HEXAGON_V6_vminw",
+    "llvm.hexagon.V6.vminw.128B" => "__builtin_HEXAGON_V6_vminw_128B",
+    "llvm.hexagon.V6.vmpabus" => "__builtin_HEXAGON_V6_vmpabus",
+    "llvm.hexagon.V6.vmpabus.128B" => "__builtin_HEXAGON_V6_vmpabus_128B",
+    "llvm.hexagon.V6.vmpabus.acc" => "__builtin_HEXAGON_V6_vmpabus_acc",
+    "llvm.hexagon.V6.vmpabus.acc.128B" => "__builtin_HEXAGON_V6_vmpabus_acc_128B",
+    "llvm.hexagon.V6.vmpabusv" => "__builtin_HEXAGON_V6_vmpabusv",
+    "llvm.hexagon.V6.vmpabusv.128B" => "__builtin_HEXAGON_V6_vmpabusv_128B",
+    "llvm.hexagon.V6.vmpabuuv" => "__builtin_HEXAGON_V6_vmpabuuv",
+    "llvm.hexagon.V6.vmpabuuv.128B" => "__builtin_HEXAGON_V6_vmpabuuv_128B",
+    "llvm.hexagon.V6.vmpahb" => "__builtin_HEXAGON_V6_vmpahb",
+    "llvm.hexagon.V6.vmpahb.128B" => "__builtin_HEXAGON_V6_vmpahb_128B",
+    "llvm.hexagon.V6.vmpahb.acc" => "__builtin_HEXAGON_V6_vmpahb_acc",
+    "llvm.hexagon.V6.vmpahb.acc.128B" => "__builtin_HEXAGON_V6_vmpahb_acc_128B",
+    "llvm.hexagon.V6.vmpybus" => "__builtin_HEXAGON_V6_vmpybus",
+    "llvm.hexagon.V6.vmpybus.128B" => "__builtin_HEXAGON_V6_vmpybus_128B",
+    "llvm.hexagon.V6.vmpybus.acc" => "__builtin_HEXAGON_V6_vmpybus_acc",
+    "llvm.hexagon.V6.vmpybus.acc.128B" => "__builtin_HEXAGON_V6_vmpybus_acc_128B",
+    "llvm.hexagon.V6.vmpybusv" => "__builtin_HEXAGON_V6_vmpybusv",
+    "llvm.hexagon.V6.vmpybusv.128B" => "__builtin_HEXAGON_V6_vmpybusv_128B",
+    "llvm.hexagon.V6.vmpybusv.acc" => "__builtin_HEXAGON_V6_vmpybusv_acc",
+    "llvm.hexagon.V6.vmpybusv.acc.128B" => "__builtin_HEXAGON_V6_vmpybusv_acc_128B",
+    "llvm.hexagon.V6.vmpybv" => "__builtin_HEXAGON_V6_vmpybv",
+    "llvm.hexagon.V6.vmpybv.128B" => "__builtin_HEXAGON_V6_vmpybv_128B",
+    "llvm.hexagon.V6.vmpybv.acc" => "__builtin_HEXAGON_V6_vmpybv_acc",
+    "llvm.hexagon.V6.vmpybv.acc.128B" => "__builtin_HEXAGON_V6_vmpybv_acc_128B",
+    "llvm.hexagon.V6.vmpyewuh" => "__builtin_HEXAGON_V6_vmpyewuh",
+    "llvm.hexagon.V6.vmpyewuh.128B" => "__builtin_HEXAGON_V6_vmpyewuh_128B",
+    "llvm.hexagon.V6.vmpyh" => "__builtin_HEXAGON_V6_vmpyh",
+    "llvm.hexagon.V6.vmpyh.128B" => "__builtin_HEXAGON_V6_vmpyh_128B",
+    "llvm.hexagon.V6.vmpyhsat.acc" => "__builtin_HEXAGON_V6_vmpyhsat_acc",
+    "llvm.hexagon.V6.vmpyhsat.acc.128B" => "__builtin_HEXAGON_V6_vmpyhsat_acc_128B",
+    "llvm.hexagon.V6.vmpyhsrs" => "__builtin_HEXAGON_V6_vmpyhsrs",
+    "llvm.hexagon.V6.vmpyhsrs.128B" => "__builtin_HEXAGON_V6_vmpyhsrs_128B",
+    "llvm.hexagon.V6.vmpyhss" => "__builtin_HEXAGON_V6_vmpyhss",
+    "llvm.hexagon.V6.vmpyhss.128B" => "__builtin_HEXAGON_V6_vmpyhss_128B",
+    "llvm.hexagon.V6.vmpyhus" => "__builtin_HEXAGON_V6_vmpyhus",
+    "llvm.hexagon.V6.vmpyhus.128B" => "__builtin_HEXAGON_V6_vmpyhus_128B",
+    "llvm.hexagon.V6.vmpyhus.acc" => "__builtin_HEXAGON_V6_vmpyhus_acc",
+    "llvm.hexagon.V6.vmpyhus.acc.128B" => "__builtin_HEXAGON_V6_vmpyhus_acc_128B",
+    "llvm.hexagon.V6.vmpyhv" => "__builtin_HEXAGON_V6_vmpyhv",
+    "llvm.hexagon.V6.vmpyhv.128B" => "__builtin_HEXAGON_V6_vmpyhv_128B",
+    "llvm.hexagon.V6.vmpyhv.acc" => "__builtin_HEXAGON_V6_vmpyhv_acc",
+    "llvm.hexagon.V6.vmpyhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyhv_acc_128B",
+    "llvm.hexagon.V6.vmpyhvsrs" => "__builtin_HEXAGON_V6_vmpyhvsrs",
+    "llvm.hexagon.V6.vmpyhvsrs.128B" => "__builtin_HEXAGON_V6_vmpyhvsrs_128B",
+    "llvm.hexagon.V6.vmpyieoh" => "__builtin_HEXAGON_V6_vmpyieoh",
+    "llvm.hexagon.V6.vmpyieoh.128B" => "__builtin_HEXAGON_V6_vmpyieoh_128B",
+    "llvm.hexagon.V6.vmpyiewh.acc" => "__builtin_HEXAGON_V6_vmpyiewh_acc",
+    "llvm.hexagon.V6.vmpyiewh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiewh_acc_128B",
+    "llvm.hexagon.V6.vmpyiewuh" => "__builtin_HEXAGON_V6_vmpyiewuh",
+    "llvm.hexagon.V6.vmpyiewuh.128B" => "__builtin_HEXAGON_V6_vmpyiewuh_128B",
+    "llvm.hexagon.V6.vmpyiewuh.acc" => "__builtin_HEXAGON_V6_vmpyiewuh_acc",
+    "llvm.hexagon.V6.vmpyiewuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiewuh_acc_128B",
+    "llvm.hexagon.V6.vmpyih" => "__builtin_HEXAGON_V6_vmpyih",
+    "llvm.hexagon.V6.vmpyih.128B" => "__builtin_HEXAGON_V6_vmpyih_128B",
+    "llvm.hexagon.V6.vmpyih.acc" => "__builtin_HEXAGON_V6_vmpyih_acc",
+    "llvm.hexagon.V6.vmpyih.acc.128B" => "__builtin_HEXAGON_V6_vmpyih_acc_128B",
+    "llvm.hexagon.V6.vmpyihb" => "__builtin_HEXAGON_V6_vmpyihb",
+    "llvm.hexagon.V6.vmpyihb.128B" => "__builtin_HEXAGON_V6_vmpyihb_128B",
+    "llvm.hexagon.V6.vmpyihb.acc" => "__builtin_HEXAGON_V6_vmpyihb_acc",
+    "llvm.hexagon.V6.vmpyihb.acc.128B" => "__builtin_HEXAGON_V6_vmpyihb_acc_128B",
+    "llvm.hexagon.V6.vmpyiowh" => "__builtin_HEXAGON_V6_vmpyiowh",
+    "llvm.hexagon.V6.vmpyiowh.128B" => "__builtin_HEXAGON_V6_vmpyiowh_128B",
+    "llvm.hexagon.V6.vmpyiwb" => "__builtin_HEXAGON_V6_vmpyiwb",
+    "llvm.hexagon.V6.vmpyiwb.128B" => "__builtin_HEXAGON_V6_vmpyiwb_128B",
+    "llvm.hexagon.V6.vmpyiwb.acc" => "__builtin_HEXAGON_V6_vmpyiwb_acc",
+    "llvm.hexagon.V6.vmpyiwb.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwb_acc_128B",
+    "llvm.hexagon.V6.vmpyiwh" => "__builtin_HEXAGON_V6_vmpyiwh",
+    "llvm.hexagon.V6.vmpyiwh.128B" => "__builtin_HEXAGON_V6_vmpyiwh_128B",
+    "llvm.hexagon.V6.vmpyiwh.acc" => "__builtin_HEXAGON_V6_vmpyiwh_acc",
+    "llvm.hexagon.V6.vmpyiwh.acc.128B" => "__builtin_HEXAGON_V6_vmpyiwh_acc_128B",
+    "llvm.hexagon.V6.vmpyowh" => "__builtin_HEXAGON_V6_vmpyowh",
+    "llvm.hexagon.V6.vmpyowh.128B" => "__builtin_HEXAGON_V6_vmpyowh_128B",
+    "llvm.hexagon.V6.vmpyowh.rnd" => "__builtin_HEXAGON_V6_vmpyowh_rnd",
+    "llvm.hexagon.V6.vmpyowh.rnd.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_128B",
+    "llvm.hexagon.V6.vmpyowh.rnd.sacc" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc",
+    "llvm.hexagon.V6.vmpyowh.rnd.sacc.128B" => "__builtin_HEXAGON_V6_vmpyowh_rnd_sacc_128B",
+    "llvm.hexagon.V6.vmpyowh.sacc" => "__builtin_HEXAGON_V6_vmpyowh_sacc",
+    "llvm.hexagon.V6.vmpyowh.sacc.128B" => "__builtin_HEXAGON_V6_vmpyowh_sacc_128B",
+    "llvm.hexagon.V6.vmpyub" => "__builtin_HEXAGON_V6_vmpyub",
+    "llvm.hexagon.V6.vmpyub.128B" => "__builtin_HEXAGON_V6_vmpyub_128B",
+    "llvm.hexagon.V6.vmpyub.acc" => "__builtin_HEXAGON_V6_vmpyub_acc",
+    "llvm.hexagon.V6.vmpyub.acc.128B" => "__builtin_HEXAGON_V6_vmpyub_acc_128B",
+    "llvm.hexagon.V6.vmpyubv" => "__builtin_HEXAGON_V6_vmpyubv",
+    "llvm.hexagon.V6.vmpyubv.128B" => "__builtin_HEXAGON_V6_vmpyubv_128B",
+    "llvm.hexagon.V6.vmpyubv.acc" => "__builtin_HEXAGON_V6_vmpyubv_acc",
+    "llvm.hexagon.V6.vmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vmpyubv_acc_128B",
+    "llvm.hexagon.V6.vmpyuh" => "__builtin_HEXAGON_V6_vmpyuh",
+    "llvm.hexagon.V6.vmpyuh.128B" => "__builtin_HEXAGON_V6_vmpyuh_128B",
+    "llvm.hexagon.V6.vmpyuh.acc" => "__builtin_HEXAGON_V6_vmpyuh_acc",
+    "llvm.hexagon.V6.vmpyuh.acc.128B" => "__builtin_HEXAGON_V6_vmpyuh_acc_128B",
+    "llvm.hexagon.V6.vmpyuhv" => "__builtin_HEXAGON_V6_vmpyuhv",
+    "llvm.hexagon.V6.vmpyuhv.128B" => "__builtin_HEXAGON_V6_vmpyuhv_128B",
+    "llvm.hexagon.V6.vmpyuhv.acc" => "__builtin_HEXAGON_V6_vmpyuhv_acc",
+    "llvm.hexagon.V6.vmpyuhv.acc.128B" => "__builtin_HEXAGON_V6_vmpyuhv_acc_128B",
+    "llvm.hexagon.V6.vnavgh" => "__builtin_HEXAGON_V6_vnavgh",
+    "llvm.hexagon.V6.vnavgh.128B" => "__builtin_HEXAGON_V6_vnavgh_128B",
+    "llvm.hexagon.V6.vnavgub" => "__builtin_HEXAGON_V6_vnavgub",
+    "llvm.hexagon.V6.vnavgub.128B" => "__builtin_HEXAGON_V6_vnavgub_128B",
+    "llvm.hexagon.V6.vnavgw" => "__builtin_HEXAGON_V6_vnavgw",
+    "llvm.hexagon.V6.vnavgw.128B" => "__builtin_HEXAGON_V6_vnavgw_128B",
+    "llvm.hexagon.V6.vnormamth" => "__builtin_HEXAGON_V6_vnormamth",
+    "llvm.hexagon.V6.vnormamth.128B" => "__builtin_HEXAGON_V6_vnormamth_128B",
+    "llvm.hexagon.V6.vnormamtw" => "__builtin_HEXAGON_V6_vnormamtw",
+    "llvm.hexagon.V6.vnormamtw.128B" => "__builtin_HEXAGON_V6_vnormamtw_128B",
+    "llvm.hexagon.V6.vnot" => "__builtin_HEXAGON_V6_vnot",
+    "llvm.hexagon.V6.vnot.128B" => "__builtin_HEXAGON_V6_vnot_128B",
+    "llvm.hexagon.V6.vor" => "__builtin_HEXAGON_V6_vor",
+    "llvm.hexagon.V6.vor.128B" => "__builtin_HEXAGON_V6_vor_128B",
+    "llvm.hexagon.V6.vpackeb" => "__builtin_HEXAGON_V6_vpackeb",
+    "llvm.hexagon.V6.vpackeb.128B" => "__builtin_HEXAGON_V6_vpackeb_128B",
+    "llvm.hexagon.V6.vpackeh" => "__builtin_HEXAGON_V6_vpackeh",
+    "llvm.hexagon.V6.vpackeh.128B" => "__builtin_HEXAGON_V6_vpackeh_128B",
+    "llvm.hexagon.V6.vpackhb.sat" => "__builtin_HEXAGON_V6_vpackhb_sat",
+    "llvm.hexagon.V6.vpackhb.sat.128B" => "__builtin_HEXAGON_V6_vpackhb_sat_128B",
+    "llvm.hexagon.V6.vpackhub.sat" => "__builtin_HEXAGON_V6_vpackhub_sat",
+    "llvm.hexagon.V6.vpackhub.sat.128B" => "__builtin_HEXAGON_V6_vpackhub_sat_128B",
+    "llvm.hexagon.V6.vpackob" => "__builtin_HEXAGON_V6_vpackob",
+    "llvm.hexagon.V6.vpackob.128B" => "__builtin_HEXAGON_V6_vpackob_128B",
+    "llvm.hexagon.V6.vpackoh" => "__builtin_HEXAGON_V6_vpackoh",
+    "llvm.hexagon.V6.vpackoh.128B" => "__builtin_HEXAGON_V6_vpackoh_128B",
+    "llvm.hexagon.V6.vpackwh.sat" => "__builtin_HEXAGON_V6_vpackwh_sat",
+    "llvm.hexagon.V6.vpackwh.sat.128B" => "__builtin_HEXAGON_V6_vpackwh_sat_128B",
+    "llvm.hexagon.V6.vpackwuh.sat" => "__builtin_HEXAGON_V6_vpackwuh_sat",
+    "llvm.hexagon.V6.vpackwuh.sat.128B" => "__builtin_HEXAGON_V6_vpackwuh_sat_128B",
+    "llvm.hexagon.V6.vpopcounth" => "__builtin_HEXAGON_V6_vpopcounth",
+    "llvm.hexagon.V6.vpopcounth.128B" => "__builtin_HEXAGON_V6_vpopcounth_128B",
+    "llvm.hexagon.V6.vrdelta" => "__builtin_HEXAGON_V6_vrdelta",
+    "llvm.hexagon.V6.vrdelta.128B" => "__builtin_HEXAGON_V6_vrdelta_128B",
+    "llvm.hexagon.V6.vrmpybus" => "__builtin_HEXAGON_V6_vrmpybus",
+    "llvm.hexagon.V6.vrmpybus.128B" => "__builtin_HEXAGON_V6_vrmpybus_128B",
+    "llvm.hexagon.V6.vrmpybus.acc" => "__builtin_HEXAGON_V6_vrmpybus_acc",
+    "llvm.hexagon.V6.vrmpybus.acc.128B" => "__builtin_HEXAGON_V6_vrmpybus_acc_128B",
+    "llvm.hexagon.V6.vrmpybusi" => "__builtin_HEXAGON_V6_vrmpybusi",
+    "llvm.hexagon.V6.vrmpybusi.128B" => "__builtin_HEXAGON_V6_vrmpybusi_128B",
+    "llvm.hexagon.V6.vrmpybusi.acc" => "__builtin_HEXAGON_V6_vrmpybusi_acc",
+    "llvm.hexagon.V6.vrmpybusi.acc.128B" => "__builtin_HEXAGON_V6_vrmpybusi_acc_128B",
+    "llvm.hexagon.V6.vrmpybusv" => "__builtin_HEXAGON_V6_vrmpybusv",
+    "llvm.hexagon.V6.vrmpybusv.128B" => "__builtin_HEXAGON_V6_vrmpybusv_128B",
+    "llvm.hexagon.V6.vrmpybusv.acc" => "__builtin_HEXAGON_V6_vrmpybusv_acc",
+    "llvm.hexagon.V6.vrmpybusv.acc.128B" => "__builtin_HEXAGON_V6_vrmpybusv_acc_128B",
+    "llvm.hexagon.V6.vrmpybv" => "__builtin_HEXAGON_V6_vrmpybv",
+    "llvm.hexagon.V6.vrmpybv.128B" => "__builtin_HEXAGON_V6_vrmpybv_128B",
+    "llvm.hexagon.V6.vrmpybv.acc" => "__builtin_HEXAGON_V6_vrmpybv_acc",
+    "llvm.hexagon.V6.vrmpybv.acc.128B" => "__builtin_HEXAGON_V6_vrmpybv_acc_128B",
+    "llvm.hexagon.V6.vrmpyub" => "__builtin_HEXAGON_V6_vrmpyub",
+    "llvm.hexagon.V6.vrmpyub.128B" => "__builtin_HEXAGON_V6_vrmpyub_128B",
+    "llvm.hexagon.V6.vrmpyub.acc" => "__builtin_HEXAGON_V6_vrmpyub_acc",
+    "llvm.hexagon.V6.vrmpyub.acc.128B" => "__builtin_HEXAGON_V6_vrmpyub_acc_128B",
+    "llvm.hexagon.V6.vrmpyubi" => "__builtin_HEXAGON_V6_vrmpyubi",
+    "llvm.hexagon.V6.vrmpyubi.128B" => "__builtin_HEXAGON_V6_vrmpyubi_128B",
+    "llvm.hexagon.V6.vrmpyubi.acc" => "__builtin_HEXAGON_V6_vrmpyubi_acc",
+    "llvm.hexagon.V6.vrmpyubi.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubi_acc_128B",
+    "llvm.hexagon.V6.vrmpyubv" => "__builtin_HEXAGON_V6_vrmpyubv",
+    "llvm.hexagon.V6.vrmpyubv.128B" => "__builtin_HEXAGON_V6_vrmpyubv_128B",
+    "llvm.hexagon.V6.vrmpyubv.acc" => "__builtin_HEXAGON_V6_vrmpyubv_acc",
+    "llvm.hexagon.V6.vrmpyubv.acc.128B" => "__builtin_HEXAGON_V6_vrmpyubv_acc_128B",
+    "llvm.hexagon.V6.vror" => "__builtin_HEXAGON_V6_vror",
+    "llvm.hexagon.V6.vror.128B" => "__builtin_HEXAGON_V6_vror_128B",
+    "llvm.hexagon.V6.vroundhb" => "__builtin_HEXAGON_V6_vroundhb",
+    "llvm.hexagon.V6.vroundhb.128B" => "__builtin_HEXAGON_V6_vroundhb_128B",
+    "llvm.hexagon.V6.vroundhub" => "__builtin_HEXAGON_V6_vroundhub",
+    "llvm.hexagon.V6.vroundhub.128B" => "__builtin_HEXAGON_V6_vroundhub_128B",
+    "llvm.hexagon.V6.vroundwh" => "__builtin_HEXAGON_V6_vroundwh",
+    "llvm.hexagon.V6.vroundwh.128B" => "__builtin_HEXAGON_V6_vroundwh_128B",
+    "llvm.hexagon.V6.vroundwuh" => "__builtin_HEXAGON_V6_vroundwuh",
+    "llvm.hexagon.V6.vroundwuh.128B" => "__builtin_HEXAGON_V6_vroundwuh_128B",
+    "llvm.hexagon.V6.vrsadubi" => "__builtin_HEXAGON_V6_vrsadubi",
+    "llvm.hexagon.V6.vrsadubi.128B" => "__builtin_HEXAGON_V6_vrsadubi_128B",
+    "llvm.hexagon.V6.vrsadubi.acc" => "__builtin_HEXAGON_V6_vrsadubi_acc",
+    "llvm.hexagon.V6.vrsadubi.acc.128B" => "__builtin_HEXAGON_V6_vrsadubi_acc_128B",
+    "llvm.hexagon.V6.vsathub" => "__builtin_HEXAGON_V6_vsathub",
+    "llvm.hexagon.V6.vsathub.128B" => "__builtin_HEXAGON_V6_vsathub_128B",
+    "llvm.hexagon.V6.vsatwh" => "__builtin_HEXAGON_V6_vsatwh",
+    "llvm.hexagon.V6.vsatwh.128B" => "__builtin_HEXAGON_V6_vsatwh_128B",
+    "llvm.hexagon.V6.vsb" => "__builtin_HEXAGON_V6_vsb",
+    "llvm.hexagon.V6.vsb.128B" => "__builtin_HEXAGON_V6_vsb_128B",
+    "llvm.hexagon.V6.vsh" => "__builtin_HEXAGON_V6_vsh",
+    "llvm.hexagon.V6.vsh.128B" => "__builtin_HEXAGON_V6_vsh_128B",
+    "llvm.hexagon.V6.vshufeh" => "__builtin_HEXAGON_V6_vshufeh",
+    "llvm.hexagon.V6.vshufeh.128B" => "__builtin_HEXAGON_V6_vshufeh_128B",
+    "llvm.hexagon.V6.vshuffb" => "__builtin_HEXAGON_V6_vshuffb",
+    "llvm.hexagon.V6.vshuffb.128B" => "__builtin_HEXAGON_V6_vshuffb_128B",
+    "llvm.hexagon.V6.vshuffeb" => "__builtin_HEXAGON_V6_vshuffeb",
+    "llvm.hexagon.V6.vshuffeb.128B" => "__builtin_HEXAGON_V6_vshuffeb_128B",
+    "llvm.hexagon.V6.vshuffh" => "__builtin_HEXAGON_V6_vshuffh",
+    "llvm.hexagon.V6.vshuffh.128B" => "__builtin_HEXAGON_V6_vshuffh_128B",
+    "llvm.hexagon.V6.vshuffob" => "__builtin_HEXAGON_V6_vshuffob",
+    "llvm.hexagon.V6.vshuffob.128B" => "__builtin_HEXAGON_V6_vshuffob_128B",
+    "llvm.hexagon.V6.vshuffvdd" => "__builtin_HEXAGON_V6_vshuffvdd",
+    "llvm.hexagon.V6.vshuffvdd.128B" => "__builtin_HEXAGON_V6_vshuffvdd_128B",
+    "llvm.hexagon.V6.vshufoeb" => "__builtin_HEXAGON_V6_vshufoeb",
+    "llvm.hexagon.V6.vshufoeb.128B" => "__builtin_HEXAGON_V6_vshufoeb_128B",
+    "llvm.hexagon.V6.vshufoeh" => "__builtin_HEXAGON_V6_vshufoeh",
+    "llvm.hexagon.V6.vshufoeh.128B" => "__builtin_HEXAGON_V6_vshufoeh_128B",
+    "llvm.hexagon.V6.vshufoh" => "__builtin_HEXAGON_V6_vshufoh",
+    "llvm.hexagon.V6.vshufoh.128B" => "__builtin_HEXAGON_V6_vshufoh_128B",
+    "llvm.hexagon.V6.vsubb" => "__builtin_HEXAGON_V6_vsubb",
+    "llvm.hexagon.V6.vsubb.128B" => "__builtin_HEXAGON_V6_vsubb_128B",
+    "llvm.hexagon.V6.vsubb.dv" => "__builtin_HEXAGON_V6_vsubb_dv",
+    "llvm.hexagon.V6.vsubb.dv.128B" => "__builtin_HEXAGON_V6_vsubb_dv_128B",
+    "llvm.hexagon.V6.vsubh" => "__builtin_HEXAGON_V6_vsubh",
+    "llvm.hexagon.V6.vsubh.128B" => "__builtin_HEXAGON_V6_vsubh_128B",
+    "llvm.hexagon.V6.vsubh.dv" => "__builtin_HEXAGON_V6_vsubh_dv",
+    "llvm.hexagon.V6.vsubh.dv.128B" => "__builtin_HEXAGON_V6_vsubh_dv_128B",
+    "llvm.hexagon.V6.vsubhsat" => "__builtin_HEXAGON_V6_vsubhsat",
+    "llvm.hexagon.V6.vsubhsat.128B" => "__builtin_HEXAGON_V6_vsubhsat_128B",
+    "llvm.hexagon.V6.vsubhsat.dv" => "__builtin_HEXAGON_V6_vsubhsat_dv",
+    "llvm.hexagon.V6.vsubhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubhsat_dv_128B",
+    "llvm.hexagon.V6.vsubhw" => "__builtin_HEXAGON_V6_vsubhw",
+    "llvm.hexagon.V6.vsubhw.128B" => "__builtin_HEXAGON_V6_vsubhw_128B",
+    "llvm.hexagon.V6.vsububh" => "__builtin_HEXAGON_V6_vsububh",
+    "llvm.hexagon.V6.vsububh.128B" => "__builtin_HEXAGON_V6_vsububh_128B",
+    "llvm.hexagon.V6.vsububsat" => "__builtin_HEXAGON_V6_vsububsat",
+    "llvm.hexagon.V6.vsububsat.128B" => "__builtin_HEXAGON_V6_vsububsat_128B",
+    "llvm.hexagon.V6.vsububsat.dv" => "__builtin_HEXAGON_V6_vsububsat_dv",
+    "llvm.hexagon.V6.vsububsat.dv.128B" => "__builtin_HEXAGON_V6_vsububsat_dv_128B",
+    "llvm.hexagon.V6.vsubuhsat" => "__builtin_HEXAGON_V6_vsubuhsat",
+    "llvm.hexagon.V6.vsubuhsat.128B" => "__builtin_HEXAGON_V6_vsubuhsat_128B",
+    "llvm.hexagon.V6.vsubuhsat.dv" => "__builtin_HEXAGON_V6_vsubuhsat_dv",
+    "llvm.hexagon.V6.vsubuhsat.dv.128B" => "__builtin_HEXAGON_V6_vsubuhsat_dv_128B",
+    "llvm.hexagon.V6.vsubuhw" => "__builtin_HEXAGON_V6_vsubuhw",
+    "llvm.hexagon.V6.vsubuhw.128B" => "__builtin_HEXAGON_V6_vsubuhw_128B",
+    "llvm.hexagon.V6.vsubw" => "__builtin_HEXAGON_V6_vsubw",
+    "llvm.hexagon.V6.vsubw.128B" => "__builtin_HEXAGON_V6_vsubw_128B",
+    "llvm.hexagon.V6.vsubw.dv" => "__builtin_HEXAGON_V6_vsubw_dv",
+    "llvm.hexagon.V6.vsubw.dv.128B" => "__builtin_HEXAGON_V6_vsubw_dv_128B",
+    "llvm.hexagon.V6.vsubwsat" => "__builtin_HEXAGON_V6_vsubwsat",
+    "llvm.hexagon.V6.vsubwsat.128B" => "__builtin_HEXAGON_V6_vsubwsat_128B",
+    "llvm.hexagon.V6.vsubwsat.dv" => "__builtin_HEXAGON_V6_vsubwsat_dv",
+    "llvm.hexagon.V6.vsubwsat.dv.128B" => "__builtin_HEXAGON_V6_vsubwsat_dv_128B",
+    "llvm.hexagon.V6.vtmpyb" => "__builtin_HEXAGON_V6_vtmpyb",
+    "llvm.hexagon.V6.vtmpyb.128B" => "__builtin_HEXAGON_V6_vtmpyb_128B",
+    "llvm.hexagon.V6.vtmpyb.acc" => "__builtin_HEXAGON_V6_vtmpyb_acc",
+    "llvm.hexagon.V6.vtmpyb.acc.128B" => "__builtin_HEXAGON_V6_vtmpyb_acc_128B",
+    "llvm.hexagon.V6.vtmpybus" => "__builtin_HEXAGON_V6_vtmpybus",
+    "llvm.hexagon.V6.vtmpybus.128B" => "__builtin_HEXAGON_V6_vtmpybus_128B",
+    "llvm.hexagon.V6.vtmpybus.acc" => "__builtin_HEXAGON_V6_vtmpybus_acc",
+    "llvm.hexagon.V6.vtmpybus.acc.128B" => "__builtin_HEXAGON_V6_vtmpybus_acc_128B",
+    "llvm.hexagon.V6.vtmpyhb" => "__builtin_HEXAGON_V6_vtmpyhb",
+    "llvm.hexagon.V6.vtmpyhb.128B" => "__builtin_HEXAGON_V6_vtmpyhb_128B",
+    "llvm.hexagon.V6.vtmpyhb.acc" => "__builtin_HEXAGON_V6_vtmpyhb_acc",
+    "llvm.hexagon.V6.vtmpyhb.acc.128B" => "__builtin_HEXAGON_V6_vtmpyhb_acc_128B",
+    "llvm.hexagon.V6.vunpackb" => "__builtin_HEXAGON_V6_vunpackb",
+    "llvm.hexagon.V6.vunpackb.128B" => "__builtin_HEXAGON_V6_vunpackb_128B",
+    "llvm.hexagon.V6.vunpackh" => "__builtin_HEXAGON_V6_vunpackh",
+    "llvm.hexagon.V6.vunpackh.128B" => "__builtin_HEXAGON_V6_vunpackh_128B",
+    "llvm.hexagon.V6.vunpackob" => "__builtin_HEXAGON_V6_vunpackob",
+    "llvm.hexagon.V6.vunpackob.128B" => "__builtin_HEXAGON_V6_vunpackob_128B",
+    "llvm.hexagon.V6.vunpackoh" => "__builtin_HEXAGON_V6_vunpackoh",
+    "llvm.hexagon.V6.vunpackoh.128B" => "__builtin_HEXAGON_V6_vunpackoh_128B",
+    "llvm.hexagon.V6.vunpackub" => "__builtin_HEXAGON_V6_vunpackub",
+    "llvm.hexagon.V6.vunpackub.128B" => "__builtin_HEXAGON_V6_vunpackub_128B",
+    "llvm.hexagon.V6.vunpackuh" => "__builtin_HEXAGON_V6_vunpackuh",
+    "llvm.hexagon.V6.vunpackuh.128B" => "__builtin_HEXAGON_V6_vunpackuh_128B",
+    "llvm.hexagon.V6.vxor" => "__builtin_HEXAGON_V6_vxor",
+    "llvm.hexagon.V6.vxor.128B" => "__builtin_HEXAGON_V6_vxor_128B",
+    "llvm.hexagon.V6.vzb" => "__builtin_HEXAGON_V6_vzb",
+    "llvm.hexagon.V6.vzb.128B" => "__builtin_HEXAGON_V6_vzb_128B",
+    "llvm.hexagon.V6.vzh" => "__builtin_HEXAGON_V6_vzh",
+    "llvm.hexagon.V6.vzh.128B" => "__builtin_HEXAGON_V6_vzh_128B",
+    "llvm.hexagon.brev.ldb" => "__builtin_brev_ldb",
+    "llvm.hexagon.brev.ldd" => "__builtin_brev_ldd",
+    "llvm.hexagon.brev.ldh" => "__builtin_brev_ldh",
+    "llvm.hexagon.brev.ldub" => "__builtin_brev_ldub",
+    "llvm.hexagon.brev.lduh" => "__builtin_brev_lduh",
+    "llvm.hexagon.brev.ldw" => "__builtin_brev_ldw",
+    "llvm.hexagon.brev.stb" => "__builtin_brev_stb",
+    "llvm.hexagon.brev.std" => "__builtin_brev_std",
+    "llvm.hexagon.brev.sth" => "__builtin_brev_sth",
+    "llvm.hexagon.brev.sthhi" => "__builtin_brev_sthhi",
+    "llvm.hexagon.brev.stw" => "__builtin_brev_stw",
+    "llvm.hexagon.circ.ldb" => "__builtin_circ_ldb",
+    "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd",
+    "llvm.hexagon.circ.ldh" => "__builtin_circ_ldh",
+    "llvm.hexagon.circ.ldub" => "__builtin_circ_ldub",
+    "llvm.hexagon.circ.lduh" => "__builtin_circ_lduh",
+    "llvm.hexagon.circ.ldw" => "__builtin_circ_ldw",
+    "llvm.hexagon.circ.stb" => "__builtin_circ_stb",
+    "llvm.hexagon.circ.std" => "__builtin_circ_std",
+    "llvm.hexagon.circ.sth" => "__builtin_circ_sth",
+    "llvm.hexagon.circ.sthhi" => "__builtin_circ_sthhi",
+    "llvm.hexagon.circ.stw" => "__builtin_circ_stw",
+    "llvm.hexagon.mm256i.vaddw" => "__builtin__mm256i_vaddw",
+    "llvm.hexagon.prefetch" => "__builtin_HEXAGON_prefetch",
+    // mips
+    "llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph",
+    "llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb",
+    "llvm.mips.absq.s.w" => "__builtin_mips_absq_s_w",
+    "llvm.mips.add.a.b" => "__builtin_msa_add_a_b",
+    "llvm.mips.add.a.d" => "__builtin_msa_add_a_d",
+    "llvm.mips.add.a.h" => "__builtin_msa_add_a_h",
+    "llvm.mips.add.a.w" => "__builtin_msa_add_a_w",
+    "llvm.mips.addq.ph" => "__builtin_mips_addq_ph",
+    "llvm.mips.addq.s.ph" => "__builtin_mips_addq_s_ph",
+    "llvm.mips.addq.s.w" => "__builtin_mips_addq_s_w",
+    "llvm.mips.addqh.ph" => "__builtin_mips_addqh_ph",
+    "llvm.mips.addqh.r.ph" => "__builtin_mips_addqh_r_ph",
+    "llvm.mips.addqh.r.w" => "__builtin_mips_addqh_r_w",
+    "llvm.mips.addqh.w" => "__builtin_mips_addqh_w",
+    "llvm.mips.adds.a.b" => "__builtin_msa_adds_a_b",
+    "llvm.mips.adds.a.d" => "__builtin_msa_adds_a_d",
+    "llvm.mips.adds.a.h" => "__builtin_msa_adds_a_h",
+    "llvm.mips.adds.a.w" => "__builtin_msa_adds_a_w",
+    "llvm.mips.adds.s.b" => "__builtin_msa_adds_s_b",
+    "llvm.mips.adds.s.d" => "__builtin_msa_adds_s_d",
+    "llvm.mips.adds.s.h" => "__builtin_msa_adds_s_h",
+    "llvm.mips.adds.s.w" => "__builtin_msa_adds_s_w",
+    "llvm.mips.adds.u.b" => "__builtin_msa_adds_u_b",
+    "llvm.mips.adds.u.d" => "__builtin_msa_adds_u_d",
+    "llvm.mips.adds.u.h" => "__builtin_msa_adds_u_h",
+    "llvm.mips.adds.u.w" => "__builtin_msa_adds_u_w",
+    "llvm.mips.addsc" => "__builtin_mips_addsc",
+    "llvm.mips.addu.ph" => "__builtin_mips_addu_ph",
+    "llvm.mips.addu.qb" => "__builtin_mips_addu_qb",
+    "llvm.mips.addu.s.ph" => "__builtin_mips_addu_s_ph",
+    "llvm.mips.addu.s.qb" => "__builtin_mips_addu_s_qb",
+    "llvm.mips.adduh.qb" => "__builtin_mips_adduh_qb",
+    "llvm.mips.adduh.r.qb" => "__builtin_mips_adduh_r_qb",
+    "llvm.mips.addv.b" => "__builtin_msa_addv_b",
+    "llvm.mips.addv.d" => "__builtin_msa_addv_d",
+    "llvm.mips.addv.h" => "__builtin_msa_addv_h",
+    "llvm.mips.addv.w" => "__builtin_msa_addv_w",
+    "llvm.mips.addvi.b" => "__builtin_msa_addvi_b",
+    "llvm.mips.addvi.d" => "__builtin_msa_addvi_d",
+    "llvm.mips.addvi.h" => "__builtin_msa_addvi_h",
+    "llvm.mips.addvi.w" => "__builtin_msa_addvi_w",
+    "llvm.mips.addwc" => "__builtin_mips_addwc",
+    "llvm.mips.and.v" => "__builtin_msa_and_v",
+    "llvm.mips.andi.b" => "__builtin_msa_andi_b",
+    "llvm.mips.append" => "__builtin_mips_append",
+    "llvm.mips.asub.s.b" => "__builtin_msa_asub_s_b",
+    "llvm.mips.asub.s.d" => "__builtin_msa_asub_s_d",
+    "llvm.mips.asub.s.h" => "__builtin_msa_asub_s_h",
+    "llvm.mips.asub.s.w" => "__builtin_msa_asub_s_w",
+    "llvm.mips.asub.u.b" => "__builtin_msa_asub_u_b",
+    "llvm.mips.asub.u.d" => "__builtin_msa_asub_u_d",
+    "llvm.mips.asub.u.h" => "__builtin_msa_asub_u_h",
+    "llvm.mips.asub.u.w" => "__builtin_msa_asub_u_w",
+    "llvm.mips.ave.s.b" => "__builtin_msa_ave_s_b",
+    "llvm.mips.ave.s.d" => "__builtin_msa_ave_s_d",
+    "llvm.mips.ave.s.h" => "__builtin_msa_ave_s_h",
+    "llvm.mips.ave.s.w" => "__builtin_msa_ave_s_w",
+    "llvm.mips.ave.u.b" => "__builtin_msa_ave_u_b",
+    "llvm.mips.ave.u.d" => "__builtin_msa_ave_u_d",
+    "llvm.mips.ave.u.h" => "__builtin_msa_ave_u_h",
+    "llvm.mips.ave.u.w" => "__builtin_msa_ave_u_w",
+    "llvm.mips.aver.s.b" => "__builtin_msa_aver_s_b",
+    "llvm.mips.aver.s.d" => "__builtin_msa_aver_s_d",
+    "llvm.mips.aver.s.h" => "__builtin_msa_aver_s_h",
+    "llvm.mips.aver.s.w" => "__builtin_msa_aver_s_w",
+    "llvm.mips.aver.u.b" => "__builtin_msa_aver_u_b",
+    "llvm.mips.aver.u.d" => "__builtin_msa_aver_u_d",
+    "llvm.mips.aver.u.h" => "__builtin_msa_aver_u_h",
+    "llvm.mips.aver.u.w" => "__builtin_msa_aver_u_w",
+    "llvm.mips.balign" => "__builtin_mips_balign",
+    "llvm.mips.bclr.b" => "__builtin_msa_bclr_b",
+    "llvm.mips.bclr.d" => "__builtin_msa_bclr_d",
+    "llvm.mips.bclr.h" => "__builtin_msa_bclr_h",
+    "llvm.mips.bclr.w" => "__builtin_msa_bclr_w",
+    "llvm.mips.bclri.b" => "__builtin_msa_bclri_b",
+    "llvm.mips.bclri.d" => "__builtin_msa_bclri_d",
+    "llvm.mips.bclri.h" => "__builtin_msa_bclri_h",
+    "llvm.mips.bclri.w" => "__builtin_msa_bclri_w",
+    "llvm.mips.binsl.b" => "__builtin_msa_binsl_b",
+    "llvm.mips.binsl.d" => "__builtin_msa_binsl_d",
+    "llvm.mips.binsl.h" => "__builtin_msa_binsl_h",
+    "llvm.mips.binsl.w" => "__builtin_msa_binsl_w",
+    "llvm.mips.binsli.b" => "__builtin_msa_binsli_b",
+    "llvm.mips.binsli.d" => "__builtin_msa_binsli_d",
+    "llvm.mips.binsli.h" => "__builtin_msa_binsli_h",
+    "llvm.mips.binsli.w" => "__builtin_msa_binsli_w",
+    "llvm.mips.binsr.b" => "__builtin_msa_binsr_b",
+    "llvm.mips.binsr.d" => "__builtin_msa_binsr_d",
+    "llvm.mips.binsr.h" => "__builtin_msa_binsr_h",
+    "llvm.mips.binsr.w" => "__builtin_msa_binsr_w",
+    "llvm.mips.binsri.b" => "__builtin_msa_binsri_b",
+    "llvm.mips.binsri.d" => "__builtin_msa_binsri_d",
+    "llvm.mips.binsri.h" => "__builtin_msa_binsri_h",
+    "llvm.mips.binsri.w" => "__builtin_msa_binsri_w",
+    "llvm.mips.bitrev" => "__builtin_mips_bitrev",
+    "llvm.mips.bmnz.v" => "__builtin_msa_bmnz_v",
+    "llvm.mips.bmnzi.b" => "__builtin_msa_bmnzi_b",
+    "llvm.mips.bmz.v" => "__builtin_msa_bmz_v",
+    "llvm.mips.bmzi.b" => "__builtin_msa_bmzi_b",
+    "llvm.mips.bneg.b" => "__builtin_msa_bneg_b",
+    "llvm.mips.bneg.d" => "__builtin_msa_bneg_d",
+    "llvm.mips.bneg.h" => "__builtin_msa_bneg_h",
+    "llvm.mips.bneg.w" => "__builtin_msa_bneg_w",
+    "llvm.mips.bnegi.b" => "__builtin_msa_bnegi_b",
+    "llvm.mips.bnegi.d" => "__builtin_msa_bnegi_d",
+    "llvm.mips.bnegi.h" => "__builtin_msa_bnegi_h",
+    "llvm.mips.bnegi.w" => "__builtin_msa_bnegi_w",
+    "llvm.mips.bnz.b" => "__builtin_msa_bnz_b",
+    "llvm.mips.bnz.d" => "__builtin_msa_bnz_d",
+    "llvm.mips.bnz.h" => "__builtin_msa_bnz_h",
+    "llvm.mips.bnz.v" => "__builtin_msa_bnz_v",
+    "llvm.mips.bnz.w" => "__builtin_msa_bnz_w",
+    "llvm.mips.bposge32" => "__builtin_mips_bposge32",
+    "llvm.mips.bsel.v" => "__builtin_msa_bsel_v",
+    "llvm.mips.bseli.b" => "__builtin_msa_bseli_b",
+    "llvm.mips.bset.b" => "__builtin_msa_bset_b",
+    "llvm.mips.bset.d" => "__builtin_msa_bset_d",
+    "llvm.mips.bset.h" => "__builtin_msa_bset_h",
+    "llvm.mips.bset.w" => "__builtin_msa_bset_w",
+    "llvm.mips.bseti.b" => "__builtin_msa_bseti_b",
+    "llvm.mips.bseti.d" => "__builtin_msa_bseti_d",
+    "llvm.mips.bseti.h" => "__builtin_msa_bseti_h",
+    "llvm.mips.bseti.w" => "__builtin_msa_bseti_w",
+    "llvm.mips.bz.b" => "__builtin_msa_bz_b",
+    "llvm.mips.bz.d" => "__builtin_msa_bz_d",
+    "llvm.mips.bz.h" => "__builtin_msa_bz_h",
+    "llvm.mips.bz.v" => "__builtin_msa_bz_v",
+    "llvm.mips.bz.w" => "__builtin_msa_bz_w",
+    "llvm.mips.ceq.b" => "__builtin_msa_ceq_b",
+    "llvm.mips.ceq.d" => "__builtin_msa_ceq_d",
+    "llvm.mips.ceq.h" => "__builtin_msa_ceq_h",
+    "llvm.mips.ceq.w" => "__builtin_msa_ceq_w",
+    "llvm.mips.ceqi.b" => "__builtin_msa_ceqi_b",
+    "llvm.mips.ceqi.d" => "__builtin_msa_ceqi_d",
+    "llvm.mips.ceqi.h" => "__builtin_msa_ceqi_h",
+    "llvm.mips.ceqi.w" => "__builtin_msa_ceqi_w",
+    "llvm.mips.cfcmsa" => "__builtin_msa_cfcmsa",
+    "llvm.mips.cle.s.b" => "__builtin_msa_cle_s_b",
+    "llvm.mips.cle.s.d" => "__builtin_msa_cle_s_d",
+    "llvm.mips.cle.s.h" => "__builtin_msa_cle_s_h",
+    "llvm.mips.cle.s.w" => "__builtin_msa_cle_s_w",
+    "llvm.mips.cle.u.b" => "__builtin_msa_cle_u_b",
+    "llvm.mips.cle.u.d" => "__builtin_msa_cle_u_d",
+    "llvm.mips.cle.u.h" => "__builtin_msa_cle_u_h",
+    "llvm.mips.cle.u.w" => "__builtin_msa_cle_u_w",
+    "llvm.mips.clei.s.b" => "__builtin_msa_clei_s_b",
+    "llvm.mips.clei.s.d" => "__builtin_msa_clei_s_d",
+    "llvm.mips.clei.s.h" => "__builtin_msa_clei_s_h",
+    "llvm.mips.clei.s.w" => "__builtin_msa_clei_s_w",
+    "llvm.mips.clei.u.b" => "__builtin_msa_clei_u_b",
+    "llvm.mips.clei.u.d" => "__builtin_msa_clei_u_d",
+    "llvm.mips.clei.u.h" => "__builtin_msa_clei_u_h",
+    "llvm.mips.clei.u.w" => "__builtin_msa_clei_u_w",
+    "llvm.mips.clt.s.b" => "__builtin_msa_clt_s_b",
+    "llvm.mips.clt.s.d" => "__builtin_msa_clt_s_d",
+    "llvm.mips.clt.s.h" => "__builtin_msa_clt_s_h",
+    "llvm.mips.clt.s.w" => "__builtin_msa_clt_s_w",
+    "llvm.mips.clt.u.b" => "__builtin_msa_clt_u_b",
+    "llvm.mips.clt.u.d" => "__builtin_msa_clt_u_d",
+    "llvm.mips.clt.u.h" => "__builtin_msa_clt_u_h",
+    "llvm.mips.clt.u.w" => "__builtin_msa_clt_u_w",
+    "llvm.mips.clti.s.b" => "__builtin_msa_clti_s_b",
+    "llvm.mips.clti.s.d" => "__builtin_msa_clti_s_d",
+    "llvm.mips.clti.s.h" => "__builtin_msa_clti_s_h",
+    "llvm.mips.clti.s.w" => "__builtin_msa_clti_s_w",
+    "llvm.mips.clti.u.b" => "__builtin_msa_clti_u_b",
+    "llvm.mips.clti.u.d" => "__builtin_msa_clti_u_d",
+    "llvm.mips.clti.u.h" => "__builtin_msa_clti_u_h",
+    "llvm.mips.clti.u.w" => "__builtin_msa_clti_u_w",
+    "llvm.mips.cmp.eq.ph" => "__builtin_mips_cmp_eq_ph",
+    "llvm.mips.cmp.le.ph" => "__builtin_mips_cmp_le_ph",
+    "llvm.mips.cmp.lt.ph" => "__builtin_mips_cmp_lt_ph",
+    "llvm.mips.cmpgdu.eq.qb" => "__builtin_mips_cmpgdu_eq_qb",
+    "llvm.mips.cmpgdu.le.qb" => "__builtin_mips_cmpgdu_le_qb",
+    "llvm.mips.cmpgdu.lt.qb" => "__builtin_mips_cmpgdu_lt_qb",
+    "llvm.mips.cmpgu.eq.qb" => "__builtin_mips_cmpgu_eq_qb",
+    "llvm.mips.cmpgu.le.qb" => "__builtin_mips_cmpgu_le_qb",
+    "llvm.mips.cmpgu.lt.qb" => "__builtin_mips_cmpgu_lt_qb",
+    "llvm.mips.cmpu.eq.qb" => "__builtin_mips_cmpu_eq_qb",
+    "llvm.mips.cmpu.le.qb" => "__builtin_mips_cmpu_le_qb",
+    "llvm.mips.cmpu.lt.qb" => "__builtin_mips_cmpu_lt_qb",
+    "llvm.mips.copy.s.b" => "__builtin_msa_copy_s_b",
+    "llvm.mips.copy.s.d" => "__builtin_msa_copy_s_d",
+    "llvm.mips.copy.s.h" => "__builtin_msa_copy_s_h",
+    "llvm.mips.copy.s.w" => "__builtin_msa_copy_s_w",
+    "llvm.mips.copy.u.b" => "__builtin_msa_copy_u_b",
+    "llvm.mips.copy.u.d" => "__builtin_msa_copy_u_d",
+    "llvm.mips.copy.u.h" => "__builtin_msa_copy_u_h",
+    "llvm.mips.copy.u.w" => "__builtin_msa_copy_u_w",
+    "llvm.mips.ctcmsa" => "__builtin_msa_ctcmsa",
+    "llvm.mips.div.s.b" => "__builtin_msa_div_s_b",
+    "llvm.mips.div.s.d" => "__builtin_msa_div_s_d",
+    "llvm.mips.div.s.h" => "__builtin_msa_div_s_h",
+    "llvm.mips.div.s.w" => "__builtin_msa_div_s_w",
+    "llvm.mips.div.u.b" => "__builtin_msa_div_u_b",
+    "llvm.mips.div.u.d" => "__builtin_msa_div_u_d",
+    "llvm.mips.div.u.h" => "__builtin_msa_div_u_h",
+    "llvm.mips.div.u.w" => "__builtin_msa_div_u_w",
+    "llvm.mips.dlsa" => "__builtin_mips_dlsa",
+    "llvm.mips.dotp.s.d" => "__builtin_msa_dotp_s_d",
+    "llvm.mips.dotp.s.h" => "__builtin_msa_dotp_s_h",
+    "llvm.mips.dotp.s.w" => "__builtin_msa_dotp_s_w",
+    "llvm.mips.dotp.u.d" => "__builtin_msa_dotp_u_d",
+    "llvm.mips.dotp.u.h" => "__builtin_msa_dotp_u_h",
+    "llvm.mips.dotp.u.w" => "__builtin_msa_dotp_u_w",
+    "llvm.mips.dpa.w.ph" => "__builtin_mips_dpa_w_ph",
+    "llvm.mips.dpadd.s.d" => "__builtin_msa_dpadd_s_d",
+    "llvm.mips.dpadd.s.h" => "__builtin_msa_dpadd_s_h",
+    "llvm.mips.dpadd.s.w" => "__builtin_msa_dpadd_s_w",
+    "llvm.mips.dpadd.u.d" => "__builtin_msa_dpadd_u_d",
+    "llvm.mips.dpadd.u.h" => "__builtin_msa_dpadd_u_h",
+    "llvm.mips.dpadd.u.w" => "__builtin_msa_dpadd_u_w",
+    "llvm.mips.dpaq.s.w.ph" => "__builtin_mips_dpaq_s_w_ph",
+    "llvm.mips.dpaq.sa.l.w" => "__builtin_mips_dpaq_sa_l_w",
+    "llvm.mips.dpaqx.s.w.ph" => "__builtin_mips_dpaqx_s_w_ph",
+    "llvm.mips.dpaqx.sa.w.ph" => "__builtin_mips_dpaqx_sa_w_ph",
+    "llvm.mips.dpau.h.qbl" => "__builtin_mips_dpau_h_qbl",
+    "llvm.mips.dpau.h.qbr" => "__builtin_mips_dpau_h_qbr",
+    "llvm.mips.dpax.w.ph" => "__builtin_mips_dpax_w_ph",
+    "llvm.mips.dps.w.ph" => "__builtin_mips_dps_w_ph",
+    "llvm.mips.dpsq.s.w.ph" => "__builtin_mips_dpsq_s_w_ph",
+    "llvm.mips.dpsq.sa.l.w" => "__builtin_mips_dpsq_sa_l_w",
+    "llvm.mips.dpsqx.s.w.ph" => "__builtin_mips_dpsqx_s_w_ph",
+    "llvm.mips.dpsqx.sa.w.ph" => "__builtin_mips_dpsqx_sa_w_ph",
+    "llvm.mips.dpsu.h.qbl" => "__builtin_mips_dpsu_h_qbl",
+    "llvm.mips.dpsu.h.qbr" => "__builtin_mips_dpsu_h_qbr",
+    "llvm.mips.dpsub.s.d" => "__builtin_msa_dpsub_s_d",
+    "llvm.mips.dpsub.s.h" => "__builtin_msa_dpsub_s_h",
+    "llvm.mips.dpsub.s.w" => "__builtin_msa_dpsub_s_w",
+    "llvm.mips.dpsub.u.d" => "__builtin_msa_dpsub_u_d",
+    "llvm.mips.dpsub.u.h" => "__builtin_msa_dpsub_u_h",
+    "llvm.mips.dpsub.u.w" => "__builtin_msa_dpsub_u_w",
+    "llvm.mips.dpsx.w.ph" => "__builtin_mips_dpsx_w_ph",
+    "llvm.mips.extp" => "__builtin_mips_extp",
+    "llvm.mips.extpdp" => "__builtin_mips_extpdp",
+    "llvm.mips.extr.r.w" => "__builtin_mips_extr_r_w",
+    "llvm.mips.extr.rs.w" => "__builtin_mips_extr_rs_w",
+    "llvm.mips.extr.s.h" => "__builtin_mips_extr_s_h",
+    "llvm.mips.extr.w" => "__builtin_mips_extr_w",
+    "llvm.mips.fadd.d" => "__builtin_msa_fadd_d",
+    "llvm.mips.fadd.w" => "__builtin_msa_fadd_w",
+    "llvm.mips.fcaf.d" => "__builtin_msa_fcaf_d",
+    "llvm.mips.fcaf.w" => "__builtin_msa_fcaf_w",
+    "llvm.mips.fceq.d" => "__builtin_msa_fceq_d",
+    "llvm.mips.fceq.w" => "__builtin_msa_fceq_w",
+    "llvm.mips.fclass.d" => "__builtin_msa_fclass_d",
+    "llvm.mips.fclass.w" => "__builtin_msa_fclass_w",
+    "llvm.mips.fcle.d" => "__builtin_msa_fcle_d",
+    "llvm.mips.fcle.w" => "__builtin_msa_fcle_w",
+    "llvm.mips.fclt.d" => "__builtin_msa_fclt_d",
+    "llvm.mips.fclt.w" => "__builtin_msa_fclt_w",
+    "llvm.mips.fcne.d" => "__builtin_msa_fcne_d",
+    "llvm.mips.fcne.w" => "__builtin_msa_fcne_w",
+    "llvm.mips.fcor.d" => "__builtin_msa_fcor_d",
+    "llvm.mips.fcor.w" => "__builtin_msa_fcor_w",
+    "llvm.mips.fcueq.d" => "__builtin_msa_fcueq_d",
+    "llvm.mips.fcueq.w" => "__builtin_msa_fcueq_w",
+    "llvm.mips.fcule.d" => "__builtin_msa_fcule_d",
+    "llvm.mips.fcule.w" => "__builtin_msa_fcule_w",
+    "llvm.mips.fcult.d" => "__builtin_msa_fcult_d",
+    "llvm.mips.fcult.w" => "__builtin_msa_fcult_w",
+    "llvm.mips.fcun.d" => "__builtin_msa_fcun_d",
+    "llvm.mips.fcun.w" => "__builtin_msa_fcun_w",
+    "llvm.mips.fcune.d" => "__builtin_msa_fcune_d",
+    "llvm.mips.fcune.w" => "__builtin_msa_fcune_w",
+    "llvm.mips.fdiv.d" => "__builtin_msa_fdiv_d",
+    "llvm.mips.fdiv.w" => "__builtin_msa_fdiv_w",
+    "llvm.mips.fexdo.h" => "__builtin_msa_fexdo_h",
+    "llvm.mips.fexdo.w" => "__builtin_msa_fexdo_w",
+    "llvm.mips.fexp2.d" => "__builtin_msa_fexp2_d",
+    "llvm.mips.fexp2.w" => "__builtin_msa_fexp2_w",
+    "llvm.mips.fexupl.d" => "__builtin_msa_fexupl_d",
+    "llvm.mips.fexupl.w" => "__builtin_msa_fexupl_w",
+    "llvm.mips.fexupr.d" => "__builtin_msa_fexupr_d",
+    "llvm.mips.fexupr.w" => "__builtin_msa_fexupr_w",
+    "llvm.mips.ffint.s.d" => "__builtin_msa_ffint_s_d",
+    "llvm.mips.ffint.s.w" => "__builtin_msa_ffint_s_w",
+    "llvm.mips.ffint.u.d" => "__builtin_msa_ffint_u_d",
+    "llvm.mips.ffint.u.w" => "__builtin_msa_ffint_u_w",
+    "llvm.mips.ffql.d" => "__builtin_msa_ffql_d",
+    "llvm.mips.ffql.w" => "__builtin_msa_ffql_w",
+    "llvm.mips.ffqr.d" => "__builtin_msa_ffqr_d",
+    "llvm.mips.ffqr.w" => "__builtin_msa_ffqr_w",
+    "llvm.mips.fill.b" => "__builtin_msa_fill_b",
+    "llvm.mips.fill.d" => "__builtin_msa_fill_d",
+    "llvm.mips.fill.h" => "__builtin_msa_fill_h",
+    "llvm.mips.fill.w" => "__builtin_msa_fill_w",
+    "llvm.mips.flog2.d" => "__builtin_msa_flog2_d",
+    "llvm.mips.flog2.w" => "__builtin_msa_flog2_w",
+    "llvm.mips.fmadd.d" => "__builtin_msa_fmadd_d",
+    "llvm.mips.fmadd.w" => "__builtin_msa_fmadd_w",
+    "llvm.mips.fmax.a.d" => "__builtin_msa_fmax_a_d",
+    "llvm.mips.fmax.a.w" => "__builtin_msa_fmax_a_w",
+    "llvm.mips.fmax.d" => "__builtin_msa_fmax_d",
+    "llvm.mips.fmax.w" => "__builtin_msa_fmax_w",
+    "llvm.mips.fmin.a.d" => "__builtin_msa_fmin_a_d",
+    "llvm.mips.fmin.a.w" => "__builtin_msa_fmin_a_w",
+    "llvm.mips.fmin.d" => "__builtin_msa_fmin_d",
+    "llvm.mips.fmin.w" => "__builtin_msa_fmin_w",
+    "llvm.mips.fmsub.d" => "__builtin_msa_fmsub_d",
+    "llvm.mips.fmsub.w" => "__builtin_msa_fmsub_w",
+    "llvm.mips.fmul.d" => "__builtin_msa_fmul_d",
+    "llvm.mips.fmul.w" => "__builtin_msa_fmul_w",
+    "llvm.mips.frcp.d" => "__builtin_msa_frcp_d",
+    "llvm.mips.frcp.w" => "__builtin_msa_frcp_w",
+    "llvm.mips.frint.d" => "__builtin_msa_frint_d",
+    "llvm.mips.frint.w" => "__builtin_msa_frint_w",
+    "llvm.mips.frsqrt.d" => "__builtin_msa_frsqrt_d",
+    "llvm.mips.frsqrt.w" => "__builtin_msa_frsqrt_w",
+    "llvm.mips.fsaf.d" => "__builtin_msa_fsaf_d",
+    "llvm.mips.fsaf.w" => "__builtin_msa_fsaf_w",
+    "llvm.mips.fseq.d" => "__builtin_msa_fseq_d",
+    "llvm.mips.fseq.w" => "__builtin_msa_fseq_w",
+    "llvm.mips.fsle.d" => "__builtin_msa_fsle_d",
+    "llvm.mips.fsle.w" => "__builtin_msa_fsle_w",
+    "llvm.mips.fslt.d" => "__builtin_msa_fslt_d",
+    "llvm.mips.fslt.w" => "__builtin_msa_fslt_w",
+    "llvm.mips.fsne.d" => "__builtin_msa_fsne_d",
+    "llvm.mips.fsne.w" => "__builtin_msa_fsne_w",
+    "llvm.mips.fsor.d" => "__builtin_msa_fsor_d",
+    "llvm.mips.fsor.w" => "__builtin_msa_fsor_w",
+    "llvm.mips.fsqrt.d" => "__builtin_msa_fsqrt_d",
+    "llvm.mips.fsqrt.w" => "__builtin_msa_fsqrt_w",
+    "llvm.mips.fsub.d" => "__builtin_msa_fsub_d",
+    "llvm.mips.fsub.w" => "__builtin_msa_fsub_w",
+    "llvm.mips.fsueq.d" => "__builtin_msa_fsueq_d",
+    "llvm.mips.fsueq.w" => "__builtin_msa_fsueq_w",
+    "llvm.mips.fsule.d" => "__builtin_msa_fsule_d",
+    "llvm.mips.fsule.w" => "__builtin_msa_fsule_w",
+    "llvm.mips.fsult.d" => "__builtin_msa_fsult_d",
+    "llvm.mips.fsult.w" => "__builtin_msa_fsult_w",
+    "llvm.mips.fsun.d" => "__builtin_msa_fsun_d",
+    "llvm.mips.fsun.w" => "__builtin_msa_fsun_w",
+    "llvm.mips.fsune.d" => "__builtin_msa_fsune_d",
+    "llvm.mips.fsune.w" => "__builtin_msa_fsune_w",
+    "llvm.mips.ftint.s.d" => "__builtin_msa_ftint_s_d",
+    "llvm.mips.ftint.s.w" => "__builtin_msa_ftint_s_w",
+    "llvm.mips.ftint.u.d" => "__builtin_msa_ftint_u_d",
+    "llvm.mips.ftint.u.w" => "__builtin_msa_ftint_u_w",
+    "llvm.mips.ftq.h" => "__builtin_msa_ftq_h",
+    "llvm.mips.ftq.w" => "__builtin_msa_ftq_w",
+    "llvm.mips.ftrunc.s.d" => "__builtin_msa_ftrunc_s_d",
+    "llvm.mips.ftrunc.s.w" => "__builtin_msa_ftrunc_s_w",
+    "llvm.mips.ftrunc.u.d" => "__builtin_msa_ftrunc_u_d",
+    "llvm.mips.ftrunc.u.w" => "__builtin_msa_ftrunc_u_w",
+    "llvm.mips.hadd.s.d" => "__builtin_msa_hadd_s_d",
+    "llvm.mips.hadd.s.h" => "__builtin_msa_hadd_s_h",
+    "llvm.mips.hadd.s.w" => "__builtin_msa_hadd_s_w",
+    "llvm.mips.hadd.u.d" => "__builtin_msa_hadd_u_d",
+    "llvm.mips.hadd.u.h" => "__builtin_msa_hadd_u_h",
+    "llvm.mips.hadd.u.w" => "__builtin_msa_hadd_u_w",
+    "llvm.mips.hsub.s.d" => "__builtin_msa_hsub_s_d",
+    "llvm.mips.hsub.s.h" => "__builtin_msa_hsub_s_h",
+    "llvm.mips.hsub.s.w" => "__builtin_msa_hsub_s_w",
+    "llvm.mips.hsub.u.d" => "__builtin_msa_hsub_u_d",
+    "llvm.mips.hsub.u.h" => "__builtin_msa_hsub_u_h",
+    "llvm.mips.hsub.u.w" => "__builtin_msa_hsub_u_w",
+    "llvm.mips.ilvev.b" => "__builtin_msa_ilvev_b",
+    "llvm.mips.ilvev.d" => "__builtin_msa_ilvev_d",
+    "llvm.mips.ilvev.h" => "__builtin_msa_ilvev_h",
+    "llvm.mips.ilvev.w" => "__builtin_msa_ilvev_w",
+    "llvm.mips.ilvl.b" => "__builtin_msa_ilvl_b",
+    "llvm.mips.ilvl.d" => "__builtin_msa_ilvl_d",
+    "llvm.mips.ilvl.h" => "__builtin_msa_ilvl_h",
+    "llvm.mips.ilvl.w" => "__builtin_msa_ilvl_w",
+    "llvm.mips.ilvod.b" => "__builtin_msa_ilvod_b",
+    "llvm.mips.ilvod.d" => "__builtin_msa_ilvod_d",
+    "llvm.mips.ilvod.h" => "__builtin_msa_ilvod_h",
+    "llvm.mips.ilvod.w" => "__builtin_msa_ilvod_w",
+    "llvm.mips.ilvr.b" => "__builtin_msa_ilvr_b",
+    "llvm.mips.ilvr.d" => "__builtin_msa_ilvr_d",
+    "llvm.mips.ilvr.h" => "__builtin_msa_ilvr_h",
+    "llvm.mips.ilvr.w" => "__builtin_msa_ilvr_w",
+    "llvm.mips.insert.b" => "__builtin_msa_insert_b",
+    "llvm.mips.insert.d" => "__builtin_msa_insert_d",
+    "llvm.mips.insert.h" => "__builtin_msa_insert_h",
+    "llvm.mips.insert.w" => "__builtin_msa_insert_w",
+    "llvm.mips.insv" => "__builtin_mips_insv",
+    "llvm.mips.insve.b" => "__builtin_msa_insve_b",
+    "llvm.mips.insve.d" => "__builtin_msa_insve_d",
+    "llvm.mips.insve.h" => "__builtin_msa_insve_h",
+    "llvm.mips.insve.w" => "__builtin_msa_insve_w",
+    "llvm.mips.lbux" => "__builtin_mips_lbux",
+    "llvm.mips.ld.b" => "__builtin_msa_ld_b",
+    "llvm.mips.ld.d" => "__builtin_msa_ld_d",
+    "llvm.mips.ld.h" => "__builtin_msa_ld_h",
+    "llvm.mips.ld.w" => "__builtin_msa_ld_w",
+    "llvm.mips.ldi.b" => "__builtin_msa_ldi_b",
+    "llvm.mips.ldi.d" => "__builtin_msa_ldi_d",
+    "llvm.mips.ldi.h" => "__builtin_msa_ldi_h",
+    "llvm.mips.ldi.w" => "__builtin_msa_ldi_w",
+    "llvm.mips.ldr.d" => "__builtin_msa_ldr_d",
+    "llvm.mips.ldr.w" => "__builtin_msa_ldr_w",
+    "llvm.mips.lhx" => "__builtin_mips_lhx",
+    "llvm.mips.lsa" => "__builtin_mips_lsa",
+    "llvm.mips.lwx" => "__builtin_mips_lwx",
+    "llvm.mips.madd" => "__builtin_mips_madd",
+    "llvm.mips.madd.q.h" => "__builtin_msa_madd_q_h",
+    "llvm.mips.madd.q.w" => "__builtin_msa_madd_q_w",
+    "llvm.mips.maddr.q.h" => "__builtin_msa_maddr_q_h",
+    "llvm.mips.maddr.q.w" => "__builtin_msa_maddr_q_w",
+    "llvm.mips.maddu" => "__builtin_mips_maddu",
+    "llvm.mips.maddv.b" => "__builtin_msa_maddv_b",
+    "llvm.mips.maddv.d" => "__builtin_msa_maddv_d",
+    "llvm.mips.maddv.h" => "__builtin_msa_maddv_h",
+    "llvm.mips.maddv.w" => "__builtin_msa_maddv_w",
+    "llvm.mips.maq.s.w.phl" => "__builtin_mips_maq_s_w_phl",
+    "llvm.mips.maq.s.w.phr" => "__builtin_mips_maq_s_w_phr",
+    "llvm.mips.maq.sa.w.phl" => "__builtin_mips_maq_sa_w_phl",
+    "llvm.mips.maq.sa.w.phr" => "__builtin_mips_maq_sa_w_phr",
+    "llvm.mips.max.a.b" => "__builtin_msa_max_a_b",
+    "llvm.mips.max.a.d" => "__builtin_msa_max_a_d",
+    "llvm.mips.max.a.h" => "__builtin_msa_max_a_h",
+    "llvm.mips.max.a.w" => "__builtin_msa_max_a_w",
+    "llvm.mips.max.s.b" => "__builtin_msa_max_s_b",
+    "llvm.mips.max.s.d" => "__builtin_msa_max_s_d",
+    "llvm.mips.max.s.h" => "__builtin_msa_max_s_h",
+    "llvm.mips.max.s.w" => "__builtin_msa_max_s_w",
+    "llvm.mips.max.u.b" => "__builtin_msa_max_u_b",
+    "llvm.mips.max.u.d" => "__builtin_msa_max_u_d",
+    "llvm.mips.max.u.h" => "__builtin_msa_max_u_h",
+    "llvm.mips.max.u.w" => "__builtin_msa_max_u_w",
+    "llvm.mips.maxi.s.b" => "__builtin_msa_maxi_s_b",
+    "llvm.mips.maxi.s.d" => "__builtin_msa_maxi_s_d",
+    "llvm.mips.maxi.s.h" => "__builtin_msa_maxi_s_h",
+    "llvm.mips.maxi.s.w" => "__builtin_msa_maxi_s_w",
+    "llvm.mips.maxi.u.b" => "__builtin_msa_maxi_u_b",
+    "llvm.mips.maxi.u.d" => "__builtin_msa_maxi_u_d",
+    "llvm.mips.maxi.u.h" => "__builtin_msa_maxi_u_h",
+    "llvm.mips.maxi.u.w" => "__builtin_msa_maxi_u_w",
+    "llvm.mips.min.a.b" => "__builtin_msa_min_a_b",
+    "llvm.mips.min.a.d" => "__builtin_msa_min_a_d",
+    "llvm.mips.min.a.h" => "__builtin_msa_min_a_h",
+    "llvm.mips.min.a.w" => "__builtin_msa_min_a_w",
+    "llvm.mips.min.s.b" => "__builtin_msa_min_s_b",
+    "llvm.mips.min.s.d" => "__builtin_msa_min_s_d",
+    "llvm.mips.min.s.h" => "__builtin_msa_min_s_h",
+    "llvm.mips.min.s.w" => "__builtin_msa_min_s_w",
+    "llvm.mips.min.u.b" => "__builtin_msa_min_u_b",
+    "llvm.mips.min.u.d" => "__builtin_msa_min_u_d",
+    "llvm.mips.min.u.h" => "__builtin_msa_min_u_h",
+    "llvm.mips.min.u.w" => "__builtin_msa_min_u_w",
+    "llvm.mips.mini.s.b" => "__builtin_msa_mini_s_b",
+    "llvm.mips.mini.s.d" => "__builtin_msa_mini_s_d",
+    "llvm.mips.mini.s.h" => "__builtin_msa_mini_s_h",
+    "llvm.mips.mini.s.w" => "__builtin_msa_mini_s_w",
+    "llvm.mips.mini.u.b" => "__builtin_msa_mini_u_b",
+    "llvm.mips.mini.u.d" => "__builtin_msa_mini_u_d",
+    "llvm.mips.mini.u.h" => "__builtin_msa_mini_u_h",
+    "llvm.mips.mini.u.w" => "__builtin_msa_mini_u_w",
+    "llvm.mips.mod.s.b" => "__builtin_msa_mod_s_b",
+    "llvm.mips.mod.s.d" => "__builtin_msa_mod_s_d",
+    "llvm.mips.mod.s.h" => "__builtin_msa_mod_s_h",
+    "llvm.mips.mod.s.w" => "__builtin_msa_mod_s_w",
+    "llvm.mips.mod.u.b" => "__builtin_msa_mod_u_b",
+    "llvm.mips.mod.u.d" => "__builtin_msa_mod_u_d",
+    "llvm.mips.mod.u.h" => "__builtin_msa_mod_u_h",
+    "llvm.mips.mod.u.w" => "__builtin_msa_mod_u_w",
+    "llvm.mips.modsub" => "__builtin_mips_modsub",
+    "llvm.mips.move.v" => "__builtin_msa_move_v",
+    "llvm.mips.msub" => "__builtin_mips_msub",
+    "llvm.mips.msub.q.h" => "__builtin_msa_msub_q_h",
+    "llvm.mips.msub.q.w" => "__builtin_msa_msub_q_w",
+    "llvm.mips.msubr.q.h" => "__builtin_msa_msubr_q_h",
+    "llvm.mips.msubr.q.w" => "__builtin_msa_msubr_q_w",
+    "llvm.mips.msubu" => "__builtin_mips_msubu",
+    "llvm.mips.msubv.b" => "__builtin_msa_msubv_b",
+    "llvm.mips.msubv.d" => "__builtin_msa_msubv_d",
+    "llvm.mips.msubv.h" => "__builtin_msa_msubv_h",
+    "llvm.mips.msubv.w" => "__builtin_msa_msubv_w",
+    "llvm.mips.mthlip" => "__builtin_mips_mthlip",
+    "llvm.mips.mul.ph" => "__builtin_mips_mul_ph",
+    "llvm.mips.mul.q.h" => "__builtin_msa_mul_q_h",
+    "llvm.mips.mul.q.w" => "__builtin_msa_mul_q_w",
+    "llvm.mips.mul.s.ph" => "__builtin_mips_mul_s_ph",
+    "llvm.mips.muleq.s.w.phl" => "__builtin_mips_muleq_s_w_phl",
+    "llvm.mips.muleq.s.w.phr" => "__builtin_mips_muleq_s_w_phr",
+    "llvm.mips.muleu.s.ph.qbl" => "__builtin_mips_muleu_s_ph_qbl",
+    "llvm.mips.muleu.s.ph.qbr" => "__builtin_mips_muleu_s_ph_qbr",
+    "llvm.mips.mulq.rs.ph" => "__builtin_mips_mulq_rs_ph",
+    "llvm.mips.mulq.rs.w" => "__builtin_mips_mulq_rs_w",
+    "llvm.mips.mulq.s.ph" => "__builtin_mips_mulq_s_ph",
+    "llvm.mips.mulq.s.w" => "__builtin_mips_mulq_s_w",
+    "llvm.mips.mulr.q.h" => "__builtin_msa_mulr_q_h",
+    "llvm.mips.mulr.q.w" => "__builtin_msa_mulr_q_w",
+    "llvm.mips.mulsa.w.ph" => "__builtin_mips_mulsa_w_ph",
+    "llvm.mips.mulsaq.s.w.ph" => "__builtin_mips_mulsaq_s_w_ph",
+    "llvm.mips.mult" => "__builtin_mips_mult",
+    "llvm.mips.multu" => "__builtin_mips_multu",
+    "llvm.mips.mulv.b" => "__builtin_msa_mulv_b",
+    "llvm.mips.mulv.d" => "__builtin_msa_mulv_d",
+    "llvm.mips.mulv.h" => "__builtin_msa_mulv_h",
+    "llvm.mips.mulv.w" => "__builtin_msa_mulv_w",
+    "llvm.mips.nloc.b" => "__builtin_msa_nloc_b",
+    "llvm.mips.nloc.d" => "__builtin_msa_nloc_d",
+    "llvm.mips.nloc.h" => "__builtin_msa_nloc_h",
+    "llvm.mips.nloc.w" => "__builtin_msa_nloc_w",
+    "llvm.mips.nlzc.b" => "__builtin_msa_nlzc_b",
+    "llvm.mips.nlzc.d" => "__builtin_msa_nlzc_d",
+    "llvm.mips.nlzc.h" => "__builtin_msa_nlzc_h",
+    "llvm.mips.nlzc.w" => "__builtin_msa_nlzc_w",
+    "llvm.mips.nor.v" => "__builtin_msa_nor_v",
+    "llvm.mips.nori.b" => "__builtin_msa_nori_b",
+    "llvm.mips.or.v" => "__builtin_msa_or_v",
+    "llvm.mips.ori.b" => "__builtin_msa_ori_b",
+    "llvm.mips.packrl.ph" => "__builtin_mips_packrl_ph",
+    "llvm.mips.pckev.b" => "__builtin_msa_pckev_b",
+    "llvm.mips.pckev.d" => "__builtin_msa_pckev_d",
+    "llvm.mips.pckev.h" => "__builtin_msa_pckev_h",
+    "llvm.mips.pckev.w" => "__builtin_msa_pckev_w",
+    "llvm.mips.pckod.b" => "__builtin_msa_pckod_b",
+    "llvm.mips.pckod.d" => "__builtin_msa_pckod_d",
+    "llvm.mips.pckod.h" => "__builtin_msa_pckod_h",
+    "llvm.mips.pckod.w" => "__builtin_msa_pckod_w",
+    "llvm.mips.pcnt.b" => "__builtin_msa_pcnt_b",
+    "llvm.mips.pcnt.d" => "__builtin_msa_pcnt_d",
+    "llvm.mips.pcnt.h" => "__builtin_msa_pcnt_h",
+    "llvm.mips.pcnt.w" => "__builtin_msa_pcnt_w",
+    "llvm.mips.pick.ph" => "__builtin_mips_pick_ph",
+    "llvm.mips.pick.qb" => "__builtin_mips_pick_qb",
+    "llvm.mips.preceq.w.phl" => "__builtin_mips_preceq_w_phl",
+    "llvm.mips.preceq.w.phr" => "__builtin_mips_preceq_w_phr",
+    "llvm.mips.precequ.ph.qbl" => "__builtin_mips_precequ_ph_qbl",
+    "llvm.mips.precequ.ph.qbla" => "__builtin_mips_precequ_ph_qbla",
+    "llvm.mips.precequ.ph.qbr" => "__builtin_mips_precequ_ph_qbr",
+    "llvm.mips.precequ.ph.qbra" => "__builtin_mips_precequ_ph_qbra",
+    "llvm.mips.preceu.ph.qbl" => "__builtin_mips_preceu_ph_qbl",
+    "llvm.mips.preceu.ph.qbla" => "__builtin_mips_preceu_ph_qbla",
+    "llvm.mips.preceu.ph.qbr" => "__builtin_mips_preceu_ph_qbr",
+    "llvm.mips.preceu.ph.qbra" => "__builtin_mips_preceu_ph_qbra",
+    "llvm.mips.precr.qb.ph" => "__builtin_mips_precr_qb_ph",
+    "llvm.mips.precr.sra.ph.w" => "__builtin_mips_precr_sra_ph_w",
+    "llvm.mips.precr.sra.r.ph.w" => "__builtin_mips_precr_sra_r_ph_w",
+    "llvm.mips.precrq.ph.w" => "__builtin_mips_precrq_ph_w",
+    "llvm.mips.precrq.qb.ph" => "__builtin_mips_precrq_qb_ph",
+    "llvm.mips.precrq.rs.ph.w" => "__builtin_mips_precrq_rs_ph_w",
+    "llvm.mips.precrqu.s.qb.ph" => "__builtin_mips_precrqu_s_qb_ph",
+    "llvm.mips.prepend" => "__builtin_mips_prepend",
+    "llvm.mips.raddu.w.qb" => "__builtin_mips_raddu_w_qb",
+    "llvm.mips.rddsp" => "__builtin_mips_rddsp",
+    "llvm.mips.repl.ph" => "__builtin_mips_repl_ph",
+    "llvm.mips.repl.qb" => "__builtin_mips_repl_qb",
+    "llvm.mips.sat.s.b" => "__builtin_msa_sat_s_b",
+    "llvm.mips.sat.s.d" => "__builtin_msa_sat_s_d",
+    "llvm.mips.sat.s.h" => "__builtin_msa_sat_s_h",
+    "llvm.mips.sat.s.w" => "__builtin_msa_sat_s_w",
+    "llvm.mips.sat.u.b" => "__builtin_msa_sat_u_b",
+    "llvm.mips.sat.u.d" => "__builtin_msa_sat_u_d",
+    "llvm.mips.sat.u.h" => "__builtin_msa_sat_u_h",
+    "llvm.mips.sat.u.w" => "__builtin_msa_sat_u_w",
+    "llvm.mips.shf.b" => "__builtin_msa_shf_b",
+    "llvm.mips.shf.h" => "__builtin_msa_shf_h",
+    "llvm.mips.shf.w" => "__builtin_msa_shf_w",
+    "llvm.mips.shilo" => "__builtin_mips_shilo",
+    "llvm.mips.shll.ph" => "__builtin_mips_shll_ph",
+    "llvm.mips.shll.qb" => "__builtin_mips_shll_qb",
+    "llvm.mips.shll.s.ph" => "__builtin_mips_shll_s_ph",
+    "llvm.mips.shll.s.w" => "__builtin_mips_shll_s_w",
+    "llvm.mips.shra.ph" => "__builtin_mips_shra_ph",
+    "llvm.mips.shra.qb" => "__builtin_mips_shra_qb",
+    "llvm.mips.shra.r.ph" => "__builtin_mips_shra_r_ph",
+    "llvm.mips.shra.r.qb" => "__builtin_mips_shra_r_qb",
+    "llvm.mips.shra.r.w" => "__builtin_mips_shra_r_w",
+    "llvm.mips.shrl.ph" => "__builtin_mips_shrl_ph",
+    "llvm.mips.shrl.qb" => "__builtin_mips_shrl_qb",
+    "llvm.mips.sld.b" => "__builtin_msa_sld_b",
+    "llvm.mips.sld.d" => "__builtin_msa_sld_d",
+    "llvm.mips.sld.h" => "__builtin_msa_sld_h",
+    "llvm.mips.sld.w" => "__builtin_msa_sld_w",
+    "llvm.mips.sldi.b" => "__builtin_msa_sldi_b",
+    "llvm.mips.sldi.d" => "__builtin_msa_sldi_d",
+    "llvm.mips.sldi.h" => "__builtin_msa_sldi_h",
+    "llvm.mips.sldi.w" => "__builtin_msa_sldi_w",
+    "llvm.mips.sll.b" => "__builtin_msa_sll_b",
+    "llvm.mips.sll.d" => "__builtin_msa_sll_d",
+    "llvm.mips.sll.h" => "__builtin_msa_sll_h",
+    "llvm.mips.sll.w" => "__builtin_msa_sll_w",
+    "llvm.mips.slli.b" => "__builtin_msa_slli_b",
+    "llvm.mips.slli.d" => "__builtin_msa_slli_d",
+    "llvm.mips.slli.h" => "__builtin_msa_slli_h",
+    "llvm.mips.slli.w" => "__builtin_msa_slli_w",
+    "llvm.mips.splat.b" => "__builtin_msa_splat_b",
+    "llvm.mips.splat.d" => "__builtin_msa_splat_d",
+    "llvm.mips.splat.h" => "__builtin_msa_splat_h",
+    "llvm.mips.splat.w" => "__builtin_msa_splat_w",
+    "llvm.mips.splati.b" => "__builtin_msa_splati_b",
+    "llvm.mips.splati.d" => "__builtin_msa_splati_d",
+    "llvm.mips.splati.h" => "__builtin_msa_splati_h",
+    "llvm.mips.splati.w" => "__builtin_msa_splati_w",
+    "llvm.mips.sra.b" => "__builtin_msa_sra_b",
+    "llvm.mips.sra.d" => "__builtin_msa_sra_d",
+    "llvm.mips.sra.h" => "__builtin_msa_sra_h",
+    "llvm.mips.sra.w" => "__builtin_msa_sra_w",
+    "llvm.mips.srai.b" => "__builtin_msa_srai_b",
+    "llvm.mips.srai.d" => "__builtin_msa_srai_d",
+    "llvm.mips.srai.h" => "__builtin_msa_srai_h",
+    "llvm.mips.srai.w" => "__builtin_msa_srai_w",
+    "llvm.mips.srar.b" => "__builtin_msa_srar_b",
+    "llvm.mips.srar.d" => "__builtin_msa_srar_d",
+    "llvm.mips.srar.h" => "__builtin_msa_srar_h",
+    "llvm.mips.srar.w" => "__builtin_msa_srar_w",
+    "llvm.mips.srari.b" => "__builtin_msa_srari_b",
+    "llvm.mips.srari.d" => "__builtin_msa_srari_d",
+    "llvm.mips.srari.h" => "__builtin_msa_srari_h",
+    "llvm.mips.srari.w" => "__builtin_msa_srari_w",
+    "llvm.mips.srl.b" => "__builtin_msa_srl_b",
+    "llvm.mips.srl.d" => "__builtin_msa_srl_d",
+    "llvm.mips.srl.h" => "__builtin_msa_srl_h",
+    "llvm.mips.srl.w" => "__builtin_msa_srl_w",
+    "llvm.mips.srli.b" => "__builtin_msa_srli_b",
+    "llvm.mips.srli.d" => "__builtin_msa_srli_d",
+    "llvm.mips.srli.h" => "__builtin_msa_srli_h",
+    "llvm.mips.srli.w" => "__builtin_msa_srli_w",
+    "llvm.mips.srlr.b" => "__builtin_msa_srlr_b",
+    "llvm.mips.srlr.d" => "__builtin_msa_srlr_d",
+    "llvm.mips.srlr.h" => "__builtin_msa_srlr_h",
+    "llvm.mips.srlr.w" => "__builtin_msa_srlr_w",
+    "llvm.mips.srlri.b" => "__builtin_msa_srlri_b",
+    "llvm.mips.srlri.d" => "__builtin_msa_srlri_d",
+    "llvm.mips.srlri.h" => "__builtin_msa_srlri_h",
+    "llvm.mips.srlri.w" => "__builtin_msa_srlri_w",
+    "llvm.mips.st.b" => "__builtin_msa_st_b",
+    "llvm.mips.st.d" => "__builtin_msa_st_d",
+    "llvm.mips.st.h" => "__builtin_msa_st_h",
+    "llvm.mips.st.w" => "__builtin_msa_st_w",
+    "llvm.mips.str.d" => "__builtin_msa_str_d",
+    "llvm.mips.str.w" => "__builtin_msa_str_w",
+    "llvm.mips.subq.ph" => "__builtin_mips_subq_ph",
+    "llvm.mips.subq.s.ph" => "__builtin_mips_subq_s_ph",
+    "llvm.mips.subq.s.w" => "__builtin_mips_subq_s_w",
+    "llvm.mips.subqh.ph" => "__builtin_mips_subqh_ph",
+    "llvm.mips.subqh.r.ph" => "__builtin_mips_subqh_r_ph",
+    "llvm.mips.subqh.r.w" => "__builtin_mips_subqh_r_w",
+    "llvm.mips.subqh.w" => "__builtin_mips_subqh_w",
+    "llvm.mips.subs.s.b" => "__builtin_msa_subs_s_b",
+    "llvm.mips.subs.s.d" => "__builtin_msa_subs_s_d",
+    "llvm.mips.subs.s.h" => "__builtin_msa_subs_s_h",
+    "llvm.mips.subs.s.w" => "__builtin_msa_subs_s_w",
+    "llvm.mips.subs.u.b" => "__builtin_msa_subs_u_b",
+    "llvm.mips.subs.u.d" => "__builtin_msa_subs_u_d",
+    "llvm.mips.subs.u.h" => "__builtin_msa_subs_u_h",
+    "llvm.mips.subs.u.w" => "__builtin_msa_subs_u_w",
+    "llvm.mips.subsus.u.b" => "__builtin_msa_subsus_u_b",
+    "llvm.mips.subsus.u.d" => "__builtin_msa_subsus_u_d",
+    "llvm.mips.subsus.u.h" => "__builtin_msa_subsus_u_h",
+    "llvm.mips.subsus.u.w" => "__builtin_msa_subsus_u_w",
+    "llvm.mips.subsuu.s.b" => "__builtin_msa_subsuu_s_b",
+    "llvm.mips.subsuu.s.d" => "__builtin_msa_subsuu_s_d",
+    "llvm.mips.subsuu.s.h" => "__builtin_msa_subsuu_s_h",
+    "llvm.mips.subsuu.s.w" => "__builtin_msa_subsuu_s_w",
+    "llvm.mips.subu.ph" => "__builtin_mips_subu_ph",
+    "llvm.mips.subu.qb" => "__builtin_mips_subu_qb",
+    "llvm.mips.subu.s.ph" => "__builtin_mips_subu_s_ph",
+    "llvm.mips.subu.s.qb" => "__builtin_mips_subu_s_qb",
+    "llvm.mips.subuh.qb" => "__builtin_mips_subuh_qb",
+    "llvm.mips.subuh.r.qb" => "__builtin_mips_subuh_r_qb",
+    "llvm.mips.subv.b" => "__builtin_msa_subv_b",
+    "llvm.mips.subv.d" => "__builtin_msa_subv_d",
+    "llvm.mips.subv.h" => "__builtin_msa_subv_h",
+    "llvm.mips.subv.w" => "__builtin_msa_subv_w",
+    "llvm.mips.subvi.b" => "__builtin_msa_subvi_b",
+    "llvm.mips.subvi.d" => "__builtin_msa_subvi_d",
+    "llvm.mips.subvi.h" => "__builtin_msa_subvi_h",
+    "llvm.mips.subvi.w" => "__builtin_msa_subvi_w",
+    "llvm.mips.vshf.b" => "__builtin_msa_vshf_b",
+    "llvm.mips.vshf.d" => "__builtin_msa_vshf_d",
+    "llvm.mips.vshf.h" => "__builtin_msa_vshf_h",
+    "llvm.mips.vshf.w" => "__builtin_msa_vshf_w",
+    "llvm.mips.wrdsp" => "__builtin_mips_wrdsp",
+    "llvm.mips.xor.v" => "__builtin_msa_xor_v",
+    "llvm.mips.xori.b" => "__builtin_msa_xori_b",
+    // nvvm
+    "llvm.nvvm.abs.i" => "__nvvm_abs_i",
+    "llvm.nvvm.abs.ll" => "__nvvm_abs_ll",
+    "llvm.nvvm.add.rm.d" => "__nvvm_add_rm_d",
+    "llvm.nvvm.add.rm.f" => "__nvvm_add_rm_f",
+    "llvm.nvvm.add.rm.ftz.f" => "__nvvm_add_rm_ftz_f",
+    "llvm.nvvm.add.rn.d" => "__nvvm_add_rn_d",
+    "llvm.nvvm.add.rn.f" => "__nvvm_add_rn_f",
+    "llvm.nvvm.add.rn.ftz.f" => "__nvvm_add_rn_ftz_f",
+    "llvm.nvvm.add.rp.d" => "__nvvm_add_rp_d",
+    "llvm.nvvm.add.rp.f" => "__nvvm_add_rp_f",
+    "llvm.nvvm.add.rp.ftz.f" => "__nvvm_add_rp_ftz_f",
+    "llvm.nvvm.add.rz.d" => "__nvvm_add_rz_d",
+    "llvm.nvvm.add.rz.f" => "__nvvm_add_rz_f",
+    "llvm.nvvm.add.rz.ftz.f" => "__nvvm_add_rz_ftz_f",
+    "llvm.nvvm.bar.sync" => "__nvvm_bar_sync",
+    "llvm.nvvm.barrier0" => "__nvvm_bar0",
+    // [DUPLICATE]: "llvm.nvvm.barrier0" => "__syncthreads",
+    "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and",
+    "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or",
+    "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc",
+    "llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll",
+    "llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i",
+    "llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f",
+    "llvm.nvvm.bitcast.ll2d" => "__nvvm_bitcast_ll2d",
+    "llvm.nvvm.brev32" => "__nvvm_brev32",
+    "llvm.nvvm.brev64" => "__nvvm_brev64",
+    "llvm.nvvm.ceil.d" => "__nvvm_ceil_d",
+    "llvm.nvvm.ceil.f" => "__nvvm_ceil_f",
+    "llvm.nvvm.ceil.ftz.f" => "__nvvm_ceil_ftz_f",
+    "llvm.nvvm.clz.i" => "__nvvm_clz_i",
+    "llvm.nvvm.clz.ll" => "__nvvm_clz_ll",
+    "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f",
+    "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f",
+    "llvm.nvvm.d2f.rm" => "__nvvm_d2f_rm",
+    "llvm.nvvm.d2f.rm.ftz" => "__nvvm_d2f_rm_ftz",
+    "llvm.nvvm.d2f.rn" => "__nvvm_d2f_rn",
+    "llvm.nvvm.d2f.rn.ftz" => "__nvvm_d2f_rn_ftz",
+    "llvm.nvvm.d2f.rp" => "__nvvm_d2f_rp",
+    "llvm.nvvm.d2f.rp.ftz" => "__nvvm_d2f_rp_ftz",
+    "llvm.nvvm.d2f.rz" => "__nvvm_d2f_rz",
+    "llvm.nvvm.d2f.rz.ftz" => "__nvvm_d2f_rz_ftz",
+    "llvm.nvvm.d2i.hi" => "__nvvm_d2i_hi",
+    "llvm.nvvm.d2i.lo" => "__nvvm_d2i_lo",
+    "llvm.nvvm.d2i.rm" => "__nvvm_d2i_rm",
+    "llvm.nvvm.d2i.rn" => "__nvvm_d2i_rn",
+    "llvm.nvvm.d2i.rp" => "__nvvm_d2i_rp",
+    "llvm.nvvm.d2i.rz" => "__nvvm_d2i_rz",
+    "llvm.nvvm.d2ll.rm" => "__nvvm_d2ll_rm",
+    "llvm.nvvm.d2ll.rn" => "__nvvm_d2ll_rn",
+    "llvm.nvvm.d2ll.rp" => "__nvvm_d2ll_rp",
+    "llvm.nvvm.d2ll.rz" => "__nvvm_d2ll_rz",
+    "llvm.nvvm.d2ui.rm" => "__nvvm_d2ui_rm",
+    "llvm.nvvm.d2ui.rn" => "__nvvm_d2ui_rn",
+    "llvm.nvvm.d2ui.rp" => "__nvvm_d2ui_rp",
+    "llvm.nvvm.d2ui.rz" => "__nvvm_d2ui_rz",
+    "llvm.nvvm.d2ull.rm" => "__nvvm_d2ull_rm",
+    "llvm.nvvm.d2ull.rn" => "__nvvm_d2ull_rn",
+    "llvm.nvvm.d2ull.rp" => "__nvvm_d2ull_rp",
+    "llvm.nvvm.d2ull.rz" => "__nvvm_d2ull_rz",
+    "llvm.nvvm.div.approx.f" => "__nvvm_div_approx_f",
+    "llvm.nvvm.div.approx.ftz.f" => "__nvvm_div_approx_ftz_f",
+    "llvm.nvvm.div.rm.d" => "__nvvm_div_rm_d",
+    "llvm.nvvm.div.rm.f" => "__nvvm_div_rm_f",
+    "llvm.nvvm.div.rm.ftz.f" => "__nvvm_div_rm_ftz_f",
+    "llvm.nvvm.div.rn.d" => "__nvvm_div_rn_d",
+    "llvm.nvvm.div.rn.f" => "__nvvm_div_rn_f",
+    "llvm.nvvm.div.rn.ftz.f" => "__nvvm_div_rn_ftz_f",
+    "llvm.nvvm.div.rp.d" => "__nvvm_div_rp_d",
+    "llvm.nvvm.div.rp.f" => "__nvvm_div_rp_f",
+    "llvm.nvvm.div.rp.ftz.f" => "__nvvm_div_rp_ftz_f",
+    "llvm.nvvm.div.rz.d" => "__nvvm_div_rz_d",
+    "llvm.nvvm.div.rz.f" => "__nvvm_div_rz_f",
+    "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f",
+    "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d",
+    "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f",
+    "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f",
+    "llvm.nvvm.f2h.rn" => "__nvvm_f2h_rn",
+    "llvm.nvvm.f2h.rn.ftz" => "__nvvm_f2h_rn_ftz",
+    "llvm.nvvm.f2i.rm" => "__nvvm_f2i_rm",
+    "llvm.nvvm.f2i.rm.ftz" => "__nvvm_f2i_rm_ftz",
+    "llvm.nvvm.f2i.rn" => "__nvvm_f2i_rn",
+    "llvm.nvvm.f2i.rn.ftz" => "__nvvm_f2i_rn_ftz",
+    "llvm.nvvm.f2i.rp" => "__nvvm_f2i_rp",
+    "llvm.nvvm.f2i.rp.ftz" => "__nvvm_f2i_rp_ftz",
+    "llvm.nvvm.f2i.rz" => "__nvvm_f2i_rz",
+    "llvm.nvvm.f2i.rz.ftz" => "__nvvm_f2i_rz_ftz",
+    "llvm.nvvm.f2ll.rm" => "__nvvm_f2ll_rm",
+    "llvm.nvvm.f2ll.rm.ftz" => "__nvvm_f2ll_rm_ftz",
+    "llvm.nvvm.f2ll.rn" => "__nvvm_f2ll_rn",
+    "llvm.nvvm.f2ll.rn.ftz" => "__nvvm_f2ll_rn_ftz",
+    "llvm.nvvm.f2ll.rp" => "__nvvm_f2ll_rp",
+    "llvm.nvvm.f2ll.rp.ftz" => "__nvvm_f2ll_rp_ftz",
+    "llvm.nvvm.f2ll.rz" => "__nvvm_f2ll_rz",
+    "llvm.nvvm.f2ll.rz.ftz" => "__nvvm_f2ll_rz_ftz",
+    "llvm.nvvm.f2ui.rm" => "__nvvm_f2ui_rm",
+    "llvm.nvvm.f2ui.rm.ftz" => "__nvvm_f2ui_rm_ftz",
+    "llvm.nvvm.f2ui.rn" => "__nvvm_f2ui_rn",
+    "llvm.nvvm.f2ui.rn.ftz" => "__nvvm_f2ui_rn_ftz",
+    "llvm.nvvm.f2ui.rp" => "__nvvm_f2ui_rp",
+    "llvm.nvvm.f2ui.rp.ftz" => "__nvvm_f2ui_rp_ftz",
+    "llvm.nvvm.f2ui.rz" => "__nvvm_f2ui_rz",
+    "llvm.nvvm.f2ui.rz.ftz" => "__nvvm_f2ui_rz_ftz",
+    "llvm.nvvm.f2ull.rm" => "__nvvm_f2ull_rm",
+    "llvm.nvvm.f2ull.rm.ftz" => "__nvvm_f2ull_rm_ftz",
+    "llvm.nvvm.f2ull.rn" => "__nvvm_f2ull_rn",
+    "llvm.nvvm.f2ull.rn.ftz" => "__nvvm_f2ull_rn_ftz",
+    "llvm.nvvm.f2ull.rp" => "__nvvm_f2ull_rp",
+    "llvm.nvvm.f2ull.rp.ftz" => "__nvvm_f2ull_rp_ftz",
+    "llvm.nvvm.f2ull.rz" => "__nvvm_f2ull_rz",
+    "llvm.nvvm.f2ull.rz.ftz" => "__nvvm_f2ull_rz_ftz",
+    "llvm.nvvm.fabs.d" => "__nvvm_fabs_d",
+    "llvm.nvvm.fabs.f" => "__nvvm_fabs_f",
+    "llvm.nvvm.fabs.ftz.f" => "__nvvm_fabs_ftz_f",
+    "llvm.nvvm.floor.d" => "__nvvm_floor_d",
+    "llvm.nvvm.floor.f" => "__nvvm_floor_f",
+    "llvm.nvvm.floor.ftz.f" => "__nvvm_floor_ftz_f",
+    "llvm.nvvm.fma.rm.d" => "__nvvm_fma_rm_d",
+    "llvm.nvvm.fma.rm.f" => "__nvvm_fma_rm_f",
+    "llvm.nvvm.fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f",
+    "llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d",
+    "llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f",
+    "llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f",
+    "llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d",
+    "llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f",
+    "llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f",
+    "llvm.nvvm.fma.rz.d" => "__nvvm_fma_rz_d",
+    "llvm.nvvm.fma.rz.f" => "__nvvm_fma_rz_f",
+    "llvm.nvvm.fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f",
+    "llvm.nvvm.fmax.d" => "__nvvm_fmax_d",
+    "llvm.nvvm.fmax.f" => "__nvvm_fmax_f",
+    "llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f",
+    "llvm.nvvm.fmin.d" => "__nvvm_fmin_d",
+    "llvm.nvvm.fmin.f" => "__nvvm_fmin_f",
+    "llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f",
+    "llvm.nvvm.h2f" => "__nvvm_h2f",
+    "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm",
+    "llvm.nvvm.i2d.rn" => "__nvvm_i2d_rn",
+    "llvm.nvvm.i2d.rp" => "__nvvm_i2d_rp",
+    "llvm.nvvm.i2d.rz" => "__nvvm_i2d_rz",
+    "llvm.nvvm.i2f.rm" => "__nvvm_i2f_rm",
+    "llvm.nvvm.i2f.rn" => "__nvvm_i2f_rn",
+    "llvm.nvvm.i2f.rp" => "__nvvm_i2f_rp",
+    "llvm.nvvm.i2f.rz" => "__nvvm_i2f_rz",
+    "llvm.nvvm.isspacep.const" => "__nvvm_isspacep_const",
+    "llvm.nvvm.isspacep.global" => "__nvvm_isspacep_global",
+    "llvm.nvvm.isspacep.local" => "__nvvm_isspacep_local",
+    "llvm.nvvm.isspacep.shared" => "__nvvm_isspacep_shared",
+    "llvm.nvvm.istypep.sampler" => "__nvvm_istypep_sampler",
+    "llvm.nvvm.istypep.surface" => "__nvvm_istypep_surface",
+    "llvm.nvvm.istypep.texture" => "__nvvm_istypep_texture",
+    "llvm.nvvm.lg2.approx.d" => "__nvvm_lg2_approx_d",
+    "llvm.nvvm.lg2.approx.f" => "__nvvm_lg2_approx_f",
+    "llvm.nvvm.lg2.approx.ftz.f" => "__nvvm_lg2_approx_ftz_f",
+    "llvm.nvvm.ll2d.rm" => "__nvvm_ll2d_rm",
+    "llvm.nvvm.ll2d.rn" => "__nvvm_ll2d_rn",
+    "llvm.nvvm.ll2d.rp" => "__nvvm_ll2d_rp",
+    "llvm.nvvm.ll2d.rz" => "__nvvm_ll2d_rz",
+    "llvm.nvvm.ll2f.rm" => "__nvvm_ll2f_rm",
+    "llvm.nvvm.ll2f.rn" => "__nvvm_ll2f_rn",
+    "llvm.nvvm.ll2f.rp" => "__nvvm_ll2f_rp",
+    "llvm.nvvm.ll2f.rz" => "__nvvm_ll2f_rz",
+    "llvm.nvvm.lohi.i2d" => "__nvvm_lohi_i2d",
+    "llvm.nvvm.max.i" => "__nvvm_max_i",
+    "llvm.nvvm.max.ll" => "__nvvm_max_ll",
+    "llvm.nvvm.max.ui" => "__nvvm_max_ui",
+    "llvm.nvvm.max.ull" => "__nvvm_max_ull",
+    "llvm.nvvm.membar.cta" => "__nvvm_membar_cta",
+    "llvm.nvvm.membar.gl" => "__nvvm_membar_gl",
+    "llvm.nvvm.membar.sys" => "__nvvm_membar_sys",
+    "llvm.nvvm.min.i" => "__nvvm_min_i",
+    "llvm.nvvm.min.ll" => "__nvvm_min_ll",
+    "llvm.nvvm.min.ui" => "__nvvm_min_ui",
+    "llvm.nvvm.min.ull" => "__nvvm_min_ull",
+    "llvm.nvvm.mul.rm.d" => "__nvvm_mul_rm_d",
+    "llvm.nvvm.mul.rm.f" => "__nvvm_mul_rm_f",
+    "llvm.nvvm.mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f",
+    "llvm.nvvm.mul.rn.d" => "__nvvm_mul_rn_d",
+    "llvm.nvvm.mul.rn.f" => "__nvvm_mul_rn_f",
+    "llvm.nvvm.mul.rn.ftz.f" => "__nvvm_mul_rn_ftz_f",
+    "llvm.nvvm.mul.rp.d" => "__nvvm_mul_rp_d",
+    "llvm.nvvm.mul.rp.f" => "__nvvm_mul_rp_f",
+    "llvm.nvvm.mul.rp.ftz.f" => "__nvvm_mul_rp_ftz_f",
+    "llvm.nvvm.mul.rz.d" => "__nvvm_mul_rz_d",
+    "llvm.nvvm.mul.rz.f" => "__nvvm_mul_rz_f",
+    "llvm.nvvm.mul.rz.ftz.f" => "__nvvm_mul_rz_ftz_f",
+    "llvm.nvvm.mul24.i" => "__nvvm_mul24_i",
+    "llvm.nvvm.mul24.ui" => "__nvvm_mul24_ui",
+    "llvm.nvvm.mulhi.i" => "__nvvm_mulhi_i",
+    "llvm.nvvm.mulhi.ll" => "__nvvm_mulhi_ll",
+    "llvm.nvvm.mulhi.ui" => "__nvvm_mulhi_ui",
+    "llvm.nvvm.mulhi.ull" => "__nvvm_mulhi_ull",
+    "llvm.nvvm.popc.i" => "__nvvm_popc_i",
+    "llvm.nvvm.popc.ll" => "__nvvm_popc_ll",
+    "llvm.nvvm.prmt" => "__nvvm_prmt",
+    "llvm.nvvm.rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d",
+    "llvm.nvvm.rcp.rm.d" => "__nvvm_rcp_rm_d",
+    "llvm.nvvm.rcp.rm.f" => "__nvvm_rcp_rm_f",
+    "llvm.nvvm.rcp.rm.ftz.f" => "__nvvm_rcp_rm_ftz_f",
+    "llvm.nvvm.rcp.rn.d" => "__nvvm_rcp_rn_d",
+    "llvm.nvvm.rcp.rn.f" => "__nvvm_rcp_rn_f",
+    "llvm.nvvm.rcp.rn.ftz.f" => "__nvvm_rcp_rn_ftz_f",
+    "llvm.nvvm.rcp.rp.d" => "__nvvm_rcp_rp_d",
+    "llvm.nvvm.rcp.rp.f" => "__nvvm_rcp_rp_f",
+    "llvm.nvvm.rcp.rp.ftz.f" => "__nvvm_rcp_rp_ftz_f",
+    "llvm.nvvm.rcp.rz.d" => "__nvvm_rcp_rz_d",
+    "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f",
+    "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f",
+    "llvm.nvvm.read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x",
+    "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y",
+    "llvm.nvvm.read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z",
+    "llvm.nvvm.read.ptx.sreg.envreg0" => "__nvvm_read_ptx_sreg_envreg0",
+    "llvm.nvvm.read.ptx.sreg.envreg1" => "__nvvm_read_ptx_sreg_envreg1",
+    "llvm.nvvm.read.ptx.sreg.envreg10" => "__nvvm_read_ptx_sreg_envreg10",
+    "llvm.nvvm.read.ptx.sreg.envreg11" => "__nvvm_read_ptx_sreg_envreg11",
+    "llvm.nvvm.read.ptx.sreg.envreg12" => "__nvvm_read_ptx_sreg_envreg12",
+    "llvm.nvvm.read.ptx.sreg.envreg13" => "__nvvm_read_ptx_sreg_envreg13",
+    "llvm.nvvm.read.ptx.sreg.envreg14" => "__nvvm_read_ptx_sreg_envreg14",
+    "llvm.nvvm.read.ptx.sreg.envreg15" => "__nvvm_read_ptx_sreg_envreg15",
+    "llvm.nvvm.read.ptx.sreg.envreg16" => "__nvvm_read_ptx_sreg_envreg16",
+    "llvm.nvvm.read.ptx.sreg.envreg17" => "__nvvm_read_ptx_sreg_envreg17",
+    "llvm.nvvm.read.ptx.sreg.envreg18" => "__nvvm_read_ptx_sreg_envreg18",
+    "llvm.nvvm.read.ptx.sreg.envreg19" => "__nvvm_read_ptx_sreg_envreg19",
+    "llvm.nvvm.read.ptx.sreg.envreg2" => "__nvvm_read_ptx_sreg_envreg2",
+    "llvm.nvvm.read.ptx.sreg.envreg20" => "__nvvm_read_ptx_sreg_envreg20",
+    "llvm.nvvm.read.ptx.sreg.envreg21" => "__nvvm_read_ptx_sreg_envreg21",
+    "llvm.nvvm.read.ptx.sreg.envreg22" => "__nvvm_read_ptx_sreg_envreg22",
+    "llvm.nvvm.read.ptx.sreg.envreg23" => "__nvvm_read_ptx_sreg_envreg23",
+    "llvm.nvvm.read.ptx.sreg.envreg24" => "__nvvm_read_ptx_sreg_envreg24",
+    "llvm.nvvm.read.ptx.sreg.envreg25" => "__nvvm_read_ptx_sreg_envreg25",
+    "llvm.nvvm.read.ptx.sreg.envreg26" => "__nvvm_read_ptx_sreg_envreg26",
+    "llvm.nvvm.read.ptx.sreg.envreg27" => "__nvvm_read_ptx_sreg_envreg27",
+    "llvm.nvvm.read.ptx.sreg.envreg28" => "__nvvm_read_ptx_sreg_envreg28",
+    "llvm.nvvm.read.ptx.sreg.envreg29" => "__nvvm_read_ptx_sreg_envreg29",
+    "llvm.nvvm.read.ptx.sreg.envreg3" => "__nvvm_read_ptx_sreg_envreg3",
+    "llvm.nvvm.read.ptx.sreg.envreg30" => "__nvvm_read_ptx_sreg_envreg30",
+    "llvm.nvvm.read.ptx.sreg.envreg31" => "__nvvm_read_ptx_sreg_envreg31",
+    "llvm.nvvm.read.ptx.sreg.envreg4" => "__nvvm_read_ptx_sreg_envreg4",
+    "llvm.nvvm.read.ptx.sreg.envreg5" => "__nvvm_read_ptx_sreg_envreg5",
+    "llvm.nvvm.read.ptx.sreg.envreg6" => "__nvvm_read_ptx_sreg_envreg6",
+    "llvm.nvvm.read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7",
+    "llvm.nvvm.read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8",
+    "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9",
+    "llvm.nvvm.read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x",
+    "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y",
+    "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z",
+    "llvm.nvvm.read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x",
+    "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y",
+    "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z",
+    "llvm.nvvm.read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x",
+    "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y",
+    "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z",
+    "llvm.nvvm.read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize",
+    // [DUPLICATE]: "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_",
+    "llvm.nvvm.rotate.b32" => "__nvvm_rotate_b32",
+    "llvm.nvvm.rotate.b64" => "__nvvm_rotate_b64",
+    "llvm.nvvm.rotate.right.b64" => "__nvvm_rotate_right_b64",
+    "llvm.nvvm.round.d" => "__nvvm_round_d",
+    "llvm.nvvm.round.f" => "__nvvm_round_f",
+    "llvm.nvvm.round.ftz.f" => "__nvvm_round_ftz_f",
+    "llvm.nvvm.rsqrt.approx.d" => "__nvvm_rsqrt_approx_d",
+    "llvm.nvvm.rsqrt.approx.f" => "__nvvm_rsqrt_approx_f",
+    "llvm.nvvm.rsqrt.approx.ftz.f" => "__nvvm_rsqrt_approx_ftz_f",
+    "llvm.nvvm.sad.i" => "__nvvm_sad_i",
+    "llvm.nvvm.sad.ui" => "__nvvm_sad_ui",
+    "llvm.nvvm.saturate.d" => "__nvvm_saturate_d",
+    "llvm.nvvm.saturate.f" => "__nvvm_saturate_f",
+    "llvm.nvvm.saturate.ftz.f" => "__nvvm_saturate_ftz_f",
+    "llvm.nvvm.shfl.bfly.f32" => "__nvvm_shfl_bfly_f32",
+    "llvm.nvvm.shfl.bfly.i32" => "__nvvm_shfl_bfly_i32",
+    "llvm.nvvm.shfl.down.f32" => "__nvvm_shfl_down_f32",
+    "llvm.nvvm.shfl.down.i32" => "__nvvm_shfl_down_i32",
+    "llvm.nvvm.shfl.idx.f32" => "__nvvm_shfl_idx_f32",
+    "llvm.nvvm.shfl.idx.i32" => "__nvvm_shfl_idx_i32",
+    "llvm.nvvm.shfl.up.f32" => "__nvvm_shfl_up_f32",
+    "llvm.nvvm.shfl.up.i32" => "__nvvm_shfl_up_i32",
+    "llvm.nvvm.sin.approx.f" => "__nvvm_sin_approx_f",
+    "llvm.nvvm.sin.approx.ftz.f" => "__nvvm_sin_approx_ftz_f",
+    "llvm.nvvm.sqrt.approx.f" => "__nvvm_sqrt_approx_f",
+    "llvm.nvvm.sqrt.approx.ftz.f" => "__nvvm_sqrt_approx_ftz_f",
+    "llvm.nvvm.sqrt.f" => "__nvvm_sqrt_f",
+    "llvm.nvvm.sqrt.rm.d" => "__nvvm_sqrt_rm_d",
+    "llvm.nvvm.sqrt.rm.f" => "__nvvm_sqrt_rm_f",
+    "llvm.nvvm.sqrt.rm.ftz.f" => "__nvvm_sqrt_rm_ftz_f",
+    "llvm.nvvm.sqrt.rn.d" => "__nvvm_sqrt_rn_d",
+    "llvm.nvvm.sqrt.rn.f" => "__nvvm_sqrt_rn_f",
+    "llvm.nvvm.sqrt.rn.ftz.f" => "__nvvm_sqrt_rn_ftz_f",
+    "llvm.nvvm.sqrt.rp.d" => "__nvvm_sqrt_rp_d",
+    "llvm.nvvm.sqrt.rp.f" => "__nvvm_sqrt_rp_f",
+    "llvm.nvvm.sqrt.rp.ftz.f" => "__nvvm_sqrt_rp_ftz_f",
+    "llvm.nvvm.sqrt.rz.d" => "__nvvm_sqrt_rz_d",
+    "llvm.nvvm.sqrt.rz.f" => "__nvvm_sqrt_rz_f",
+    "llvm.nvvm.sqrt.rz.ftz.f" => "__nvvm_sqrt_rz_ftz_f",
+    "llvm.nvvm.suq.array.size" => "__nvvm_suq_array_size",
+    "llvm.nvvm.suq.channel.data.type" => "__nvvm_suq_channel_data_type",
+    "llvm.nvvm.suq.channel.order" => "__nvvm_suq_channel_order",
+    "llvm.nvvm.suq.depth" => "__nvvm_suq_depth",
+    "llvm.nvvm.suq.height" => "__nvvm_suq_height",
+    "llvm.nvvm.suq.width" => "__nvvm_suq_width",
+    "llvm.nvvm.sust.b.1d.array.i16.clamp" => "__nvvm_sust_b_1d_array_i16_clamp",
+    "llvm.nvvm.sust.b.1d.array.i16.trap" => "__nvvm_sust_b_1d_array_i16_trap",
+    "llvm.nvvm.sust.b.1d.array.i16.zero" => "__nvvm_sust_b_1d_array_i16_zero",
+    "llvm.nvvm.sust.b.1d.array.i32.clamp" => "__nvvm_sust_b_1d_array_i32_clamp",
+    "llvm.nvvm.sust.b.1d.array.i32.trap" => "__nvvm_sust_b_1d_array_i32_trap",
+    "llvm.nvvm.sust.b.1d.array.i32.zero" => "__nvvm_sust_b_1d_array_i32_zero",
+    "llvm.nvvm.sust.b.1d.array.i64.clamp" => "__nvvm_sust_b_1d_array_i64_clamp",
+    "llvm.nvvm.sust.b.1d.array.i64.trap" => "__nvvm_sust_b_1d_array_i64_trap",
+    "llvm.nvvm.sust.b.1d.array.i64.zero" => "__nvvm_sust_b_1d_array_i64_zero",
+    "llvm.nvvm.sust.b.1d.array.i8.clamp" => "__nvvm_sust_b_1d_array_i8_clamp",
+    "llvm.nvvm.sust.b.1d.array.i8.trap" => "__nvvm_sust_b_1d_array_i8_trap",
+    "llvm.nvvm.sust.b.1d.array.i8.zero" => "__nvvm_sust_b_1d_array_i8_zero",
+    "llvm.nvvm.sust.b.1d.array.v2i16.clamp" => "__nvvm_sust_b_1d_array_v2i16_clamp",
+    "llvm.nvvm.sust.b.1d.array.v2i16.trap" => "__nvvm_sust_b_1d_array_v2i16_trap",
+    "llvm.nvvm.sust.b.1d.array.v2i16.zero" => "__nvvm_sust_b_1d_array_v2i16_zero",
+    "llvm.nvvm.sust.b.1d.array.v2i32.clamp" => "__nvvm_sust_b_1d_array_v2i32_clamp",
+    "llvm.nvvm.sust.b.1d.array.v2i32.trap" => "__nvvm_sust_b_1d_array_v2i32_trap",
+    "llvm.nvvm.sust.b.1d.array.v2i32.zero" => "__nvvm_sust_b_1d_array_v2i32_zero",
+    "llvm.nvvm.sust.b.1d.array.v2i64.clamp" => "__nvvm_sust_b_1d_array_v2i64_clamp",
+    "llvm.nvvm.sust.b.1d.array.v2i64.trap" => "__nvvm_sust_b_1d_array_v2i64_trap",
+    "llvm.nvvm.sust.b.1d.array.v2i64.zero" => "__nvvm_sust_b_1d_array_v2i64_zero",
+    "llvm.nvvm.sust.b.1d.array.v2i8.clamp" => "__nvvm_sust_b_1d_array_v2i8_clamp",
+    "llvm.nvvm.sust.b.1d.array.v2i8.trap" => "__nvvm_sust_b_1d_array_v2i8_trap",
+    "llvm.nvvm.sust.b.1d.array.v2i8.zero" => "__nvvm_sust_b_1d_array_v2i8_zero",
+    "llvm.nvvm.sust.b.1d.array.v4i16.clamp" => "__nvvm_sust_b_1d_array_v4i16_clamp",
+    "llvm.nvvm.sust.b.1d.array.v4i16.trap" => "__nvvm_sust_b_1d_array_v4i16_trap",
+    "llvm.nvvm.sust.b.1d.array.v4i16.zero" => "__nvvm_sust_b_1d_array_v4i16_zero",
+    "llvm.nvvm.sust.b.1d.array.v4i32.clamp" => "__nvvm_sust_b_1d_array_v4i32_clamp",
+    "llvm.nvvm.sust.b.1d.array.v4i32.trap" => "__nvvm_sust_b_1d_array_v4i32_trap",
+    "llvm.nvvm.sust.b.1d.array.v4i32.zero" => "__nvvm_sust_b_1d_array_v4i32_zero",
+    "llvm.nvvm.sust.b.1d.array.v4i8.clamp" => "__nvvm_sust_b_1d_array_v4i8_clamp",
+    "llvm.nvvm.sust.b.1d.array.v4i8.trap" => "__nvvm_sust_b_1d_array_v4i8_trap",
+    "llvm.nvvm.sust.b.1d.array.v4i8.zero" => "__nvvm_sust_b_1d_array_v4i8_zero",
+    "llvm.nvvm.sust.b.1d.i16.clamp" => "__nvvm_sust_b_1d_i16_clamp",
+    "llvm.nvvm.sust.b.1d.i16.trap" => "__nvvm_sust_b_1d_i16_trap",
+    "llvm.nvvm.sust.b.1d.i16.zero" => "__nvvm_sust_b_1d_i16_zero",
+    "llvm.nvvm.sust.b.1d.i32.clamp" => "__nvvm_sust_b_1d_i32_clamp",
+    "llvm.nvvm.sust.b.1d.i32.trap" => "__nvvm_sust_b_1d_i32_trap",
+    "llvm.nvvm.sust.b.1d.i32.zero" => "__nvvm_sust_b_1d_i32_zero",
+    "llvm.nvvm.sust.b.1d.i64.clamp" => "__nvvm_sust_b_1d_i64_clamp",
+    "llvm.nvvm.sust.b.1d.i64.trap" => "__nvvm_sust_b_1d_i64_trap",
+    "llvm.nvvm.sust.b.1d.i64.zero" => "__nvvm_sust_b_1d_i64_zero",
+    "llvm.nvvm.sust.b.1d.i8.clamp" => "__nvvm_sust_b_1d_i8_clamp",
+    "llvm.nvvm.sust.b.1d.i8.trap" => "__nvvm_sust_b_1d_i8_trap",
+    "llvm.nvvm.sust.b.1d.i8.zero" => "__nvvm_sust_b_1d_i8_zero",
+    "llvm.nvvm.sust.b.1d.v2i16.clamp" => "__nvvm_sust_b_1d_v2i16_clamp",
+    "llvm.nvvm.sust.b.1d.v2i16.trap" => "__nvvm_sust_b_1d_v2i16_trap",
+    "llvm.nvvm.sust.b.1d.v2i16.zero" => "__nvvm_sust_b_1d_v2i16_zero",
+    "llvm.nvvm.sust.b.1d.v2i32.clamp" => "__nvvm_sust_b_1d_v2i32_clamp",
+    "llvm.nvvm.sust.b.1d.v2i32.trap" => "__nvvm_sust_b_1d_v2i32_trap",
+    "llvm.nvvm.sust.b.1d.v2i32.zero" => "__nvvm_sust_b_1d_v2i32_zero",
+    "llvm.nvvm.sust.b.1d.v2i64.clamp" => "__nvvm_sust_b_1d_v2i64_clamp",
+    "llvm.nvvm.sust.b.1d.v2i64.trap" => "__nvvm_sust_b_1d_v2i64_trap",
+    "llvm.nvvm.sust.b.1d.v2i64.zero" => "__nvvm_sust_b_1d_v2i64_zero",
+    "llvm.nvvm.sust.b.1d.v2i8.clamp" => "__nvvm_sust_b_1d_v2i8_clamp",
+    "llvm.nvvm.sust.b.1d.v2i8.trap" => "__nvvm_sust_b_1d_v2i8_trap",
+    "llvm.nvvm.sust.b.1d.v2i8.zero" => "__nvvm_sust_b_1d_v2i8_zero",
+    "llvm.nvvm.sust.b.1d.v4i16.clamp" => "__nvvm_sust_b_1d_v4i16_clamp",
+    "llvm.nvvm.sust.b.1d.v4i16.trap" => "__nvvm_sust_b_1d_v4i16_trap",
+    "llvm.nvvm.sust.b.1d.v4i16.zero" => "__nvvm_sust_b_1d_v4i16_zero",
+    "llvm.nvvm.sust.b.1d.v4i32.clamp" => "__nvvm_sust_b_1d_v4i32_clamp",
+    "llvm.nvvm.sust.b.1d.v4i32.trap" => "__nvvm_sust_b_1d_v4i32_trap",
+    "llvm.nvvm.sust.b.1d.v4i32.zero" => "__nvvm_sust_b_1d_v4i32_zero",
+    "llvm.nvvm.sust.b.1d.v4i8.clamp" => "__nvvm_sust_b_1d_v4i8_clamp",
+    "llvm.nvvm.sust.b.1d.v4i8.trap" => "__nvvm_sust_b_1d_v4i8_trap",
+    "llvm.nvvm.sust.b.1d.v4i8.zero" => "__nvvm_sust_b_1d_v4i8_zero",
+    "llvm.nvvm.sust.b.2d.array.i16.clamp" => "__nvvm_sust_b_2d_array_i16_clamp",
+    "llvm.nvvm.sust.b.2d.array.i16.trap" => "__nvvm_sust_b_2d_array_i16_trap",
+    "llvm.nvvm.sust.b.2d.array.i16.zero" => "__nvvm_sust_b_2d_array_i16_zero",
+    "llvm.nvvm.sust.b.2d.array.i32.clamp" => "__nvvm_sust_b_2d_array_i32_clamp",
+    "llvm.nvvm.sust.b.2d.array.i32.trap" => "__nvvm_sust_b_2d_array_i32_trap",
+    "llvm.nvvm.sust.b.2d.array.i32.zero" => "__nvvm_sust_b_2d_array_i32_zero",
+    "llvm.nvvm.sust.b.2d.array.i64.clamp" => "__nvvm_sust_b_2d_array_i64_clamp",
+    "llvm.nvvm.sust.b.2d.array.i64.trap" => "__nvvm_sust_b_2d_array_i64_trap",
+    "llvm.nvvm.sust.b.2d.array.i64.zero" => "__nvvm_sust_b_2d_array_i64_zero",
+    "llvm.nvvm.sust.b.2d.array.i8.clamp" => "__nvvm_sust_b_2d_array_i8_clamp",
+    "llvm.nvvm.sust.b.2d.array.i8.trap" => "__nvvm_sust_b_2d_array_i8_trap",
+    "llvm.nvvm.sust.b.2d.array.i8.zero" => "__nvvm_sust_b_2d_array_i8_zero",
+    "llvm.nvvm.sust.b.2d.array.v2i16.clamp" => "__nvvm_sust_b_2d_array_v2i16_clamp",
+    "llvm.nvvm.sust.b.2d.array.v2i16.trap" => "__nvvm_sust_b_2d_array_v2i16_trap",
+    "llvm.nvvm.sust.b.2d.array.v2i16.zero" => "__nvvm_sust_b_2d_array_v2i16_zero",
+    "llvm.nvvm.sust.b.2d.array.v2i32.clamp" => "__nvvm_sust_b_2d_array_v2i32_clamp",
+    "llvm.nvvm.sust.b.2d.array.v2i32.trap" => "__nvvm_sust_b_2d_array_v2i32_trap",
+    "llvm.nvvm.sust.b.2d.array.v2i32.zero" => "__nvvm_sust_b_2d_array_v2i32_zero",
+    "llvm.nvvm.sust.b.2d.array.v2i64.clamp" => "__nvvm_sust_b_2d_array_v2i64_clamp",
+    "llvm.nvvm.sust.b.2d.array.v2i64.trap" => "__nvvm_sust_b_2d_array_v2i64_trap",
+    "llvm.nvvm.sust.b.2d.array.v2i64.zero" => "__nvvm_sust_b_2d_array_v2i64_zero",
+    "llvm.nvvm.sust.b.2d.array.v2i8.clamp" => "__nvvm_sust_b_2d_array_v2i8_clamp",
+    "llvm.nvvm.sust.b.2d.array.v2i8.trap" => "__nvvm_sust_b_2d_array_v2i8_trap",
+    "llvm.nvvm.sust.b.2d.array.v2i8.zero" => "__nvvm_sust_b_2d_array_v2i8_zero",
+    "llvm.nvvm.sust.b.2d.array.v4i16.clamp" => "__nvvm_sust_b_2d_array_v4i16_clamp",
+    "llvm.nvvm.sust.b.2d.array.v4i16.trap" => "__nvvm_sust_b_2d_array_v4i16_trap",
+    "llvm.nvvm.sust.b.2d.array.v4i16.zero" => "__nvvm_sust_b_2d_array_v4i16_zero",
+    "llvm.nvvm.sust.b.2d.array.v4i32.clamp" => "__nvvm_sust_b_2d_array_v4i32_clamp",
+    "llvm.nvvm.sust.b.2d.array.v4i32.trap" => "__nvvm_sust_b_2d_array_v4i32_trap",
+    "llvm.nvvm.sust.b.2d.array.v4i32.zero" => "__nvvm_sust_b_2d_array_v4i32_zero",
+    "llvm.nvvm.sust.b.2d.array.v4i8.clamp" => "__nvvm_sust_b_2d_array_v4i8_clamp",
+    "llvm.nvvm.sust.b.2d.array.v4i8.trap" => "__nvvm_sust_b_2d_array_v4i8_trap",
+    "llvm.nvvm.sust.b.2d.array.v4i8.zero" => "__nvvm_sust_b_2d_array_v4i8_zero",
+    "llvm.nvvm.sust.b.2d.i16.clamp" => "__nvvm_sust_b_2d_i16_clamp",
+    "llvm.nvvm.sust.b.2d.i16.trap" => "__nvvm_sust_b_2d_i16_trap",
+    "llvm.nvvm.sust.b.2d.i16.zero" => "__nvvm_sust_b_2d_i16_zero",
+    "llvm.nvvm.sust.b.2d.i32.clamp" => "__nvvm_sust_b_2d_i32_clamp",
+    "llvm.nvvm.sust.b.2d.i32.trap" => "__nvvm_sust_b_2d_i32_trap",
+    "llvm.nvvm.sust.b.2d.i32.zero" => "__nvvm_sust_b_2d_i32_zero",
+    "llvm.nvvm.sust.b.2d.i64.clamp" => "__nvvm_sust_b_2d_i64_clamp",
+    "llvm.nvvm.sust.b.2d.i64.trap" => "__nvvm_sust_b_2d_i64_trap",
+    "llvm.nvvm.sust.b.2d.i64.zero" => "__nvvm_sust_b_2d_i64_zero",
+    "llvm.nvvm.sust.b.2d.i8.clamp" => "__nvvm_sust_b_2d_i8_clamp",
+    "llvm.nvvm.sust.b.2d.i8.trap" => "__nvvm_sust_b_2d_i8_trap",
+    "llvm.nvvm.sust.b.2d.i8.zero" => "__nvvm_sust_b_2d_i8_zero",
+    "llvm.nvvm.sust.b.2d.v2i16.clamp" => "__nvvm_sust_b_2d_v2i16_clamp",
+    "llvm.nvvm.sust.b.2d.v2i16.trap" => "__nvvm_sust_b_2d_v2i16_trap",
+    "llvm.nvvm.sust.b.2d.v2i16.zero" => "__nvvm_sust_b_2d_v2i16_zero",
+    "llvm.nvvm.sust.b.2d.v2i32.clamp" => "__nvvm_sust_b_2d_v2i32_clamp",
+    "llvm.nvvm.sust.b.2d.v2i32.trap" => "__nvvm_sust_b_2d_v2i32_trap",
+    "llvm.nvvm.sust.b.2d.v2i32.zero" => "__nvvm_sust_b_2d_v2i32_zero",
+    "llvm.nvvm.sust.b.2d.v2i64.clamp" => "__nvvm_sust_b_2d_v2i64_clamp",
+    "llvm.nvvm.sust.b.2d.v2i64.trap" => "__nvvm_sust_b_2d_v2i64_trap",
+    "llvm.nvvm.sust.b.2d.v2i64.zero" => "__nvvm_sust_b_2d_v2i64_zero",
+    "llvm.nvvm.sust.b.2d.v2i8.clamp" => "__nvvm_sust_b_2d_v2i8_clamp",
+    "llvm.nvvm.sust.b.2d.v2i8.trap" => "__nvvm_sust_b_2d_v2i8_trap",
+    "llvm.nvvm.sust.b.2d.v2i8.zero" => "__nvvm_sust_b_2d_v2i8_zero",
+    "llvm.nvvm.sust.b.2d.v4i16.clamp" => "__nvvm_sust_b_2d_v4i16_clamp",
+    "llvm.nvvm.sust.b.2d.v4i16.trap" => "__nvvm_sust_b_2d_v4i16_trap",
+    "llvm.nvvm.sust.b.2d.v4i16.zero" => "__nvvm_sust_b_2d_v4i16_zero",
+    "llvm.nvvm.sust.b.2d.v4i32.clamp" => "__nvvm_sust_b_2d_v4i32_clamp",
+    "llvm.nvvm.sust.b.2d.v4i32.trap" => "__nvvm_sust_b_2d_v4i32_trap",
+    "llvm.nvvm.sust.b.2d.v4i32.zero" => "__nvvm_sust_b_2d_v4i32_zero",
+    "llvm.nvvm.sust.b.2d.v4i8.clamp" => "__nvvm_sust_b_2d_v4i8_clamp",
+    "llvm.nvvm.sust.b.2d.v4i8.trap" => "__nvvm_sust_b_2d_v4i8_trap",
+    "llvm.nvvm.sust.b.2d.v4i8.zero" => "__nvvm_sust_b_2d_v4i8_zero",
+    "llvm.nvvm.sust.b.3d.i16.clamp" => "__nvvm_sust_b_3d_i16_clamp",
+    "llvm.nvvm.sust.b.3d.i16.trap" => "__nvvm_sust_b_3d_i16_trap",
+    "llvm.nvvm.sust.b.3d.i16.zero" => "__nvvm_sust_b_3d_i16_zero",
+    "llvm.nvvm.sust.b.3d.i32.clamp" => "__nvvm_sust_b_3d_i32_clamp",
+    "llvm.nvvm.sust.b.3d.i32.trap" => "__nvvm_sust_b_3d_i32_trap",
+    "llvm.nvvm.sust.b.3d.i32.zero" => "__nvvm_sust_b_3d_i32_zero",
+    "llvm.nvvm.sust.b.3d.i64.clamp" => "__nvvm_sust_b_3d_i64_clamp",
+    "llvm.nvvm.sust.b.3d.i64.trap" => "__nvvm_sust_b_3d_i64_trap",
+    "llvm.nvvm.sust.b.3d.i64.zero" => "__nvvm_sust_b_3d_i64_zero",
+    "llvm.nvvm.sust.b.3d.i8.clamp" => "__nvvm_sust_b_3d_i8_clamp",
+    "llvm.nvvm.sust.b.3d.i8.trap" => "__nvvm_sust_b_3d_i8_trap",
+    "llvm.nvvm.sust.b.3d.i8.zero" => "__nvvm_sust_b_3d_i8_zero",
+    "llvm.nvvm.sust.b.3d.v2i16.clamp" => "__nvvm_sust_b_3d_v2i16_clamp",
+    "llvm.nvvm.sust.b.3d.v2i16.trap" => "__nvvm_sust_b_3d_v2i16_trap",
+    "llvm.nvvm.sust.b.3d.v2i16.zero" => "__nvvm_sust_b_3d_v2i16_zero",
+    "llvm.nvvm.sust.b.3d.v2i32.clamp" => "__nvvm_sust_b_3d_v2i32_clamp",
+    "llvm.nvvm.sust.b.3d.v2i32.trap" => "__nvvm_sust_b_3d_v2i32_trap",
+    "llvm.nvvm.sust.b.3d.v2i32.zero" => "__nvvm_sust_b_3d_v2i32_zero",
+    "llvm.nvvm.sust.b.3d.v2i64.clamp" => "__nvvm_sust_b_3d_v2i64_clamp",
+    "llvm.nvvm.sust.b.3d.v2i64.trap" => "__nvvm_sust_b_3d_v2i64_trap",
+    "llvm.nvvm.sust.b.3d.v2i64.zero" => "__nvvm_sust_b_3d_v2i64_zero",
+    "llvm.nvvm.sust.b.3d.v2i8.clamp" => "__nvvm_sust_b_3d_v2i8_clamp",
+    "llvm.nvvm.sust.b.3d.v2i8.trap" => "__nvvm_sust_b_3d_v2i8_trap",
+    "llvm.nvvm.sust.b.3d.v2i8.zero" => "__nvvm_sust_b_3d_v2i8_zero",
+    "llvm.nvvm.sust.b.3d.v4i16.clamp" => "__nvvm_sust_b_3d_v4i16_clamp",
+    "llvm.nvvm.sust.b.3d.v4i16.trap" => "__nvvm_sust_b_3d_v4i16_trap",
+    "llvm.nvvm.sust.b.3d.v4i16.zero" => "__nvvm_sust_b_3d_v4i16_zero",
+    "llvm.nvvm.sust.b.3d.v4i32.clamp" => "__nvvm_sust_b_3d_v4i32_clamp",
+    "llvm.nvvm.sust.b.3d.v4i32.trap" => "__nvvm_sust_b_3d_v4i32_trap",
+    "llvm.nvvm.sust.b.3d.v4i32.zero" => "__nvvm_sust_b_3d_v4i32_zero",
+    "llvm.nvvm.sust.b.3d.v4i8.clamp" => "__nvvm_sust_b_3d_v4i8_clamp",
+    "llvm.nvvm.sust.b.3d.v4i8.trap" => "__nvvm_sust_b_3d_v4i8_trap",
+    "llvm.nvvm.sust.b.3d.v4i8.zero" => "__nvvm_sust_b_3d_v4i8_zero",
+    "llvm.nvvm.sust.p.1d.array.i16.trap" => "__nvvm_sust_p_1d_array_i16_trap",
+    "llvm.nvvm.sust.p.1d.array.i32.trap" => "__nvvm_sust_p_1d_array_i32_trap",
+    "llvm.nvvm.sust.p.1d.array.i8.trap" => "__nvvm_sust_p_1d_array_i8_trap",
+    "llvm.nvvm.sust.p.1d.array.v2i16.trap" => "__nvvm_sust_p_1d_array_v2i16_trap",
+    "llvm.nvvm.sust.p.1d.array.v2i32.trap" => "__nvvm_sust_p_1d_array_v2i32_trap",
+    "llvm.nvvm.sust.p.1d.array.v2i8.trap" => "__nvvm_sust_p_1d_array_v2i8_trap",
+    "llvm.nvvm.sust.p.1d.array.v4i16.trap" => "__nvvm_sust_p_1d_array_v4i16_trap",
+    "llvm.nvvm.sust.p.1d.array.v4i32.trap" => "__nvvm_sust_p_1d_array_v4i32_trap",
+    "llvm.nvvm.sust.p.1d.array.v4i8.trap" => "__nvvm_sust_p_1d_array_v4i8_trap",
+    "llvm.nvvm.sust.p.1d.i16.trap" => "__nvvm_sust_p_1d_i16_trap",
+    "llvm.nvvm.sust.p.1d.i32.trap" => "__nvvm_sust_p_1d_i32_trap",
+    "llvm.nvvm.sust.p.1d.i8.trap" => "__nvvm_sust_p_1d_i8_trap",
+    "llvm.nvvm.sust.p.1d.v2i16.trap" => "__nvvm_sust_p_1d_v2i16_trap",
+    "llvm.nvvm.sust.p.1d.v2i32.trap" => "__nvvm_sust_p_1d_v2i32_trap",
+    "llvm.nvvm.sust.p.1d.v2i8.trap" => "__nvvm_sust_p_1d_v2i8_trap",
+    "llvm.nvvm.sust.p.1d.v4i16.trap" => "__nvvm_sust_p_1d_v4i16_trap",
+    "llvm.nvvm.sust.p.1d.v4i32.trap" => "__nvvm_sust_p_1d_v4i32_trap",
+    "llvm.nvvm.sust.p.1d.v4i8.trap" => "__nvvm_sust_p_1d_v4i8_trap",
+    "llvm.nvvm.sust.p.2d.array.i16.trap" => "__nvvm_sust_p_2d_array_i16_trap",
+    "llvm.nvvm.sust.p.2d.array.i32.trap" => "__nvvm_sust_p_2d_array_i32_trap",
+    "llvm.nvvm.sust.p.2d.array.i8.trap" => "__nvvm_sust_p_2d_array_i8_trap",
+    "llvm.nvvm.sust.p.2d.array.v2i16.trap" => "__nvvm_sust_p_2d_array_v2i16_trap",
+    "llvm.nvvm.sust.p.2d.array.v2i32.trap" => "__nvvm_sust_p_2d_array_v2i32_trap",
+    "llvm.nvvm.sust.p.2d.array.v2i8.trap" => "__nvvm_sust_p_2d_array_v2i8_trap",
+    "llvm.nvvm.sust.p.2d.array.v4i16.trap" => "__nvvm_sust_p_2d_array_v4i16_trap",
+    "llvm.nvvm.sust.p.2d.array.v4i32.trap" => "__nvvm_sust_p_2d_array_v4i32_trap",
+    "llvm.nvvm.sust.p.2d.array.v4i8.trap" => "__nvvm_sust_p_2d_array_v4i8_trap",
+    "llvm.nvvm.sust.p.2d.i16.trap" => "__nvvm_sust_p_2d_i16_trap",
+    "llvm.nvvm.sust.p.2d.i32.trap" => "__nvvm_sust_p_2d_i32_trap",
+    "llvm.nvvm.sust.p.2d.i8.trap" => "__nvvm_sust_p_2d_i8_trap",
+    "llvm.nvvm.sust.p.2d.v2i16.trap" => "__nvvm_sust_p_2d_v2i16_trap",
+    "llvm.nvvm.sust.p.2d.v2i32.trap" => "__nvvm_sust_p_2d_v2i32_trap",
+    "llvm.nvvm.sust.p.2d.v2i8.trap" => "__nvvm_sust_p_2d_v2i8_trap",
+    "llvm.nvvm.sust.p.2d.v4i16.trap" => "__nvvm_sust_p_2d_v4i16_trap",
+    "llvm.nvvm.sust.p.2d.v4i32.trap" => "__nvvm_sust_p_2d_v4i32_trap",
+    "llvm.nvvm.sust.p.2d.v4i8.trap" => "__nvvm_sust_p_2d_v4i8_trap",
+    "llvm.nvvm.sust.p.3d.i16.trap" => "__nvvm_sust_p_3d_i16_trap",
+    "llvm.nvvm.sust.p.3d.i32.trap" => "__nvvm_sust_p_3d_i32_trap",
+    "llvm.nvvm.sust.p.3d.i8.trap" => "__nvvm_sust_p_3d_i8_trap",
+    "llvm.nvvm.sust.p.3d.v2i16.trap" => "__nvvm_sust_p_3d_v2i16_trap",
+    "llvm.nvvm.sust.p.3d.v2i32.trap" => "__nvvm_sust_p_3d_v2i32_trap",
+    "llvm.nvvm.sust.p.3d.v2i8.trap" => "__nvvm_sust_p_3d_v2i8_trap",
+    "llvm.nvvm.sust.p.3d.v4i16.trap" => "__nvvm_sust_p_3d_v4i16_trap",
+    "llvm.nvvm.sust.p.3d.v4i32.trap" => "__nvvm_sust_p_3d_v4i32_trap",
+    "llvm.nvvm.sust.p.3d.v4i8.trap" => "__nvvm_sust_p_3d_v4i8_trap",
+    "llvm.nvvm.swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64",
+    "llvm.nvvm.trunc.d" => "__nvvm_trunc_d",
+    "llvm.nvvm.trunc.f" => "__nvvm_trunc_f",
+    "llvm.nvvm.trunc.ftz.f" => "__nvvm_trunc_ftz_f",
+    "llvm.nvvm.txq.array.size" => "__nvvm_txq_array_size",
+    "llvm.nvvm.txq.channel.data.type" => "__nvvm_txq_channel_data_type",
+    "llvm.nvvm.txq.channel.order" => "__nvvm_txq_channel_order",
+    "llvm.nvvm.txq.depth" => "__nvvm_txq_depth",
+    "llvm.nvvm.txq.height" => "__nvvm_txq_height",
+    "llvm.nvvm.txq.num.mipmap.levels" => "__nvvm_txq_num_mipmap_levels",
+    "llvm.nvvm.txq.num.samples" => "__nvvm_txq_num_samples",
+    "llvm.nvvm.txq.width" => "__nvvm_txq_width",
+    "llvm.nvvm.ui2d.rm" => "__nvvm_ui2d_rm",
+    "llvm.nvvm.ui2d.rn" => "__nvvm_ui2d_rn",
+    "llvm.nvvm.ui2d.rp" => "__nvvm_ui2d_rp",
+    "llvm.nvvm.ui2d.rz" => "__nvvm_ui2d_rz",
+    "llvm.nvvm.ui2f.rm" => "__nvvm_ui2f_rm",
+    "llvm.nvvm.ui2f.rn" => "__nvvm_ui2f_rn",
+    "llvm.nvvm.ui2f.rp" => "__nvvm_ui2f_rp",
+    "llvm.nvvm.ui2f.rz" => "__nvvm_ui2f_rz",
+    "llvm.nvvm.ull2d.rm" => "__nvvm_ull2d_rm",
+    "llvm.nvvm.ull2d.rn" => "__nvvm_ull2d_rn",
+    "llvm.nvvm.ull2d.rp" => "__nvvm_ull2d_rp",
+    "llvm.nvvm.ull2d.rz" => "__nvvm_ull2d_rz",
+    "llvm.nvvm.ull2f.rm" => "__nvvm_ull2f_rm",
+    "llvm.nvvm.ull2f.rn" => "__nvvm_ull2f_rn",
+    "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp",
+    "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz",
+    // ppc
+    "llvm.ppc.addex" => "__builtin_ppc_addex",
+    "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd",
+    "llvm.ppc.altivec.crypto.vcipher" => "__builtin_altivec_crypto_vcipher",
+    "llvm.ppc.altivec.crypto.vcipherlast" => "__builtin_altivec_crypto_vcipherlast",
+    "llvm.ppc.altivec.crypto.vncipher" => "__builtin_altivec_crypto_vncipher",
+    "llvm.ppc.altivec.crypto.vncipherlast" => "__builtin_altivec_crypto_vncipherlast",
+    "llvm.ppc.altivec.crypto.vpermxor" => "__builtin_altivec_crypto_vpermxor",
+    "llvm.ppc.altivec.crypto.vpermxor.be" => "__builtin_altivec_crypto_vpermxor_be",
+    "llvm.ppc.altivec.crypto.vpmsumb" => "__builtin_altivec_crypto_vpmsumb",
+    "llvm.ppc.altivec.crypto.vpmsumd" => "__builtin_altivec_crypto_vpmsumd",
+    "llvm.ppc.altivec.crypto.vpmsumh" => "__builtin_altivec_crypto_vpmsumh",
+    "llvm.ppc.altivec.crypto.vpmsumw" => "__builtin_altivec_crypto_vpmsumw",
+    "llvm.ppc.altivec.crypto.vsbox" => "__builtin_altivec_crypto_vsbox",
+    "llvm.ppc.altivec.crypto.vshasigmad" => "__builtin_altivec_crypto_vshasigmad",
+    "llvm.ppc.altivec.crypto.vshasigmaw" => "__builtin_altivec_crypto_vshasigmaw",
+    "llvm.ppc.altivec.dss" => "__builtin_altivec_dss",
+    "llvm.ppc.altivec.dssall" => "__builtin_altivec_dssall",
+    "llvm.ppc.altivec.dst" => "__builtin_altivec_dst",
+    "llvm.ppc.altivec.dstst" => "__builtin_altivec_dstst",
+    "llvm.ppc.altivec.dststt" => "__builtin_altivec_dststt",
+    "llvm.ppc.altivec.dstt" => "__builtin_altivec_dstt",
+    "llvm.ppc.altivec.mfvscr" => "__builtin_altivec_mfvscr",
+    "llvm.ppc.altivec.mtvscr" => "__builtin_altivec_mtvscr",
+    "llvm.ppc.altivec.mtvsrbm" => "__builtin_altivec_mtvsrbm",
+    "llvm.ppc.altivec.mtvsrdm" => "__builtin_altivec_mtvsrdm",
+    "llvm.ppc.altivec.mtvsrhm" => "__builtin_altivec_mtvsrhm",
+    "llvm.ppc.altivec.mtvsrqm" => "__builtin_altivec_mtvsrqm",
+    "llvm.ppc.altivec.mtvsrwm" => "__builtin_altivec_mtvsrwm",
+    "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw",
+    "llvm.ppc.altivec.vaddecuq" => "__builtin_altivec_vaddecuq",
+    "llvm.ppc.altivec.vaddeuqm" => "__builtin_altivec_vaddeuqm",
+    "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs",
+    "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs",
+    "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws",
+    "llvm.ppc.altivec.vaddubs" => "__builtin_altivec_vaddubs",
+    "llvm.ppc.altivec.vadduhs" => "__builtin_altivec_vadduhs",
+    "llvm.ppc.altivec.vadduws" => "__builtin_altivec_vadduws",
+    "llvm.ppc.altivec.vavgsb" => "__builtin_altivec_vavgsb",
+    "llvm.ppc.altivec.vavgsh" => "__builtin_altivec_vavgsh",
+    "llvm.ppc.altivec.vavgsw" => "__builtin_altivec_vavgsw",
+    "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub",
+    "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh",
+    "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw",
+    "llvm.ppc.altivec.vbpermd" => "__builtin_altivec_vbpermd",
+    "llvm.ppc.altivec.vbpermq" => "__builtin_altivec_vbpermq",
+    "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx",
+    "llvm.ppc.altivec.vcfuged" => "__builtin_altivec_vcfuged",
+    "llvm.ppc.altivec.vcfux" => "__builtin_altivec_vcfux",
+    "llvm.ppc.altivec.vclrlb" => "__builtin_altivec_vclrlb",
+    "llvm.ppc.altivec.vclrrb" => "__builtin_altivec_vclrrb",
+    "llvm.ppc.altivec.vclzdm" => "__builtin_altivec_vclzdm",
+    "llvm.ppc.altivec.vclzlsbb" => "__builtin_altivec_vclzlsbb",
+    "llvm.ppc.altivec.vcmpbfp" => "__builtin_altivec_vcmpbfp",
+    "llvm.ppc.altivec.vcmpbfp.p" => "__builtin_altivec_vcmpbfp_p",
+    "llvm.ppc.altivec.vcmpeqfp" => "__builtin_altivec_vcmpeqfp",
+    "llvm.ppc.altivec.vcmpeqfp.p" => "__builtin_altivec_vcmpeqfp_p",
+    "llvm.ppc.altivec.vcmpequb" => "__builtin_altivec_vcmpequb",
+    "llvm.ppc.altivec.vcmpequb.p" => "__builtin_altivec_vcmpequb_p",
+    "llvm.ppc.altivec.vcmpequd" => "__builtin_altivec_vcmpequd",
+    "llvm.ppc.altivec.vcmpequd.p" => "__builtin_altivec_vcmpequd_p",
+    "llvm.ppc.altivec.vcmpequh" => "__builtin_altivec_vcmpequh",
+    "llvm.ppc.altivec.vcmpequh.p" => "__builtin_altivec_vcmpequh_p",
+    "llvm.ppc.altivec.vcmpequq" => "__builtin_altivec_vcmpequq",
+    "llvm.ppc.altivec.vcmpequq.p" => "__builtin_altivec_vcmpequq_p",
+    "llvm.ppc.altivec.vcmpequw" => "__builtin_altivec_vcmpequw",
+    "llvm.ppc.altivec.vcmpequw.p" => "__builtin_altivec_vcmpequw_p",
+    "llvm.ppc.altivec.vcmpgefp" => "__builtin_altivec_vcmpgefp",
+    "llvm.ppc.altivec.vcmpgefp.p" => "__builtin_altivec_vcmpgefp_p",
+    "llvm.ppc.altivec.vcmpgtfp" => "__builtin_altivec_vcmpgtfp",
+    "llvm.ppc.altivec.vcmpgtfp.p" => "__builtin_altivec_vcmpgtfp_p",
+    "llvm.ppc.altivec.vcmpgtsb" => "__builtin_altivec_vcmpgtsb",
+    "llvm.ppc.altivec.vcmpgtsb.p" => "__builtin_altivec_vcmpgtsb_p",
+    "llvm.ppc.altivec.vcmpgtsd" => "__builtin_altivec_vcmpgtsd",
+    "llvm.ppc.altivec.vcmpgtsd.p" => "__builtin_altivec_vcmpgtsd_p",
+    "llvm.ppc.altivec.vcmpgtsh" => "__builtin_altivec_vcmpgtsh",
+    "llvm.ppc.altivec.vcmpgtsh.p" => "__builtin_altivec_vcmpgtsh_p",
+    "llvm.ppc.altivec.vcmpgtsq" => "__builtin_altivec_vcmpgtsq",
+    "llvm.ppc.altivec.vcmpgtsq.p" => "__builtin_altivec_vcmpgtsq_p",
+    "llvm.ppc.altivec.vcmpgtsw" => "__builtin_altivec_vcmpgtsw",
+    "llvm.ppc.altivec.vcmpgtsw.p" => "__builtin_altivec_vcmpgtsw_p",
+    "llvm.ppc.altivec.vcmpgtub" => "__builtin_altivec_vcmpgtub",
+    "llvm.ppc.altivec.vcmpgtub.p" => "__builtin_altivec_vcmpgtub_p",
+    "llvm.ppc.altivec.vcmpgtud" => "__builtin_altivec_vcmpgtud",
+    "llvm.ppc.altivec.vcmpgtud.p" => "__builtin_altivec_vcmpgtud_p",
+    "llvm.ppc.altivec.vcmpgtuh" => "__builtin_altivec_vcmpgtuh",
+    "llvm.ppc.altivec.vcmpgtuh.p" => "__builtin_altivec_vcmpgtuh_p",
+    "llvm.ppc.altivec.vcmpgtuq" => "__builtin_altivec_vcmpgtuq",
+    "llvm.ppc.altivec.vcmpgtuq.p" => "__builtin_altivec_vcmpgtuq_p",
+    "llvm.ppc.altivec.vcmpgtuw" => "__builtin_altivec_vcmpgtuw",
+    "llvm.ppc.altivec.vcmpgtuw.p" => "__builtin_altivec_vcmpgtuw_p",
+    "llvm.ppc.altivec.vcmpneb" => "__builtin_altivec_vcmpneb",
+    "llvm.ppc.altivec.vcmpneb.p" => "__builtin_altivec_vcmpneb_p",
+    "llvm.ppc.altivec.vcmpneh" => "__builtin_altivec_vcmpneh",
+    "llvm.ppc.altivec.vcmpneh.p" => "__builtin_altivec_vcmpneh_p",
+    "llvm.ppc.altivec.vcmpnew" => "__builtin_altivec_vcmpnew",
+    "llvm.ppc.altivec.vcmpnew.p" => "__builtin_altivec_vcmpnew_p",
+    "llvm.ppc.altivec.vcmpnezb" => "__builtin_altivec_vcmpnezb",
+    "llvm.ppc.altivec.vcmpnezb.p" => "__builtin_altivec_vcmpnezb_p",
+    "llvm.ppc.altivec.vcmpnezh" => "__builtin_altivec_vcmpnezh",
+    "llvm.ppc.altivec.vcmpnezh.p" => "__builtin_altivec_vcmpnezh_p",
+    "llvm.ppc.altivec.vcmpnezw" => "__builtin_altivec_vcmpnezw",
+    "llvm.ppc.altivec.vcmpnezw.p" => "__builtin_altivec_vcmpnezw_p",
+    "llvm.ppc.altivec.vcntmbb" => "__builtin_altivec_vcntmbb",
+    "llvm.ppc.altivec.vcntmbd" => "__builtin_altivec_vcntmbd",
+    "llvm.ppc.altivec.vcntmbh" => "__builtin_altivec_vcntmbh",
+    "llvm.ppc.altivec.vcntmbw" => "__builtin_altivec_vcntmbw",
+    "llvm.ppc.altivec.vctsxs" => "__builtin_altivec_vctsxs",
+    "llvm.ppc.altivec.vctuxs" => "__builtin_altivec_vctuxs",
+    "llvm.ppc.altivec.vctzdm" => "__builtin_altivec_vctzdm",
+    "llvm.ppc.altivec.vctzlsbb" => "__builtin_altivec_vctzlsbb",
+    "llvm.ppc.altivec.vexpandbm" => "__builtin_altivec_vexpandbm",
+    "llvm.ppc.altivec.vexpanddm" => "__builtin_altivec_vexpanddm",
+    "llvm.ppc.altivec.vexpandhm" => "__builtin_altivec_vexpandhm",
+    "llvm.ppc.altivec.vexpandqm" => "__builtin_altivec_vexpandqm",
+    "llvm.ppc.altivec.vexpandwm" => "__builtin_altivec_vexpandwm",
+    "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp",
+    "llvm.ppc.altivec.vextddvlx" => "__builtin_altivec_vextddvlx",
+    "llvm.ppc.altivec.vextddvrx" => "__builtin_altivec_vextddvrx",
+    "llvm.ppc.altivec.vextdubvlx" => "__builtin_altivec_vextdubvlx",
+    "llvm.ppc.altivec.vextdubvrx" => "__builtin_altivec_vextdubvrx",
+    "llvm.ppc.altivec.vextduhvlx" => "__builtin_altivec_vextduhvlx",
+    "llvm.ppc.altivec.vextduhvrx" => "__builtin_altivec_vextduhvrx",
+    "llvm.ppc.altivec.vextduwvlx" => "__builtin_altivec_vextduwvlx",
+    "llvm.ppc.altivec.vextduwvrx" => "__builtin_altivec_vextduwvrx",
+    "llvm.ppc.altivec.vextractbm" => "__builtin_altivec_vextractbm",
+    "llvm.ppc.altivec.vextractdm" => "__builtin_altivec_vextractdm",
+    "llvm.ppc.altivec.vextracthm" => "__builtin_altivec_vextracthm",
+    "llvm.ppc.altivec.vextractqm" => "__builtin_altivec_vextractqm",
+    "llvm.ppc.altivec.vextractwm" => "__builtin_altivec_vextractwm",
+    "llvm.ppc.altivec.vextsb2d" => "__builtin_altivec_vextsb2d",
+    "llvm.ppc.altivec.vextsb2w" => "__builtin_altivec_vextsb2w",
+    "llvm.ppc.altivec.vextsd2q" => "__builtin_altivec_vextsd2q",
+    "llvm.ppc.altivec.vextsh2d" => "__builtin_altivec_vextsh2d",
+    "llvm.ppc.altivec.vextsh2w" => "__builtin_altivec_vextsh2w",
+    "llvm.ppc.altivec.vextsw2d" => "__builtin_altivec_vextsw2d",
+    "llvm.ppc.altivec.vgbbd" => "__builtin_altivec_vgbbd",
+    "llvm.ppc.altivec.vgnb" => "__builtin_altivec_vgnb",
+    "llvm.ppc.altivec.vinsblx" => "__builtin_altivec_vinsblx",
+    "llvm.ppc.altivec.vinsbrx" => "__builtin_altivec_vinsbrx",
+    "llvm.ppc.altivec.vinsbvlx" => "__builtin_altivec_vinsbvlx",
+    "llvm.ppc.altivec.vinsbvrx" => "__builtin_altivec_vinsbvrx",
+    "llvm.ppc.altivec.vinsdlx" => "__builtin_altivec_vinsdlx",
+    "llvm.ppc.altivec.vinsdrx" => "__builtin_altivec_vinsdrx",
+    "llvm.ppc.altivec.vinshlx" => "__builtin_altivec_vinshlx",
+    "llvm.ppc.altivec.vinshrx" => "__builtin_altivec_vinshrx",
+    "llvm.ppc.altivec.vinshvlx" => "__builtin_altivec_vinshvlx",
+    "llvm.ppc.altivec.vinshvrx" => "__builtin_altivec_vinshvrx",
+    "llvm.ppc.altivec.vinswlx" => "__builtin_altivec_vinswlx",
+    "llvm.ppc.altivec.vinswrx" => "__builtin_altivec_vinswrx",
+    "llvm.ppc.altivec.vinswvlx" => "__builtin_altivec_vinswvlx",
+    "llvm.ppc.altivec.vinswvrx" => "__builtin_altivec_vinswvrx",
+    "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp",
+    "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp",
+    "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp",
+    "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb",
+    "llvm.ppc.altivec.vmaxsd" => "__builtin_altivec_vmaxsd",
+    "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh",
+    "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw",
+    "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub",
+    "llvm.ppc.altivec.vmaxud" => "__builtin_altivec_vmaxud",
+    "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh",
+    "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw",
+    "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs",
+    "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs",
+    "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp",
+    "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb",
+    "llvm.ppc.altivec.vminsd" => "__builtin_altivec_vminsd",
+    "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh",
+    "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw",
+    "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub",
+    "llvm.ppc.altivec.vminud" => "__builtin_altivec_vminud",
+    "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh",
+    "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw",
+    "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm",
+    "llvm.ppc.altivec.vmsumcud" => "__builtin_altivec_vmsumcud",
+    "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm",
+    "llvm.ppc.altivec.vmsumshm" => "__builtin_altivec_vmsumshm",
+    "llvm.ppc.altivec.vmsumshs" => "__builtin_altivec_vmsumshs",
+    "llvm.ppc.altivec.vmsumubm" => "__builtin_altivec_vmsumubm",
+    "llvm.ppc.altivec.vmsumudm" => "__builtin_altivec_vmsumudm",
+    "llvm.ppc.altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm",
+    "llvm.ppc.altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs",
+    "llvm.ppc.altivec.vmulesb" => "__builtin_altivec_vmulesb",
+    "llvm.ppc.altivec.vmulesh" => "__builtin_altivec_vmulesh",
+    "llvm.ppc.altivec.vmulesw" => "__builtin_altivec_vmulesw",
+    "llvm.ppc.altivec.vmuleub" => "__builtin_altivec_vmuleub",
+    "llvm.ppc.altivec.vmuleuh" => "__builtin_altivec_vmuleuh",
+    "llvm.ppc.altivec.vmuleuw" => "__builtin_altivec_vmuleuw",
+    "llvm.ppc.altivec.vmulosb" => "__builtin_altivec_vmulosb",
+    "llvm.ppc.altivec.vmulosh" => "__builtin_altivec_vmulosh",
+    "llvm.ppc.altivec.vmulosw" => "__builtin_altivec_vmulosw",
+    "llvm.ppc.altivec.vmuloub" => "__builtin_altivec_vmuloub",
+    "llvm.ppc.altivec.vmulouh" => "__builtin_altivec_vmulouh",
+    "llvm.ppc.altivec.vmulouw" => "__builtin_altivec_vmulouw",
+    "llvm.ppc.altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp",
+    "llvm.ppc.altivec.vpdepd" => "__builtin_altivec_vpdepd",
+    "llvm.ppc.altivec.vperm" => "__builtin_altivec_vperm_4si",
+    "llvm.ppc.altivec.vpextd" => "__builtin_altivec_vpextd",
+    "llvm.ppc.altivec.vpkpx" => "__builtin_altivec_vpkpx",
+    "llvm.ppc.altivec.vpksdss" => "__builtin_altivec_vpksdss",
+    "llvm.ppc.altivec.vpksdus" => "__builtin_altivec_vpksdus",
+    "llvm.ppc.altivec.vpkshss" => "__builtin_altivec_vpkshss",
+    "llvm.ppc.altivec.vpkshus" => "__builtin_altivec_vpkshus",
+    "llvm.ppc.altivec.vpkswss" => "__builtin_altivec_vpkswss",
+    "llvm.ppc.altivec.vpkswus" => "__builtin_altivec_vpkswus",
+    "llvm.ppc.altivec.vpkudus" => "__builtin_altivec_vpkudus",
+    "llvm.ppc.altivec.vpkuhus" => "__builtin_altivec_vpkuhus",
+    "llvm.ppc.altivec.vpkuwus" => "__builtin_altivec_vpkuwus",
+    "llvm.ppc.altivec.vprtybd" => "__builtin_altivec_vprtybd",
+    "llvm.ppc.altivec.vprtybq" => "__builtin_altivec_vprtybq",
+    "llvm.ppc.altivec.vprtybw" => "__builtin_altivec_vprtybw",
+    "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp",
+    "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim",
+    "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin",
+    "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip",
+    "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz",
+    "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb",
+    "llvm.ppc.altivec.vrld" => "__builtin_altivec_vrld",
+    "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh",
+    "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw",
+    "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp",
+    "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si",
+    "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl",
+    "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb",
+    "llvm.ppc.altivec.vsldbi" => "__builtin_altivec_vsldbi",
+    "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh",
+    "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo",
+    "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw",
+    "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr",
+    "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab",
+    "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah",
+    "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw",
+    "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb",
+    "llvm.ppc.altivec.vsrdbi" => "__builtin_altivec_vsrdbi",
+    "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh",
+    "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro",
+    "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw",
+    "llvm.ppc.altivec.vstribl" => "__builtin_altivec_vstribl",
+    "llvm.ppc.altivec.vstribl.p" => "__builtin_altivec_vstribl_p",
+    "llvm.ppc.altivec.vstribr" => "__builtin_altivec_vstribr",
+    "llvm.ppc.altivec.vstribr.p" => "__builtin_altivec_vstribr_p",
+    "llvm.ppc.altivec.vstrihl" => "__builtin_altivec_vstrihl",
+    "llvm.ppc.altivec.vstrihl.p" => "__builtin_altivec_vstrihl_p",
+    "llvm.ppc.altivec.vstrihr" => "__builtin_altivec_vstrihr",
+    "llvm.ppc.altivec.vstrihr.p" => "__builtin_altivec_vstrihr_p",
+    "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw",
+    "llvm.ppc.altivec.vsubecuq" => "__builtin_altivec_vsubecuq",
+    "llvm.ppc.altivec.vsubeuqm" => "__builtin_altivec_vsubeuqm",
+    "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs",
+    "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs",
+    "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws",
+    "llvm.ppc.altivec.vsububs" => "__builtin_altivec_vsububs",
+    "llvm.ppc.altivec.vsubuhs" => "__builtin_altivec_vsubuhs",
+    "llvm.ppc.altivec.vsubuws" => "__builtin_altivec_vsubuws",
+    "llvm.ppc.altivec.vsum2sws" => "__builtin_altivec_vsum2sws",
+    "llvm.ppc.altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs",
+    "llvm.ppc.altivec.vsum4shs" => "__builtin_altivec_vsum4shs",
+    "llvm.ppc.altivec.vsum4ubs" => "__builtin_altivec_vsum4ubs",
+    "llvm.ppc.altivec.vsumsws" => "__builtin_altivec_vsumsws",
+    "llvm.ppc.altivec.vupkhpx" => "__builtin_altivec_vupkhpx",
+    "llvm.ppc.altivec.vupkhsb" => "__builtin_altivec_vupkhsb",
+    "llvm.ppc.altivec.vupkhsh" => "__builtin_altivec_vupkhsh",
+    "llvm.ppc.altivec.vupkhsw" => "__builtin_altivec_vupkhsw",
+    "llvm.ppc.altivec.vupklpx" => "__builtin_altivec_vupklpx",
+    "llvm.ppc.altivec.vupklsb" => "__builtin_altivec_vupklsb",
+    "llvm.ppc.altivec.vupklsh" => "__builtin_altivec_vupklsh",
+    "llvm.ppc.altivec.vupklsw" => "__builtin_altivec_vupklsw",
+    "llvm.ppc.bcdadd" => "__builtin_ppc_bcdadd",
+    "llvm.ppc.bcdadd.p" => "__builtin_ppc_bcdadd_p",
+    "llvm.ppc.bcdsub" => "__builtin_ppc_bcdsub",
+    "llvm.ppc.bcdsub.p" => "__builtin_ppc_bcdsub_p",
+    "llvm.ppc.bpermd" => "__builtin_bpermd",
+    "llvm.ppc.cfuged" => "__builtin_cfuged",
+    "llvm.ppc.cmpeqb" => "__builtin_ppc_cmpeqb",
+    "llvm.ppc.cmprb" => "__builtin_ppc_cmprb",
+    "llvm.ppc.cntlzdm" => "__builtin_cntlzdm",
+    "llvm.ppc.cnttzdm" => "__builtin_cnttzdm",
+    "llvm.ppc.compare.exp.eq" => "__builtin_ppc_compare_exp_eq",
+    "llvm.ppc.compare.exp.gt" => "__builtin_ppc_compare_exp_gt",
+    "llvm.ppc.compare.exp.lt" => "__builtin_ppc_compare_exp_lt",
+    "llvm.ppc.compare.exp.uo" => "__builtin_ppc_compare_exp_uo",
+    "llvm.ppc.darn" => "__builtin_darn",
+    "llvm.ppc.darn32" => "__builtin_darn_32",
+    "llvm.ppc.darnraw" => "__builtin_darn_raw",
+    "llvm.ppc.dcbf" => "__builtin_dcbf",
+    "llvm.ppc.dcbfl" => "__builtin_ppc_dcbfl",
+    "llvm.ppc.dcbflp" => "__builtin_ppc_dcbflp",
+    "llvm.ppc.dcbst" => "__builtin_ppc_dcbst",
+    "llvm.ppc.dcbt" => "__builtin_ppc_dcbt",
+    "llvm.ppc.dcbtst" => "__builtin_ppc_dcbtst",
+    "llvm.ppc.dcbtstt" => "__builtin_ppc_dcbtstt",
+    "llvm.ppc.dcbtt" => "__builtin_ppc_dcbtt",
+    "llvm.ppc.dcbz" => "__builtin_ppc_dcbz",
+    "llvm.ppc.divde" => "__builtin_divde",
+    "llvm.ppc.divdeu" => "__builtin_divdeu",
+    "llvm.ppc.divf128.round.to.odd" => "__builtin_divf128_round_to_odd",
+    "llvm.ppc.divwe" => "__builtin_divwe",
+    "llvm.ppc.divweu" => "__builtin_divweu",
+    "llvm.ppc.eieio" => "__builtin_ppc_eieio",
+    "llvm.ppc.extract.exp" => "__builtin_ppc_extract_exp",
+    "llvm.ppc.extract.sig" => "__builtin_ppc_extract_sig",
+    "llvm.ppc.fcfid" => "__builtin_ppc_fcfid",
+    "llvm.ppc.fcfud" => "__builtin_ppc_fcfud",
+    "llvm.ppc.fctid" => "__builtin_ppc_fctid",
+    "llvm.ppc.fctidz" => "__builtin_ppc_fctidz",
+    "llvm.ppc.fctiw" => "__builtin_ppc_fctiw",
+    "llvm.ppc.fctiwz" => "__builtin_ppc_fctiwz",
+    "llvm.ppc.fctudz" => "__builtin_ppc_fctudz",
+    "llvm.ppc.fctuwz" => "__builtin_ppc_fctuwz",
+    "llvm.ppc.fmaf128.round.to.odd" => "__builtin_fmaf128_round_to_odd",
+    "llvm.ppc.fmsub" => "__builtin_ppc_fmsub",
+    "llvm.ppc.fmsubs" => "__builtin_ppc_fmsubs",
+    "llvm.ppc.fnmadd" => "__builtin_ppc_fnmadd",
+    "llvm.ppc.fnmadds" => "__builtin_ppc_fnmadds",
+    "llvm.ppc.fre" => "__builtin_ppc_fre",
+    "llvm.ppc.fres" => "__builtin_ppc_fres",
+    "llvm.ppc.frsqrte" => "__builtin_ppc_frsqrte",
+    "llvm.ppc.frsqrtes" => "__builtin_ppc_frsqrtes",
+    "llvm.ppc.fsel" => "__builtin_ppc_fsel",
+    "llvm.ppc.fsels" => "__builtin_ppc_fsels",
+    "llvm.ppc.get.texasr" => "__builtin_get_texasr",
+    "llvm.ppc.get.texasru" => "__builtin_get_texasru",
+    "llvm.ppc.get.tfhar" => "__builtin_get_tfhar",
+    "llvm.ppc.get.tfiar" => "__builtin_get_tfiar",
+    "llvm.ppc.icbt" => "__builtin_ppc_icbt",
+    "llvm.ppc.insert.exp" => "__builtin_ppc_insert_exp",
+    "llvm.ppc.iospace.eieio" => "__builtin_ppc_iospace_eieio",
+    "llvm.ppc.iospace.lwsync" => "__builtin_ppc_iospace_lwsync",
+    "llvm.ppc.iospace.sync" => "__builtin_ppc_iospace_sync",
+    "llvm.ppc.isync" => "__builtin_ppc_isync",
+    "llvm.ppc.load4r" => "__builtin_ppc_load4r",
+    "llvm.ppc.load8r" => "__builtin_ppc_load8r",
+    "llvm.ppc.lwsync" => "__builtin_ppc_lwsync",
+    "llvm.ppc.maddhd" => "__builtin_ppc_maddhd",
+    "llvm.ppc.maddhdu" => "__builtin_ppc_maddhdu",
+    "llvm.ppc.maddld" => "__builtin_ppc_maddld",
+    "llvm.ppc.mfmsr" => "__builtin_ppc_mfmsr",
+    "llvm.ppc.mftbu" => "__builtin_ppc_mftbu",
+    "llvm.ppc.mtfsb0" => "__builtin_ppc_mtfsb0",
+    "llvm.ppc.mtfsb1" => "__builtin_ppc_mtfsb1",
+    "llvm.ppc.mtfsfi" => "__builtin_ppc_mtfsfi",
+    "llvm.ppc.mtmsr" => "__builtin_ppc_mtmsr",
+    "llvm.ppc.mulf128.round.to.odd" => "__builtin_mulf128_round_to_odd",
+    "llvm.ppc.mulhd" => "__builtin_ppc_mulhd",
+    "llvm.ppc.mulhdu" => "__builtin_ppc_mulhdu",
+    "llvm.ppc.mulhw" => "__builtin_ppc_mulhw",
+    "llvm.ppc.mulhwu" => "__builtin_ppc_mulhwu",
+    "llvm.ppc.pack.longdouble" => "__builtin_pack_longdouble",
+    "llvm.ppc.pdepd" => "__builtin_pdepd",
+    "llvm.ppc.pextd" => "__builtin_pextd",
+    "llvm.ppc.qpx.qvfabs" => "__builtin_qpx_qvfabs",
+    "llvm.ppc.qpx.qvfadd" => "__builtin_qpx_qvfadd",
+    "llvm.ppc.qpx.qvfadds" => "__builtin_qpx_qvfadds",
+    "llvm.ppc.qpx.qvfcfid" => "__builtin_qpx_qvfcfid",
+    "llvm.ppc.qpx.qvfcfids" => "__builtin_qpx_qvfcfids",
+    "llvm.ppc.qpx.qvfcfidu" => "__builtin_qpx_qvfcfidu",
+    "llvm.ppc.qpx.qvfcfidus" => "__builtin_qpx_qvfcfidus",
+    "llvm.ppc.qpx.qvfcmpeq" => "__builtin_qpx_qvfcmpeq",
+    "llvm.ppc.qpx.qvfcmpgt" => "__builtin_qpx_qvfcmpgt",
+    "llvm.ppc.qpx.qvfcmplt" => "__builtin_qpx_qvfcmplt",
+    "llvm.ppc.qpx.qvfcpsgn" => "__builtin_qpx_qvfcpsgn",
+    "llvm.ppc.qpx.qvfctid" => "__builtin_qpx_qvfctid",
+    "llvm.ppc.qpx.qvfctidu" => "__builtin_qpx_qvfctidu",
+    "llvm.ppc.qpx.qvfctiduz" => "__builtin_qpx_qvfctiduz",
+    "llvm.ppc.qpx.qvfctidz" => "__builtin_qpx_qvfctidz",
+    "llvm.ppc.qpx.qvfctiw" => "__builtin_qpx_qvfctiw",
+    "llvm.ppc.qpx.qvfctiwu" => "__builtin_qpx_qvfctiwu",
+    "llvm.ppc.qpx.qvfctiwuz" => "__builtin_qpx_qvfctiwuz",
+    "llvm.ppc.qpx.qvfctiwz" => "__builtin_qpx_qvfctiwz",
+    "llvm.ppc.qpx.qvflogical" => "__builtin_qpx_qvflogical",
+    "llvm.ppc.qpx.qvfmadd" => "__builtin_qpx_qvfmadd",
+    "llvm.ppc.qpx.qvfmadds" => "__builtin_qpx_qvfmadds",
+    "llvm.ppc.qpx.qvfmsub" => "__builtin_qpx_qvfmsub",
+    "llvm.ppc.qpx.qvfmsubs" => "__builtin_qpx_qvfmsubs",
+    "llvm.ppc.qpx.qvfmul" => "__builtin_qpx_qvfmul",
+    "llvm.ppc.qpx.qvfmuls" => "__builtin_qpx_qvfmuls",
+    "llvm.ppc.qpx.qvfnabs" => "__builtin_qpx_qvfnabs",
+    "llvm.ppc.qpx.qvfneg" => "__builtin_qpx_qvfneg",
+    "llvm.ppc.qpx.qvfnmadd" => "__builtin_qpx_qvfnmadd",
+    "llvm.ppc.qpx.qvfnmadds" => "__builtin_qpx_qvfnmadds",
+    "llvm.ppc.qpx.qvfnmsub" => "__builtin_qpx_qvfnmsub",
+    "llvm.ppc.qpx.qvfnmsubs" => "__builtin_qpx_qvfnmsubs",
+    "llvm.ppc.qpx.qvfperm" => "__builtin_qpx_qvfperm",
+    "llvm.ppc.qpx.qvfre" => "__builtin_qpx_qvfre",
+    "llvm.ppc.qpx.qvfres" => "__builtin_qpx_qvfres",
+    "llvm.ppc.qpx.qvfrim" => "__builtin_qpx_qvfrim",
+    "llvm.ppc.qpx.qvfrin" => "__builtin_qpx_qvfrin",
+    "llvm.ppc.qpx.qvfrip" => "__builtin_qpx_qvfrip",
+    "llvm.ppc.qpx.qvfriz" => "__builtin_qpx_qvfriz",
+    "llvm.ppc.qpx.qvfrsp" => "__builtin_qpx_qvfrsp",
+    "llvm.ppc.qpx.qvfrsqrte" => "__builtin_qpx_qvfrsqrte",
+    "llvm.ppc.qpx.qvfrsqrtes" => "__builtin_qpx_qvfrsqrtes",
+    "llvm.ppc.qpx.qvfsel" => "__builtin_qpx_qvfsel",
+    "llvm.ppc.qpx.qvfsub" => "__builtin_qpx_qvfsub",
+    "llvm.ppc.qpx.qvfsubs" => "__builtin_qpx_qvfsubs",
+    "llvm.ppc.qpx.qvftstnan" => "__builtin_qpx_qvftstnan",
+    "llvm.ppc.qpx.qvfxmadd" => "__builtin_qpx_qvfxmadd",
+    "llvm.ppc.qpx.qvfxmadds" => "__builtin_qpx_qvfxmadds",
+    "llvm.ppc.qpx.qvfxmul" => "__builtin_qpx_qvfxmul",
+    "llvm.ppc.qpx.qvfxmuls" => "__builtin_qpx_qvfxmuls",
+    "llvm.ppc.qpx.qvfxxcpnmadd" => "__builtin_qpx_qvfxxcpnmadd",
+    "llvm.ppc.qpx.qvfxxcpnmadds" => "__builtin_qpx_qvfxxcpnmadds",
+    "llvm.ppc.qpx.qvfxxmadd" => "__builtin_qpx_qvfxxmadd",
+    "llvm.ppc.qpx.qvfxxmadds" => "__builtin_qpx_qvfxxmadds",
+    "llvm.ppc.qpx.qvfxxnpmadd" => "__builtin_qpx_qvfxxnpmadd",
+    "llvm.ppc.qpx.qvfxxnpmadds" => "__builtin_qpx_qvfxxnpmadds",
+    "llvm.ppc.qpx.qvgpci" => "__builtin_qpx_qvgpci",
+    "llvm.ppc.qpx.qvlfcd" => "__builtin_qpx_qvlfcd",
+    "llvm.ppc.qpx.qvlfcda" => "__builtin_qpx_qvlfcda",
+    "llvm.ppc.qpx.qvlfcs" => "__builtin_qpx_qvlfcs",
+    "llvm.ppc.qpx.qvlfcsa" => "__builtin_qpx_qvlfcsa",
+    "llvm.ppc.qpx.qvlfd" => "__builtin_qpx_qvlfd",
+    "llvm.ppc.qpx.qvlfda" => "__builtin_qpx_qvlfda",
+    "llvm.ppc.qpx.qvlfiwa" => "__builtin_qpx_qvlfiwa",
+    "llvm.ppc.qpx.qvlfiwaa" => "__builtin_qpx_qvlfiwaa",
+    "llvm.ppc.qpx.qvlfiwz" => "__builtin_qpx_qvlfiwz",
+    "llvm.ppc.qpx.qvlfiwza" => "__builtin_qpx_qvlfiwza",
+    "llvm.ppc.qpx.qvlfs" => "__builtin_qpx_qvlfs",
+    "llvm.ppc.qpx.qvlfsa" => "__builtin_qpx_qvlfsa",
+    "llvm.ppc.qpx.qvlpcld" => "__builtin_qpx_qvlpcld",
+    "llvm.ppc.qpx.qvlpcls" => "__builtin_qpx_qvlpcls",
+    "llvm.ppc.qpx.qvlpcrd" => "__builtin_qpx_qvlpcrd",
+    "llvm.ppc.qpx.qvlpcrs" => "__builtin_qpx_qvlpcrs",
+    "llvm.ppc.qpx.qvstfcd" => "__builtin_qpx_qvstfcd",
+    "llvm.ppc.qpx.qvstfcda" => "__builtin_qpx_qvstfcda",
+    "llvm.ppc.qpx.qvstfcs" => "__builtin_qpx_qvstfcs",
+    "llvm.ppc.qpx.qvstfcsa" => "__builtin_qpx_qvstfcsa",
+    "llvm.ppc.qpx.qvstfd" => "__builtin_qpx_qvstfd",
+    "llvm.ppc.qpx.qvstfda" => "__builtin_qpx_qvstfda",
+    "llvm.ppc.qpx.qvstfiw" => "__builtin_qpx_qvstfiw",
+    "llvm.ppc.qpx.qvstfiwa" => "__builtin_qpx_qvstfiwa",
+    "llvm.ppc.qpx.qvstfs" => "__builtin_qpx_qvstfs",
+    "llvm.ppc.qpx.qvstfsa" => "__builtin_qpx_qvstfsa",
+    "llvm.ppc.readflm" => "__builtin_readflm",
+    "llvm.ppc.scalar.extract.expq" => "__builtin_vsx_scalar_extract_expq",
+    "llvm.ppc.scalar.insert.exp.qp" => "__builtin_vsx_scalar_insert_exp_qp",
+    "llvm.ppc.set.texasr" => "__builtin_set_texasr",
+    "llvm.ppc.set.texasru" => "__builtin_set_texasru",
+    "llvm.ppc.set.tfhar" => "__builtin_set_tfhar",
+    "llvm.ppc.set.tfiar" => "__builtin_set_tfiar",
+    "llvm.ppc.setb" => "__builtin_ppc_setb",
+    "llvm.ppc.setflm" => "__builtin_setflm",
+    "llvm.ppc.setrnd" => "__builtin_setrnd",
+    "llvm.ppc.sqrtf128.round.to.odd" => "__builtin_sqrtf128_round_to_odd",
+    "llvm.ppc.stbcx" => "__builtin_ppc_stbcx",
+    "llvm.ppc.stdcx" => "__builtin_ppc_stdcx",
+    "llvm.ppc.stfiw" => "__builtin_ppc_stfiw",
+    "llvm.ppc.store2r" => "__builtin_ppc_store2r",
+    "llvm.ppc.store4r" => "__builtin_ppc_store4r",
+    "llvm.ppc.store8r" => "__builtin_ppc_store8r",
+    "llvm.ppc.stwcx" => "__builtin_ppc_stwcx",
+    "llvm.ppc.subf128.round.to.odd" => "__builtin_subf128_round_to_odd",
+    "llvm.ppc.sync" => "__builtin_ppc_sync",
+    "llvm.ppc.tabort" => "__builtin_tabort",
+    "llvm.ppc.tabortdc" => "__builtin_tabortdc",
+    "llvm.ppc.tabortdci" => "__builtin_tabortdci",
+    "llvm.ppc.tabortwc" => "__builtin_tabortwc",
+    "llvm.ppc.tabortwci" => "__builtin_tabortwci",
+    "llvm.ppc.tbegin" => "__builtin_tbegin",
+    "llvm.ppc.tcheck" => "__builtin_tcheck",
+    "llvm.ppc.tdw" => "__builtin_ppc_tdw",
+    "llvm.ppc.tend" => "__builtin_tend",
+    "llvm.ppc.tendall" => "__builtin_tendall",
+    "llvm.ppc.trap" => "__builtin_ppc_trap",
+    "llvm.ppc.trapd" => "__builtin_ppc_trapd",
+    "llvm.ppc.trechkpt" => "__builtin_trechkpt",
+    "llvm.ppc.treclaim" => "__builtin_treclaim",
+    "llvm.ppc.tresume" => "__builtin_tresume",
+    "llvm.ppc.truncf128.round.to.odd" => "__builtin_truncf128_round_to_odd",
+    "llvm.ppc.tsr" => "__builtin_tsr",
+    "llvm.ppc.tsuspend" => "__builtin_tsuspend",
+    "llvm.ppc.ttest" => "__builtin_ttest",
+    "llvm.ppc.tw" => "__builtin_ppc_tw",
+    "llvm.ppc.unpack.longdouble" => "__builtin_unpack_longdouble",
+    "llvm.ppc.vsx.xsmaxdp" => "__builtin_vsx_xsmaxdp",
+    "llvm.ppc.vsx.xsmindp" => "__builtin_vsx_xsmindp",
+    "llvm.ppc.vsx.xvcmpeqdp" => "__builtin_vsx_xvcmpeqdp",
+    "llvm.ppc.vsx.xvcmpeqdp.p" => "__builtin_vsx_xvcmpeqdp_p",
+    "llvm.ppc.vsx.xvcmpeqsp" => "__builtin_vsx_xvcmpeqsp",
+    "llvm.ppc.vsx.xvcmpeqsp.p" => "__builtin_vsx_xvcmpeqsp_p",
+    "llvm.ppc.vsx.xvcmpgedp" => "__builtin_vsx_xvcmpgedp",
+    "llvm.ppc.vsx.xvcmpgedp.p" => "__builtin_vsx_xvcmpgedp_p",
+    "llvm.ppc.vsx.xvcmpgesp" => "__builtin_vsx_xvcmpgesp",
+    "llvm.ppc.vsx.xvcmpgesp.p" => "__builtin_vsx_xvcmpgesp_p",
+    "llvm.ppc.vsx.xvcmpgtdp" => "__builtin_vsx_xvcmpgtdp",
+    "llvm.ppc.vsx.xvcmpgtdp.p" => "__builtin_vsx_xvcmpgtdp_p",
+    "llvm.ppc.vsx.xvcmpgtsp" => "__builtin_vsx_xvcmpgtsp",
+    "llvm.ppc.vsx.xvcmpgtsp.p" => "__builtin_vsx_xvcmpgtsp_p",
+    "llvm.ppc.vsx.xvdivdp" => "__builtin_vsx_xvdivdp",
+    "llvm.ppc.vsx.xvdivsp" => "__builtin_vsx_xvdivsp",
+    "llvm.ppc.vsx.xvmaxdp" => "__builtin_vsx_xvmaxdp",
+    "llvm.ppc.vsx.xvmaxsp" => "__builtin_vsx_xvmaxsp",
+    "llvm.ppc.vsx.xvmindp" => "__builtin_vsx_xvmindp",
+    "llvm.ppc.vsx.xvminsp" => "__builtin_vsx_xvminsp",
+    "llvm.ppc.vsx.xvredp" => "__builtin_vsx_xvredp",
+    "llvm.ppc.vsx.xvresp" => "__builtin_vsx_xvresp",
+    "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp",
+    "llvm.ppc.vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp",
+    "llvm.ppc.vsx.xxblendvb" => "__builtin_vsx_xxblendvb",
+    "llvm.ppc.vsx.xxblendvd" => "__builtin_vsx_xxblendvd",
+    "llvm.ppc.vsx.xxblendvh" => "__builtin_vsx_xxblendvh",
+    "llvm.ppc.vsx.xxblendvw" => "__builtin_vsx_xxblendvw",
+    "llvm.ppc.vsx.xxleqv" => "__builtin_vsx_xxleqv",
+    "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx",
+    // ptx
+    "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync",
+    "llvm.ptx.read.clock" => "__builtin_ptx_read_clock",
+    "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64",
+    "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid",
+    "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid",
+    "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq",
+    "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge",
+    "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt",
+    "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le",
+    "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt",
+    "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid",
+    "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid",
+    "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0",
+    "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1",
+    "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2",
+    "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3",
+    "llvm.ptx.read.smid" => "__builtin_ptx_read_smid",
+    "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid",
+    // s390
+    "llvm.s390.efpc" => "__builtin_s390_efpc",
+    "llvm.s390.etnd" => "__builtin_tx_nesting_depth",
+    "llvm.s390.lcbb" => "__builtin_s390_lcbb",
+    "llvm.s390.ppa.txassist" => "__builtin_tx_assist",
+    "llvm.s390.sfpc" => "__builtin_s390_sfpc",
+    "llvm.s390.tend" => "__builtin_tend",
+    "llvm.s390.vcfn" => "__builtin_s390_vcfn",
+    "llvm.s390.vclfnhs" => "__builtin_s390_vclfnhs",
+    "llvm.s390.vclfnls" => "__builtin_s390_vclfnls",
+    "llvm.s390.vcnf" => "__builtin_s390_vcnf",
+    "llvm.s390.vcrnfs" => "__builtin_s390_vcrnfs",
+    "llvm.s390.vlbb" => "__builtin_s390_vlbb",
+    "llvm.s390.vll" => "__builtin_s390_vll",
+    "llvm.s390.vlrl" => "__builtin_s390_vlrl",
+    "llvm.s390.vmslg" => "__builtin_s390_vmslg",
+    "llvm.s390.vpdi" => "__builtin_s390_vpdi",
+    "llvm.s390.vperm" => "__builtin_s390_vperm",
+    "llvm.s390.vsld" => "__builtin_s390_vsld",
+    "llvm.s390.vsldb" => "__builtin_s390_vsldb",
+    "llvm.s390.vsrd" => "__builtin_s390_vsrd",
+    "llvm.s390.vstl" => "__builtin_s390_vstl",
+    "llvm.s390.vstrl" => "__builtin_s390_vstrl",
+    // ve
+    "llvm.ve.vl.extract.vm512l" => "__builtin_ve_vl_extract_vm512l",
+    "llvm.ve.vl.extract.vm512u" => "__builtin_ve_vl_extract_vm512u",
+    "llvm.ve.vl.insert.vm512l" => "__builtin_ve_vl_insert_vm512l",
+    "llvm.ve.vl.insert.vm512u" => "__builtin_ve_vl_insert_vm512u",
+    "llvm.ve.vl.pack.f32a" => "__builtin_ve_vl_pack_f32a",
+    "llvm.ve.vl.pack.f32p" => "__builtin_ve_vl_pack_f32p",
+    // x86
+    "llvm.x86.3dnow.pavgusb" => "__builtin_ia32_pavgusb",
+    "llvm.x86.3dnow.pf2id" => "__builtin_ia32_pf2id",
+    "llvm.x86.3dnow.pfacc" => "__builtin_ia32_pfacc",
+    "llvm.x86.3dnow.pfadd" => "__builtin_ia32_pfadd",
+    "llvm.x86.3dnow.pfcmpeq" => "__builtin_ia32_pfcmpeq",
+    "llvm.x86.3dnow.pfcmpge" => "__builtin_ia32_pfcmpge",
+    "llvm.x86.3dnow.pfcmpgt" => "__builtin_ia32_pfcmpgt",
+    "llvm.x86.3dnow.pfmax" => "__builtin_ia32_pfmax",
+    "llvm.x86.3dnow.pfmin" => "__builtin_ia32_pfmin",
+    "llvm.x86.3dnow.pfmul" => "__builtin_ia32_pfmul",
+    "llvm.x86.3dnow.pfrcp" => "__builtin_ia32_pfrcp",
+    "llvm.x86.3dnow.pfrcpit1" => "__builtin_ia32_pfrcpit1",
+    "llvm.x86.3dnow.pfrcpit2" => "__builtin_ia32_pfrcpit2",
+    "llvm.x86.3dnow.pfrsqit1" => "__builtin_ia32_pfrsqit1",
+    "llvm.x86.3dnow.pfrsqrt" => "__builtin_ia32_pfrsqrt",
+    "llvm.x86.3dnow.pfsub" => "__builtin_ia32_pfsub",
+    "llvm.x86.3dnow.pfsubr" => "__builtin_ia32_pfsubr",
+    "llvm.x86.3dnow.pi2fd" => "__builtin_ia32_pi2fd",
+    "llvm.x86.3dnow.pmulhrw" => "__builtin_ia32_pmulhrw",
+    "llvm.x86.3dnowa.pf2iw" => "__builtin_ia32_pf2iw",
+    "llvm.x86.3dnowa.pfnacc" => "__builtin_ia32_pfnacc",
+    "llvm.x86.3dnowa.pfpnacc" => "__builtin_ia32_pfpnacc",
+    "llvm.x86.3dnowa.pi2fw" => "__builtin_ia32_pi2fw",
+    "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32",
+    "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64",
+    "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32",
+    "llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64",
+    "llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128",
+    "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_aesdec256",
+    "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_aesdec512",
+    "llvm.x86.aesni.aesdeclast" => "__builtin_ia32_aesdeclast128",
+    "llvm.x86.aesni.aesdeclast.256" => "__builtin_ia32_aesdeclast256",
+    "llvm.x86.aesni.aesdeclast.512" => "__builtin_ia32_aesdeclast512",
+    "llvm.x86.aesni.aesenc" => "__builtin_ia32_aesenc128",
+    "llvm.x86.aesni.aesenc.256" => "__builtin_ia32_aesenc256",
+    "llvm.x86.aesni.aesenc.512" => "__builtin_ia32_aesenc512",
+    "llvm.x86.aesni.aesenclast" => "__builtin_ia32_aesenclast128",
+    "llvm.x86.aesni.aesenclast.256" => "__builtin_ia32_aesenclast256",
+    "llvm.x86.aesni.aesenclast.512" => "__builtin_ia32_aesenclast512",
+    "llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128",
+    "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128",
+    "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256",
+    "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256",
+    "llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256",
+    "llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256",
+    "llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256",
+    "llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256",
+    "llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256",
+    "llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256",
+    "llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256",
+    "llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256",
+    "llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256",
+    "llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256",
+    "llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256",
+    "llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256",
+    "llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256",
+    "llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256",
+    "llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256",
+    "llvm.x86.avx.hadd.pd.256" => "__builtin_ia32_haddpd256",
+    "llvm.x86.avx.hadd.ps.256" => "__builtin_ia32_haddps256",
+    "llvm.x86.avx.hsub.pd.256" => "__builtin_ia32_hsubpd256",
+    "llvm.x86.avx.hsub.ps.256" => "__builtin_ia32_hsubps256",
+    "llvm.x86.avx.ldu.dq.256" => "__builtin_ia32_lddqu256",
+    "llvm.x86.avx.maskload.pd" => "__builtin_ia32_maskloadpd",
+    "llvm.x86.avx.maskload.pd.256" => "__builtin_ia32_maskloadpd256",
+    "llvm.x86.avx.maskload.ps" => "__builtin_ia32_maskloadps",
+    "llvm.x86.avx.maskload.ps.256" => "__builtin_ia32_maskloadps256",
+    "llvm.x86.avx.maskstore.pd" => "__builtin_ia32_maskstorepd",
+    "llvm.x86.avx.maskstore.pd.256" => "__builtin_ia32_maskstorepd256",
+    "llvm.x86.avx.maskstore.ps" => "__builtin_ia32_maskstoreps",
+    "llvm.x86.avx.maskstore.ps.256" => "__builtin_ia32_maskstoreps256",
+    "llvm.x86.avx.max.pd.256" => "__builtin_ia32_maxpd256",
+    "llvm.x86.avx.max.ps.256" => "__builtin_ia32_maxps256",
+    "llvm.x86.avx.min.pd.256" => "__builtin_ia32_minpd256",
+    "llvm.x86.avx.min.ps.256" => "__builtin_ia32_minps256",
+    "llvm.x86.avx.movmsk.pd.256" => "__builtin_ia32_movmskpd256",
+    "llvm.x86.avx.movmsk.ps.256" => "__builtin_ia32_movmskps256",
+    "llvm.x86.avx.ptestc.256" => "__builtin_ia32_ptestc256",
+    "llvm.x86.avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256",
+    "llvm.x86.avx.ptestz.256" => "__builtin_ia32_ptestz256",
+    "llvm.x86.avx.rcp.ps.256" => "__builtin_ia32_rcpps256",
+    "llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256",
+    "llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256",
+    "llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256",
+    "llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256",
+    "llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256",
+    "llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256",
+    "llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256",
+    "llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256",
+    "llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256",
+    "llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256",
+    "llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256",
+    "llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256",
+    "llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256",
+    "llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256",
+    "llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256",
+    "llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256",
+    "llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256",
+    "llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256",
+    "llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256",
+    "llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd",
+    "llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256",
+    "llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps",
+    "llvm.x86.avx.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256",
+    "llvm.x86.avx.vtestc.pd" => "__builtin_ia32_vtestcpd",
+    "llvm.x86.avx.vtestc.pd.256" => "__builtin_ia32_vtestcpd256",
+    "llvm.x86.avx.vtestc.ps" => "__builtin_ia32_vtestcps",
+    "llvm.x86.avx.vtestc.ps.256" => "__builtin_ia32_vtestcps256",
+    "llvm.x86.avx.vtestnzc.pd" => "__builtin_ia32_vtestnzcpd",
+    "llvm.x86.avx.vtestnzc.pd.256" => "__builtin_ia32_vtestnzcpd256",
+    "llvm.x86.avx.vtestnzc.ps" => "__builtin_ia32_vtestnzcps",
+    "llvm.x86.avx.vtestnzc.ps.256" => "__builtin_ia32_vtestnzcps256",
+    "llvm.x86.avx.vtestz.pd" => "__builtin_ia32_vtestzpd",
+    "llvm.x86.avx.vtestz.pd.256" => "__builtin_ia32_vtestzpd256",
+    "llvm.x86.avx.vtestz.ps" => "__builtin_ia32_vtestzps",
+    "llvm.x86.avx.vtestz.ps.256" => "__builtin_ia32_vtestzps256",
+    "llvm.x86.avx.vzeroall" => "__builtin_ia32_vzeroall",
+    "llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper",
+    "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d",
+    "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256",
+    "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd",
+    "llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256",
+    "llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps",
+    "llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256",
+    "llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q",
+    "llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256",
+    "llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d",
+    "llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256",
+    "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd",
+    "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256",
+    "llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps",
+    "llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256",
+    "llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q",
+    "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256",
+    "llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd",
+    "llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256",
+    "llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq",
+    "llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256",
+    "llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored",
+    "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256",
+    "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq",
+    "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256",
+    "llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256",
+    "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256",
+    "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256",
+    "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256",
+    "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256",
+    "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256",
+    "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256",
+    "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256",
+    "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256",
+    "llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256",
+    "llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256",
+    "llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256",
+    "llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256",
+    "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256",
+    "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256",
+    "llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128",
+    "llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256",
+    "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256",
+    "llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256",
+    "llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128",
+    "llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256",
+    "llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128",
+    "llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256",
+    "llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128",
+    "llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256",
+    "llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128",
+    "llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256",
+    "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256",
+    "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256",
+    "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256",
+    "llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256",
+    "llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256",
+    "llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256",
+    "llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256",
+    "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256",
+    "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256",
+    "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256",
+    "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256",
+    "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256",
+    "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256",
+    "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256",
+    "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256",
+    "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256",
+    "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256",
+    "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256",
+    "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256",
+    "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256",
+    "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256",
+    "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256",
+    "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256",
+    "llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256",
+    "llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256",
+    "llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256",
+    "llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256",
+    "llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256",
+    "llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256",
+    "llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256",
+    "llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256",
+    "llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256",
+    "llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256",
+    "llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256",
+    "llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256",
+    "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256",
+    "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256",
+    "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256",
+    "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256",
+    "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256",
+    "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256",
+    "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256",
+    "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256",
+    "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256",
+    "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256",
+    "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256",
+    "llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256",
+    "llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift",
+    "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256",
+    "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256",
+    "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256",
+    "llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256",
+    "llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256",
+    "llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si",
+    "llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si",
+    "llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di",
+    "llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di",
+    "llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256",
+    "llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256",
+    "llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256",
+    "llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256",
+    "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si",
+    "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si",
+    "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256",
+    "llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256",
+    "llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift",
+    "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256",
+    "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256",
+    "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256",
+    "llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256",
+    "llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256",
+    "llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si",
+    "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si",
+    "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di",
+    "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di",
+    "llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256",
+    "llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256",
+    "llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256",
+    "llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256",
+    "llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256",
+    "llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps",
+    "llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256",
+    "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256",
+    "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256",
+    "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256",
+    "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512",
+    "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512",
+    "llvm.x86.avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128",
+    "llvm.x86.avx512.broadcastmb.256" => "__builtin_ia32_broadcastmb256",
+    "llvm.x86.avx512.broadcastmb.512" => "__builtin_ia32_broadcastmb512",
+    "llvm.x86.avx512.broadcastmw.128" => "__builtin_ia32_broadcastmw128",
+    "llvm.x86.avx512.broadcastmw.256" => "__builtin_ia32_broadcastmw256",
+    "llvm.x86.avx512.broadcastmw.512" => "__builtin_ia32_broadcastmw512",
+    "llvm.x86.avx512.conflict.d.128" => "__builtin_ia32_vpconflictsi_128",
+    "llvm.x86.avx512.conflict.d.256" => "__builtin_ia32_vpconflictsi_256",
+    "llvm.x86.avx512.conflict.d.512" => "__builtin_ia32_vpconflictsi_512",
+    "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128",
+    "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256",
+    "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512",
+    "llvm.x86.avx512.cvtb2mask.128" => "__builtin_ia32_cvtb2mask128",
+    "llvm.x86.avx512.cvtb2mask.256" => "__builtin_ia32_cvtb2mask256",
+    "llvm.x86.avx512.cvtb2mask.512" => "__builtin_ia32_cvtb2mask512",
+    "llvm.x86.avx512.cvtd2mask.128" => "__builtin_ia32_cvtd2mask128",
+    "llvm.x86.avx512.cvtd2mask.256" => "__builtin_ia32_cvtd2mask256",
+    "llvm.x86.avx512.cvtd2mask.512" => "__builtin_ia32_cvtd2mask512",
+    "llvm.x86.avx512.cvtmask2b.128" => "__builtin_ia32_cvtmask2b128",
+    "llvm.x86.avx512.cvtmask2b.256" => "__builtin_ia32_cvtmask2b256",
+    "llvm.x86.avx512.cvtmask2b.512" => "__builtin_ia32_cvtmask2b512",
+    "llvm.x86.avx512.cvtmask2d.128" => "__builtin_ia32_cvtmask2d128",
+    "llvm.x86.avx512.cvtmask2d.256" => "__builtin_ia32_cvtmask2d256",
+    "llvm.x86.avx512.cvtmask2d.512" => "__builtin_ia32_cvtmask2d512",
+    "llvm.x86.avx512.cvtmask2q.128" => "__builtin_ia32_cvtmask2q128",
+    "llvm.x86.avx512.cvtmask2q.256" => "__builtin_ia32_cvtmask2q256",
+    "llvm.x86.avx512.cvtmask2q.512" => "__builtin_ia32_cvtmask2q512",
+    "llvm.x86.avx512.cvtmask2w.128" => "__builtin_ia32_cvtmask2w128",
+    "llvm.x86.avx512.cvtmask2w.256" => "__builtin_ia32_cvtmask2w256",
+    "llvm.x86.avx512.cvtmask2w.512" => "__builtin_ia32_cvtmask2w512",
+    "llvm.x86.avx512.cvtq2mask.128" => "__builtin_ia32_cvtq2mask128",
+    "llvm.x86.avx512.cvtq2mask.256" => "__builtin_ia32_cvtq2mask256",
+    "llvm.x86.avx512.cvtq2mask.512" => "__builtin_ia32_cvtq2mask512",
+    "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi",
+    "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64",
+    "llvm.x86.avx512.cvtsi2sd32" => "__builtin_ia32_cvtsi2sd32",
+    "llvm.x86.avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64",
+    "llvm.x86.avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32",
+    "llvm.x86.avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64",
+    "llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi",
+    "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64",
+    "llvm.x86.avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32",
+    "llvm.x86.avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64",
+    "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32",
+    // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi",
+    "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64",
+    // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64",
+    "llvm.x86.avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32",
+    "llvm.x86.avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64",
+    "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32",
+    // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi",
+    "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64",
+    // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64",
+    "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd",
+    // [DUPLICATE]: "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd32",
+    "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32",
+    // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss",
+    "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64",
+    // [DUPLICATE]: "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd",
+    "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64",
+    // [DUPLICATE]: "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss",
+    "llvm.x86.avx512.cvtw2mask.128" => "__builtin_ia32_cvtw2mask128",
+    "llvm.x86.avx512.cvtw2mask.256" => "__builtin_ia32_cvtw2mask256",
+    "llvm.x86.avx512.cvtw2mask.512" => "__builtin_ia32_cvtw2mask512",
+    "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128",
+    "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256",
+    "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512",
+    "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512",
+    "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512",
+    "llvm.x86.avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask",
+    "llvm.x86.avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask",
+    "llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df",
+    "llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si",
+    "llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di",
+    "llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf",
+    "llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df",
+    "llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si",
+    "llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di",
+    "llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf",
+    "llvm.x86.avx512.gather3div2.df" => "__builtin_ia32_gather3div2df",
+    "llvm.x86.avx512.gather3div2.di" => "__builtin_ia32_gather3div2di",
+    "llvm.x86.avx512.gather3div4.df" => "__builtin_ia32_gather3div4df",
+    "llvm.x86.avx512.gather3div4.di" => "__builtin_ia32_gather3div4di",
+    "llvm.x86.avx512.gather3div4.sf" => "__builtin_ia32_gather3div4sf",
+    "llvm.x86.avx512.gather3div4.si" => "__builtin_ia32_gather3div4si",
+    "llvm.x86.avx512.gather3div8.sf" => "__builtin_ia32_gather3div8sf",
+    "llvm.x86.avx512.gather3div8.si" => "__builtin_ia32_gather3div8si",
+    "llvm.x86.avx512.gather3siv2.df" => "__builtin_ia32_gather3siv2df",
+    "llvm.x86.avx512.gather3siv2.di" => "__builtin_ia32_gather3siv2di",
+    "llvm.x86.avx512.gather3siv4.df" => "__builtin_ia32_gather3siv4df",
+    "llvm.x86.avx512.gather3siv4.di" => "__builtin_ia32_gather3siv4di",
+    "llvm.x86.avx512.gather3siv4.sf" => "__builtin_ia32_gather3siv4sf",
+    "llvm.x86.avx512.gather3siv4.si" => "__builtin_ia32_gather3siv4si",
+    "llvm.x86.avx512.gather3siv8.sf" => "__builtin_ia32_gather3siv8sf",
+    "llvm.x86.avx512.gather3siv8.si" => "__builtin_ia32_gather3siv8si",
+    "llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd",
+    "llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps",
+    "llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd",
+    "llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps",
+    "llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi",
+    "llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi",
+    "llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi",
+    "llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi",
+    "llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi",
+    "llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi",
+    "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi",
+    "llvm.x86.avx512.kunpck.dq" => "__builtin_ia32_kunpckdi",
+    "llvm.x86.avx512.kunpck.wd" => "__builtin_ia32_kunpcksi",
+    "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi",
+    "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi",
+    "llvm.x86.avx512.mask.add.pd.128" => "__builtin_ia32_addpd128_mask",
+    "llvm.x86.avx512.mask.add.pd.256" => "__builtin_ia32_addpd256_mask",
+    "llvm.x86.avx512.mask.add.pd.512" => "__builtin_ia32_addpd512_mask",
+    "llvm.x86.avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask",
+    "llvm.x86.avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask",
+    "llvm.x86.avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask",
+    "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask",
+    "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask",
+    "llvm.x86.avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask",
+    "llvm.x86.avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask",
+    "llvm.x86.avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask",
+    "llvm.x86.avx512.mask.and.ps.128" => "__builtin_ia32_andps128_mask",
+    "llvm.x86.avx512.mask.and.ps.256" => "__builtin_ia32_andps256_mask",
+    "llvm.x86.avx512.mask.and.ps.512" => "__builtin_ia32_andps512_mask",
+    "llvm.x86.avx512.mask.andn.pd.128" => "__builtin_ia32_andnpd128_mask",
+    "llvm.x86.avx512.mask.andn.pd.256" => "__builtin_ia32_andnpd256_mask",
+    "llvm.x86.avx512.mask.andn.pd.512" => "__builtin_ia32_andnpd512_mask",
+    "llvm.x86.avx512.mask.andn.ps.128" => "__builtin_ia32_andnps128_mask",
+    "llvm.x86.avx512.mask.andn.ps.256" => "__builtin_ia32_andnps256_mask",
+    "llvm.x86.avx512.mask.andn.ps.512" => "__builtin_ia32_andnps512_mask",
+    "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask",
+    "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask",
+    "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask",
+    "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask",
+    "llvm.x86.avx512.mask.broadcastf32x2.256" => "__builtin_ia32_broadcastf32x2_256_mask",
+    "llvm.x86.avx512.mask.broadcastf32x2.512" => "__builtin_ia32_broadcastf32x2_512_mask",
+    "llvm.x86.avx512.mask.broadcastf32x4.256" => "__builtin_ia32_broadcastf32x4_256_mask",
+    "llvm.x86.avx512.mask.broadcastf32x4.512" => "__builtin_ia32_broadcastf32x4_512",
+    "llvm.x86.avx512.mask.broadcastf32x8.512" => "__builtin_ia32_broadcastf32x8_512_mask",
+    "llvm.x86.avx512.mask.broadcastf64x2.256" => "__builtin_ia32_broadcastf64x2_256_mask",
+    "llvm.x86.avx512.mask.broadcastf64x2.512" => "__builtin_ia32_broadcastf64x2_512_mask",
+    "llvm.x86.avx512.mask.broadcastf64x4.512" => "__builtin_ia32_broadcastf64x4_512",
+    "llvm.x86.avx512.mask.broadcasti32x2.128" => "__builtin_ia32_broadcasti32x2_128_mask",
+    "llvm.x86.avx512.mask.broadcasti32x2.256" => "__builtin_ia32_broadcasti32x2_256_mask",
+    "llvm.x86.avx512.mask.broadcasti32x2.512" => "__builtin_ia32_broadcasti32x2_512_mask",
+    "llvm.x86.avx512.mask.broadcasti32x4.256" => "__builtin_ia32_broadcasti32x4_256_mask",
+    "llvm.x86.avx512.mask.broadcasti32x4.512" => "__builtin_ia32_broadcasti32x4_512",
+    "llvm.x86.avx512.mask.broadcasti32x8.512" => "__builtin_ia32_broadcasti32x8_512_mask",
+    "llvm.x86.avx512.mask.broadcasti64x2.256" => "__builtin_ia32_broadcasti64x2_256_mask",
+    "llvm.x86.avx512.mask.broadcasti64x2.512" => "__builtin_ia32_broadcasti64x2_512_mask",
+    "llvm.x86.avx512.mask.broadcasti64x4.512" => "__builtin_ia32_broadcasti64x4_512",
+    "llvm.x86.avx512.mask.cmp.pd.128" => "__builtin_ia32_cmppd128_mask",
+    "llvm.x86.avx512.mask.cmp.pd.256" => "__builtin_ia32_cmppd256_mask",
+    "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask",
+    "llvm.x86.avx512.mask.cmp.ps.128" => "__builtin_ia32_cmpps128_mask",
+    "llvm.x86.avx512.mask.cmp.ps.256" => "__builtin_ia32_cmpps256_mask",
+    "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask",
+    "llvm.x86.avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask",
+    "llvm.x86.avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask",
+    "llvm.x86.avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask",
+    "llvm.x86.avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask",
+    "llvm.x86.avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask",
+    "llvm.x86.avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask",
+    "llvm.x86.avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask",
+    "llvm.x86.avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask",
+    "llvm.x86.avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask",
+    "llvm.x86.avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask",
+    "llvm.x86.avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask",
+    "llvm.x86.avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask",
+    "llvm.x86.avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask",
+    "llvm.x86.avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask",
+    "llvm.x86.avx512.mask.compress.store.d.128" => "__builtin_ia32_compressstoresi128_mask",
+    "llvm.x86.avx512.mask.compress.store.d.256" => "__builtin_ia32_compressstoresi256_mask",
+    "llvm.x86.avx512.mask.compress.store.d.512" => "__builtin_ia32_compressstoresi512_mask",
+    "llvm.x86.avx512.mask.compress.store.pd.128" => "__builtin_ia32_compressstoredf128_mask",
+    "llvm.x86.avx512.mask.compress.store.pd.256" => "__builtin_ia32_compressstoredf256_mask",
+    "llvm.x86.avx512.mask.compress.store.pd.512" => "__builtin_ia32_compressstoredf512_mask",
+    "llvm.x86.avx512.mask.compress.store.ps.128" => "__builtin_ia32_compressstoresf128_mask",
+    "llvm.x86.avx512.mask.compress.store.ps.256" => "__builtin_ia32_compressstoresf256_mask",
+    "llvm.x86.avx512.mask.compress.store.ps.512" => "__builtin_ia32_compressstoresf512_mask",
+    "llvm.x86.avx512.mask.compress.store.q.128" => "__builtin_ia32_compressstoredi128_mask",
+    "llvm.x86.avx512.mask.compress.store.q.256" => "__builtin_ia32_compressstoredi256_mask",
+    "llvm.x86.avx512.mask.compress.store.q.512" => "__builtin_ia32_compressstoredi512_mask",
+    "llvm.x86.avx512.mask.conflict.d.128" => "__builtin_ia32_vpconflictsi_128_mask",
+    "llvm.x86.avx512.mask.conflict.d.256" => "__builtin_ia32_vpconflictsi_256_mask",
+    "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask",
+    "llvm.x86.avx512.mask.conflict.q.128" => "__builtin_ia32_vpconflictdi_128_mask",
+    "llvm.x86.avx512.mask.conflict.q.256" => "__builtin_ia32_vpconflictdi_256_mask",
+    "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask",
+    "llvm.x86.avx512.mask.cvtdq2pd.128" => "__builtin_ia32_cvtdq2pd128_mask",
+    "llvm.x86.avx512.mask.cvtdq2pd.256" => "__builtin_ia32_cvtdq2pd256_mask",
+    "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask",
+    "llvm.x86.avx512.mask.cvtdq2ps.128" => "__builtin_ia32_cvtdq2ps128_mask",
+    "llvm.x86.avx512.mask.cvtdq2ps.256" => "__builtin_ia32_cvtdq2ps256_mask",
+    "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask",
+    "llvm.x86.avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask",
+    "llvm.x86.avx512.mask.cvtpd2dq.256" => "__builtin_ia32_cvtpd2dq256_mask",
+    "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask",
+    "llvm.x86.avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask",
+    "llvm.x86.avx512.mask.cvtpd2ps.256" => "__builtin_ia32_cvtpd2ps256_mask",
+    "llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask",
+    "llvm.x86.avx512.mask.cvtpd2qq.128" => "__builtin_ia32_cvtpd2qq128_mask",
+    "llvm.x86.avx512.mask.cvtpd2qq.256" => "__builtin_ia32_cvtpd2qq256_mask",
+    "llvm.x86.avx512.mask.cvtpd2qq.512" => "__builtin_ia32_cvtpd2qq512_mask",
+    "llvm.x86.avx512.mask.cvtpd2udq.128" => "__builtin_ia32_cvtpd2udq128_mask",
+    "llvm.x86.avx512.mask.cvtpd2udq.256" => "__builtin_ia32_cvtpd2udq256_mask",
+    "llvm.x86.avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask",
+    "llvm.x86.avx512.mask.cvtpd2uqq.128" => "__builtin_ia32_cvtpd2uqq128_mask",
+    "llvm.x86.avx512.mask.cvtpd2uqq.256" => "__builtin_ia32_cvtpd2uqq256_mask",
+    "llvm.x86.avx512.mask.cvtpd2uqq.512" => "__builtin_ia32_cvtpd2uqq512_mask",
+    "llvm.x86.avx512.mask.cvtps2dq.128" => "__builtin_ia32_cvtps2dq128_mask",
+    "llvm.x86.avx512.mask.cvtps2dq.256" => "__builtin_ia32_cvtps2dq256_mask",
+    "llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask",
+    "llvm.x86.avx512.mask.cvtps2pd.128" => "__builtin_ia32_cvtps2pd128_mask",
+    "llvm.x86.avx512.mask.cvtps2pd.256" => "__builtin_ia32_cvtps2pd256_mask",
+    "llvm.x86.avx512.mask.cvtps2pd.512" => "__builtin_ia32_cvtps2pd512_mask",
+    "llvm.x86.avx512.mask.cvtps2qq.128" => "__builtin_ia32_cvtps2qq128_mask",
+    "llvm.x86.avx512.mask.cvtps2qq.256" => "__builtin_ia32_cvtps2qq256_mask",
+    "llvm.x86.avx512.mask.cvtps2qq.512" => "__builtin_ia32_cvtps2qq512_mask",
+    "llvm.x86.avx512.mask.cvtps2udq.128" => "__builtin_ia32_cvtps2udq128_mask",
+    "llvm.x86.avx512.mask.cvtps2udq.256" => "__builtin_ia32_cvtps2udq256_mask",
+    "llvm.x86.avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask",
+    "llvm.x86.avx512.mask.cvtps2uqq.128" => "__builtin_ia32_cvtps2uqq128_mask",
+    "llvm.x86.avx512.mask.cvtps2uqq.256" => "__builtin_ia32_cvtps2uqq256_mask",
+    "llvm.x86.avx512.mask.cvtps2uqq.512" => "__builtin_ia32_cvtps2uqq512_mask",
+    "llvm.x86.avx512.mask.cvtqq2pd.128" => "__builtin_ia32_cvtqq2pd128_mask",
+    "llvm.x86.avx512.mask.cvtqq2pd.256" => "__builtin_ia32_cvtqq2pd256_mask",
+    "llvm.x86.avx512.mask.cvtqq2pd.512" => "__builtin_ia32_cvtqq2pd512_mask",
+    "llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask",
+    "llvm.x86.avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask",
+    "llvm.x86.avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask",
+    "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask",
+    "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask",
+    "llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask",
+    "llvm.x86.avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask",
+    "llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask",
+    "llvm.x86.avx512.mask.cvttpd2qq.128" => "__builtin_ia32_cvttpd2qq128_mask",
+    "llvm.x86.avx512.mask.cvttpd2qq.256" => "__builtin_ia32_cvttpd2qq256_mask",
+    "llvm.x86.avx512.mask.cvttpd2qq.512" => "__builtin_ia32_cvttpd2qq512_mask",
+    "llvm.x86.avx512.mask.cvttpd2udq.128" => "__builtin_ia32_cvttpd2udq128_mask",
+    "llvm.x86.avx512.mask.cvttpd2udq.256" => "__builtin_ia32_cvttpd2udq256_mask",
+    "llvm.x86.avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask",
+    "llvm.x86.avx512.mask.cvttpd2uqq.128" => "__builtin_ia32_cvttpd2uqq128_mask",
+    "llvm.x86.avx512.mask.cvttpd2uqq.256" => "__builtin_ia32_cvttpd2uqq256_mask",
+    "llvm.x86.avx512.mask.cvttpd2uqq.512" => "__builtin_ia32_cvttpd2uqq512_mask",
+    "llvm.x86.avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask",
+    "llvm.x86.avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask",
+    "llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask",
+    "llvm.x86.avx512.mask.cvttps2qq.128" => "__builtin_ia32_cvttps2qq128_mask",
+    "llvm.x86.avx512.mask.cvttps2qq.256" => "__builtin_ia32_cvttps2qq256_mask",
+    "llvm.x86.avx512.mask.cvttps2qq.512" => "__builtin_ia32_cvttps2qq512_mask",
+    "llvm.x86.avx512.mask.cvttps2udq.128" => "__builtin_ia32_cvttps2udq128_mask",
+    "llvm.x86.avx512.mask.cvttps2udq.256" => "__builtin_ia32_cvttps2udq256_mask",
+    "llvm.x86.avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask",
+    "llvm.x86.avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask",
+    "llvm.x86.avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask",
+    "llvm.x86.avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask",
+    "llvm.x86.avx512.mask.cvtudq2pd.128" => "__builtin_ia32_cvtudq2pd128_mask",
+    "llvm.x86.avx512.mask.cvtudq2pd.256" => "__builtin_ia32_cvtudq2pd256_mask",
+    "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask",
+    "llvm.x86.avx512.mask.cvtudq2ps.128" => "__builtin_ia32_cvtudq2ps128_mask",
+    "llvm.x86.avx512.mask.cvtudq2ps.256" => "__builtin_ia32_cvtudq2ps256_mask",
+    "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask",
+    "llvm.x86.avx512.mask.cvtuqq2pd.128" => "__builtin_ia32_cvtuqq2pd128_mask",
+    "llvm.x86.avx512.mask.cvtuqq2pd.256" => "__builtin_ia32_cvtuqq2pd256_mask",
+    "llvm.x86.avx512.mask.cvtuqq2pd.512" => "__builtin_ia32_cvtuqq2pd512_mask",
+    "llvm.x86.avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask",
+    "llvm.x86.avx512.mask.cvtuqq2ps.256" => "__builtin_ia32_cvtuqq2ps256_mask",
+    "llvm.x86.avx512.mask.cvtuqq2ps.512" => "__builtin_ia32_cvtuqq2ps512_mask",
+    "llvm.x86.avx512.mask.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask",
+    "llvm.x86.avx512.mask.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask",
+    "llvm.x86.avx512.mask.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask",
+    "llvm.x86.avx512.mask.div.pd.128" => "__builtin_ia32_divpd_mask",
+    "llvm.x86.avx512.mask.div.pd.256" => "__builtin_ia32_divpd256_mask",
+    "llvm.x86.avx512.mask.div.pd.512" => "__builtin_ia32_divpd512_mask",
+    "llvm.x86.avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask",
+    "llvm.x86.avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask",
+    "llvm.x86.avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask",
+    "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask",
+    "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask",
+    "llvm.x86.avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask",
+    "llvm.x86.avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask",
+    "llvm.x86.avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask",
+    "llvm.x86.avx512.mask.expand.load.d.128" => "__builtin_ia32_expandloadsi128_mask",
+    "llvm.x86.avx512.mask.expand.load.d.256" => "__builtin_ia32_expandloadsi256_mask",
+    "llvm.x86.avx512.mask.expand.load.d.512" => "__builtin_ia32_expandloadsi512_mask",
+    "llvm.x86.avx512.mask.expand.load.pd.128" => "__builtin_ia32_expandloaddf128_mask",
+    "llvm.x86.avx512.mask.expand.load.pd.256" => "__builtin_ia32_expandloaddf256_mask",
+    "llvm.x86.avx512.mask.expand.load.pd.512" => "__builtin_ia32_expandloaddf512_mask",
+    "llvm.x86.avx512.mask.expand.load.ps.128" => "__builtin_ia32_expandloadsf128_mask",
+    "llvm.x86.avx512.mask.expand.load.ps.256" => "__builtin_ia32_expandloadsf256_mask",
+    "llvm.x86.avx512.mask.expand.load.ps.512" => "__builtin_ia32_expandloadsf512_mask",
+    "llvm.x86.avx512.mask.expand.load.q.128" => "__builtin_ia32_expandloaddi128_mask",
+    "llvm.x86.avx512.mask.expand.load.q.256" => "__builtin_ia32_expandloaddi256_mask",
+    "llvm.x86.avx512.mask.expand.load.q.512" => "__builtin_ia32_expandloaddi512_mask",
+    "llvm.x86.avx512.mask.expand.pd.128" => "__builtin_ia32_expanddf128_mask",
+    "llvm.x86.avx512.mask.expand.pd.256" => "__builtin_ia32_expanddf256_mask",
+    "llvm.x86.avx512.mask.expand.pd.512" => "__builtin_ia32_expanddf512_mask",
+    "llvm.x86.avx512.mask.expand.ps.128" => "__builtin_ia32_expandsf128_mask",
+    "llvm.x86.avx512.mask.expand.ps.256" => "__builtin_ia32_expandsf256_mask",
+    "llvm.x86.avx512.mask.expand.ps.512" => "__builtin_ia32_expandsf512_mask",
+    "llvm.x86.avx512.mask.expand.q.128" => "__builtin_ia32_expanddi128_mask",
+    "llvm.x86.avx512.mask.expand.q.256" => "__builtin_ia32_expanddi256_mask",
+    "llvm.x86.avx512.mask.expand.q.512" => "__builtin_ia32_expanddi512_mask",
+    "llvm.x86.avx512.mask.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_mask",
+    "llvm.x86.avx512.mask.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_mask",
+    "llvm.x86.avx512.mask.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_mask",
+    "llvm.x86.avx512.mask.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_mask",
+    "llvm.x86.avx512.mask.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_mask",
+    "llvm.x86.avx512.mask.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_mask",
+    "llvm.x86.avx512.mask.fixupimm.sd" => "__builtin_ia32_fixupimmsd_mask",
+    "llvm.x86.avx512.mask.fixupimm.ss" => "__builtin_ia32_fixupimmss_mask",
+    "llvm.x86.avx512.mask.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask",
+    "llvm.x86.avx512.mask.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask",
+    "llvm.x86.avx512.mask.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask",
+    "llvm.x86.avx512.mask.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask",
+    "llvm.x86.avx512.mask.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask",
+    "llvm.x86.avx512.mask.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask",
+    "llvm.x86.avx512.mask.fpclass.sd" => "__builtin_ia32_fpclasssd_mask",
+    "llvm.x86.avx512.mask.fpclass.ss" => "__builtin_ia32_fpclassss_mask",
+    "llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask",
+    "llvm.x86.avx512.mask.getexp.pd.256" => "__builtin_ia32_getexppd256_mask",
+    "llvm.x86.avx512.mask.getexp.pd.512" => "__builtin_ia32_getexppd512_mask",
+    "llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask",
+    "llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask",
+    "llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask",
+    "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask",
+    "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask",
+    "llvm.x86.avx512.mask.getmant.pd.128" => "__builtin_ia32_getmantpd128_mask",
+    "llvm.x86.avx512.mask.getmant.pd.256" => "__builtin_ia32_getmantpd256_mask",
+    "llvm.x86.avx512.mask.getmant.pd.512" => "__builtin_ia32_getmantpd512_mask",
+    "llvm.x86.avx512.mask.getmant.ps.128" => "__builtin_ia32_getmantps128_mask",
+    "llvm.x86.avx512.mask.getmant.ps.256" => "__builtin_ia32_getmantps256_mask",
+    "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask",
+    "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask",
+    "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask",
+    "llvm.x86.avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask",
+    "llvm.x86.avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask",
+    "llvm.x86.avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask",
+    "llvm.x86.avx512.mask.insertf64x2.256" => "__builtin_ia32_insertf64x2_256_mask",
+    "llvm.x86.avx512.mask.insertf64x2.512" => "__builtin_ia32_insertf64x2_512_mask",
+    "llvm.x86.avx512.mask.insertf64x4.512" => "__builtin_ia32_insertf64x4_mask",
+    "llvm.x86.avx512.mask.inserti32x4.256" => "__builtin_ia32_inserti32x4_256_mask",
+    "llvm.x86.avx512.mask.inserti32x4.512" => "__builtin_ia32_inserti32x4_mask",
+    "llvm.x86.avx512.mask.inserti32x8.512" => "__builtin_ia32_inserti32x8_mask",
+    "llvm.x86.avx512.mask.inserti64x2.256" => "__builtin_ia32_inserti64x2_256_mask",
+    "llvm.x86.avx512.mask.inserti64x2.512" => "__builtin_ia32_inserti64x2_512_mask",
+    "llvm.x86.avx512.mask.inserti64x4.512" => "__builtin_ia32_inserti64x4_mask",
+    "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask",
+    "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask",
+    "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask",
+    "llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask",
+    "llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask",
+    "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask",
+    "llvm.x86.avx512.mask.max.pd.128" => "__builtin_ia32_maxpd_mask",
+    "llvm.x86.avx512.mask.max.pd.256" => "__builtin_ia32_maxpd256_mask",
+    "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask",
+    "llvm.x86.avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask",
+    "llvm.x86.avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask",
+    "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask",
+    "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask",
+    "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask",
+    "llvm.x86.avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask",
+    "llvm.x86.avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask",
+    "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask",
+    "llvm.x86.avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask",
+    "llvm.x86.avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask",
+    "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask",
+    "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask",
+    "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask",
+    "llvm.x86.avx512.mask.move.sd" => "__builtin_ia32_movsd_mask",
+    "llvm.x86.avx512.mask.move.ss" => "__builtin_ia32_movss_mask",
+    "llvm.x86.avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask",
+    "llvm.x86.avx512.mask.mul.pd.256" => "__builtin_ia32_mulpd256_mask",
+    "llvm.x86.avx512.mask.mul.pd.512" => "__builtin_ia32_mulpd512_mask",
+    "llvm.x86.avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask",
+    "llvm.x86.avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask",
+    "llvm.x86.avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask",
+    "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask",
+    "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask",
+    "llvm.x86.avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask",
+    "llvm.x86.avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask",
+    "llvm.x86.avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask",
+    "llvm.x86.avx512.mask.or.ps.128" => "__builtin_ia32_orps128_mask",
+    "llvm.x86.avx512.mask.or.ps.256" => "__builtin_ia32_orps256_mask",
+    "llvm.x86.avx512.mask.or.ps.512" => "__builtin_ia32_orps512_mask",
+    "llvm.x86.avx512.mask.pabs.b.128" => "__builtin_ia32_pabsb128_mask",
+    "llvm.x86.avx512.mask.pabs.b.256" => "__builtin_ia32_pabsb256_mask",
+    "llvm.x86.avx512.mask.pabs.b.512" => "__builtin_ia32_pabsb512_mask",
+    "llvm.x86.avx512.mask.pabs.d.128" => "__builtin_ia32_pabsd128_mask",
+    "llvm.x86.avx512.mask.pabs.d.256" => "__builtin_ia32_pabsd256_mask",
+    "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask",
+    "llvm.x86.avx512.mask.pabs.q.128" => "__builtin_ia32_pabsq128_mask",
+    "llvm.x86.avx512.mask.pabs.q.256" => "__builtin_ia32_pabsq256_mask",
+    "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask",
+    "llvm.x86.avx512.mask.pabs.w.128" => "__builtin_ia32_pabsw128_mask",
+    "llvm.x86.avx512.mask.pabs.w.256" => "__builtin_ia32_pabsw256_mask",
+    "llvm.x86.avx512.mask.pabs.w.512" => "__builtin_ia32_pabsw512_mask",
+    "llvm.x86.avx512.mask.packssdw.128" => "__builtin_ia32_packssdw128_mask",
+    "llvm.x86.avx512.mask.packssdw.256" => "__builtin_ia32_packssdw256_mask",
+    "llvm.x86.avx512.mask.packssdw.512" => "__builtin_ia32_packssdw512_mask",
+    "llvm.x86.avx512.mask.packsswb.128" => "__builtin_ia32_packsswb128_mask",
+    "llvm.x86.avx512.mask.packsswb.256" => "__builtin_ia32_packsswb256_mask",
+    "llvm.x86.avx512.mask.packsswb.512" => "__builtin_ia32_packsswb512_mask",
+    "llvm.x86.avx512.mask.packusdw.128" => "__builtin_ia32_packusdw128_mask",
+    "llvm.x86.avx512.mask.packusdw.256" => "__builtin_ia32_packusdw256_mask",
+    "llvm.x86.avx512.mask.packusdw.512" => "__builtin_ia32_packusdw512_mask",
+    "llvm.x86.avx512.mask.packuswb.128" => "__builtin_ia32_packuswb128_mask",
+    "llvm.x86.avx512.mask.packuswb.256" => "__builtin_ia32_packuswb256_mask",
+    "llvm.x86.avx512.mask.packuswb.512" => "__builtin_ia32_packuswb512_mask",
+    "llvm.x86.avx512.mask.padd.b.128" => "__builtin_ia32_paddb128_mask",
+    "llvm.x86.avx512.mask.padd.b.256" => "__builtin_ia32_paddb256_mask",
+    "llvm.x86.avx512.mask.padd.b.512" => "__builtin_ia32_paddb512_mask",
+    "llvm.x86.avx512.mask.padd.d.128" => "__builtin_ia32_paddd128_mask",
+    "llvm.x86.avx512.mask.padd.d.256" => "__builtin_ia32_paddd256_mask",
+    "llvm.x86.avx512.mask.padd.d.512" => "__builtin_ia32_paddd512_mask",
+    "llvm.x86.avx512.mask.padd.q.128" => "__builtin_ia32_paddq128_mask",
+    "llvm.x86.avx512.mask.padd.q.256" => "__builtin_ia32_paddq256_mask",
+    "llvm.x86.avx512.mask.padd.q.512" => "__builtin_ia32_paddq512_mask",
+    "llvm.x86.avx512.mask.padd.w.128" => "__builtin_ia32_paddw128_mask",
+    "llvm.x86.avx512.mask.padd.w.256" => "__builtin_ia32_paddw256_mask",
+    "llvm.x86.avx512.mask.padd.w.512" => "__builtin_ia32_paddw512_mask",
+    "llvm.x86.avx512.mask.padds.b.128" => "__builtin_ia32_paddsb128_mask",
+    "llvm.x86.avx512.mask.padds.b.256" => "__builtin_ia32_paddsb256_mask",
+    "llvm.x86.avx512.mask.padds.b.512" => "__builtin_ia32_paddsb512_mask",
+    "llvm.x86.avx512.mask.padds.w.128" => "__builtin_ia32_paddsw128_mask",
+    "llvm.x86.avx512.mask.padds.w.256" => "__builtin_ia32_paddsw256_mask",
+    "llvm.x86.avx512.mask.padds.w.512" => "__builtin_ia32_paddsw512_mask",
+    "llvm.x86.avx512.mask.paddus.b.128" => "__builtin_ia32_paddusb128_mask",
+    "llvm.x86.avx512.mask.paddus.b.256" => "__builtin_ia32_paddusb256_mask",
+    "llvm.x86.avx512.mask.paddus.b.512" => "__builtin_ia32_paddusb512_mask",
+    "llvm.x86.avx512.mask.paddus.w.128" => "__builtin_ia32_paddusw128_mask",
+    "llvm.x86.avx512.mask.paddus.w.256" => "__builtin_ia32_paddusw256_mask",
+    "llvm.x86.avx512.mask.paddus.w.512" => "__builtin_ia32_paddusw512_mask",
+    "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask",
+    "llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask",
+    "llvm.x86.avx512.mask.pavg.b.128" => "__builtin_ia32_pavgb128_mask",
+    "llvm.x86.avx512.mask.pavg.b.256" => "__builtin_ia32_pavgb256_mask",
+    "llvm.x86.avx512.mask.pavg.b.512" => "__builtin_ia32_pavgb512_mask",
+    "llvm.x86.avx512.mask.pavg.w.128" => "__builtin_ia32_pavgw128_mask",
+    "llvm.x86.avx512.mask.pavg.w.256" => "__builtin_ia32_pavgw256_mask",
+    "llvm.x86.avx512.mask.pavg.w.512" => "__builtin_ia32_pavgw512_mask",
+    "llvm.x86.avx512.mask.pbroadcast.b.gpr.128" => "__builtin_ia32_pbroadcastb128_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.b.gpr.256" => "__builtin_ia32_pbroadcastb256_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.b.gpr.512" => "__builtin_ia32_pbroadcastb512_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.d.gpr.128" => "__builtin_ia32_pbroadcastd128_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.d.gpr.256" => "__builtin_ia32_pbroadcastd256_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.q.gpr.128" => "__builtin_ia32_pbroadcastq128_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.q.gpr.256" => "__builtin_ia32_pbroadcastq256_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask",
+    "llvm.x86.avx512.mask.pbroadcast.w.gpr.128" => "__builtin_ia32_pbroadcastw128_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.w.gpr.256" => "__builtin_ia32_pbroadcastw256_gpr_mask",
+    "llvm.x86.avx512.mask.pbroadcast.w.gpr.512" => "__builtin_ia32_pbroadcastw512_gpr_mask",
+    "llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask",
+    "llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask",
+    "llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask",
+    "llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask",
+    "llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask",
+    "llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask",
+    "llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask",
+    "llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask",
+    "llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask",
+    "llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask",
+    "llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask",
+    "llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask",
+    "llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask",
+    "llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask",
+    "llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask",
+    "llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask",
+    "llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask",
+    "llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask",
+    "llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask",
+    "llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask",
+    "llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask",
+    "llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask",
+    "llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask",
+    "llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask",
+    "llvm.x86.avx512.mask.permvar.df.256" => "__builtin_ia32_permvardf256_mask",
+    "llvm.x86.avx512.mask.permvar.df.512" => "__builtin_ia32_permvardf512_mask",
+    "llvm.x86.avx512.mask.permvar.di.256" => "__builtin_ia32_permvardi256_mask",
+    "llvm.x86.avx512.mask.permvar.di.512" => "__builtin_ia32_permvardi512_mask",
+    "llvm.x86.avx512.mask.permvar.hi.128" => "__builtin_ia32_permvarhi128_mask",
+    "llvm.x86.avx512.mask.permvar.hi.256" => "__builtin_ia32_permvarhi256_mask",
+    "llvm.x86.avx512.mask.permvar.hi.512" => "__builtin_ia32_permvarhi512_mask",
+    "llvm.x86.avx512.mask.permvar.qi.128" => "__builtin_ia32_permvarqi128_mask",
+    "llvm.x86.avx512.mask.permvar.qi.256" => "__builtin_ia32_permvarqi256_mask",
+    "llvm.x86.avx512.mask.permvar.qi.512" => "__builtin_ia32_permvarqi512_mask",
+    "llvm.x86.avx512.mask.permvar.sf.256" => "__builtin_ia32_permvarsf256_mask",
+    "llvm.x86.avx512.mask.permvar.sf.512" => "__builtin_ia32_permvarsf512_mask",
+    "llvm.x86.avx512.mask.permvar.si.256" => "__builtin_ia32_permvarsi256_mask",
+    "llvm.x86.avx512.mask.permvar.si.512" => "__builtin_ia32_permvarsi512_mask",
+    "llvm.x86.avx512.mask.pmaddubs.w.128" => "__builtin_ia32_pmaddubsw128_mask",
+    "llvm.x86.avx512.mask.pmaddubs.w.256" => "__builtin_ia32_pmaddubsw256_mask",
+    "llvm.x86.avx512.mask.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512_mask",
+    "llvm.x86.avx512.mask.pmaddw.d.128" => "__builtin_ia32_pmaddwd128_mask",
+    "llvm.x86.avx512.mask.pmaddw.d.256" => "__builtin_ia32_pmaddwd256_mask",
+    "llvm.x86.avx512.mask.pmaddw.d.512" => "__builtin_ia32_pmaddwd512_mask",
+    "llvm.x86.avx512.mask.pmaxs.b.128" => "__builtin_ia32_pmaxsb128_mask",
+    "llvm.x86.avx512.mask.pmaxs.b.256" => "__builtin_ia32_pmaxsb256_mask",
+    "llvm.x86.avx512.mask.pmaxs.b.512" => "__builtin_ia32_pmaxsb512_mask",
+    "llvm.x86.avx512.mask.pmaxs.d.128" => "__builtin_ia32_pmaxsd128_mask",
+    "llvm.x86.avx512.mask.pmaxs.d.256" => "__builtin_ia32_pmaxsd256_mask",
+    "llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask",
+    "llvm.x86.avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask",
+    "llvm.x86.avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask",
+    "llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask",
+    "llvm.x86.avx512.mask.pmaxs.w.128" => "__builtin_ia32_pmaxsw128_mask",
+    "llvm.x86.avx512.mask.pmaxs.w.256" => "__builtin_ia32_pmaxsw256_mask",
+    "llvm.x86.avx512.mask.pmaxs.w.512" => "__builtin_ia32_pmaxsw512_mask",
+    "llvm.x86.avx512.mask.pmaxu.b.128" => "__builtin_ia32_pmaxub128_mask",
+    "llvm.x86.avx512.mask.pmaxu.b.256" => "__builtin_ia32_pmaxub256_mask",
+    "llvm.x86.avx512.mask.pmaxu.b.512" => "__builtin_ia32_pmaxub512_mask",
+    "llvm.x86.avx512.mask.pmaxu.d.128" => "__builtin_ia32_pmaxud128_mask",
+    "llvm.x86.avx512.mask.pmaxu.d.256" => "__builtin_ia32_pmaxud256_mask",
+    "llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask",
+    "llvm.x86.avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask",
+    "llvm.x86.avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask",
+    "llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask",
+    "llvm.x86.avx512.mask.pmaxu.w.128" => "__builtin_ia32_pmaxuw128_mask",
+    "llvm.x86.avx512.mask.pmaxu.w.256" => "__builtin_ia32_pmaxuw256_mask",
+    "llvm.x86.avx512.mask.pmaxu.w.512" => "__builtin_ia32_pmaxuw512_mask",
+    "llvm.x86.avx512.mask.pmins.b.128" => "__builtin_ia32_pminsb128_mask",
+    "llvm.x86.avx512.mask.pmins.b.256" => "__builtin_ia32_pminsb256_mask",
+    "llvm.x86.avx512.mask.pmins.b.512" => "__builtin_ia32_pminsb512_mask",
+    "llvm.x86.avx512.mask.pmins.d.128" => "__builtin_ia32_pminsd128_mask",
+    "llvm.x86.avx512.mask.pmins.d.256" => "__builtin_ia32_pminsd256_mask",
+    "llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask",
+    "llvm.x86.avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask",
+    "llvm.x86.avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask",
+    "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask",
+    "llvm.x86.avx512.mask.pmins.w.128" => "__builtin_ia32_pminsw128_mask",
+    "llvm.x86.avx512.mask.pmins.w.256" => "__builtin_ia32_pminsw256_mask",
+    "llvm.x86.avx512.mask.pmins.w.512" => "__builtin_ia32_pminsw512_mask",
+    "llvm.x86.avx512.mask.pminu.b.128" => "__builtin_ia32_pminub128_mask",
+    "llvm.x86.avx512.mask.pminu.b.256" => "__builtin_ia32_pminub256_mask",
+    "llvm.x86.avx512.mask.pminu.b.512" => "__builtin_ia32_pminub512_mask",
+    "llvm.x86.avx512.mask.pminu.d.128" => "__builtin_ia32_pminud128_mask",
+    "llvm.x86.avx512.mask.pminu.d.256" => "__builtin_ia32_pminud256_mask",
+    "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask",
+    "llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask",
+    "llvm.x86.avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask",
+    "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask",
+    "llvm.x86.avx512.mask.pminu.w.128" => "__builtin_ia32_pminuw128_mask",
+    "llvm.x86.avx512.mask.pminu.w.256" => "__builtin_ia32_pminuw256_mask",
+    "llvm.x86.avx512.mask.pminu.w.512" => "__builtin_ia32_pminuw512_mask",
+    "llvm.x86.avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask",
+    "llvm.x86.avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask",
+    "llvm.x86.avx512.mask.pmov.db.512" => "__builtin_ia32_pmovdb512_mask",
+    "llvm.x86.avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask",
+    "llvm.x86.avx512.mask.pmov.db.mem.256" => "__builtin_ia32_pmovdb256mem_mask",
+    "llvm.x86.avx512.mask.pmov.db.mem.512" => "__builtin_ia32_pmovdb512mem_mask",
+    "llvm.x86.avx512.mask.pmov.dw.128" => "__builtin_ia32_pmovdw128_mask",
+    "llvm.x86.avx512.mask.pmov.dw.256" => "__builtin_ia32_pmovdw256_mask",
+    "llvm.x86.avx512.mask.pmov.dw.512" => "__builtin_ia32_pmovdw512_mask",
+    "llvm.x86.avx512.mask.pmov.dw.mem.128" => "__builtin_ia32_pmovdw128mem_mask",
+    "llvm.x86.avx512.mask.pmov.dw.mem.256" => "__builtin_ia32_pmovdw256mem_mask",
+    "llvm.x86.avx512.mask.pmov.dw.mem.512" => "__builtin_ia32_pmovdw512mem_mask",
+    "llvm.x86.avx512.mask.pmov.qb.128" => "__builtin_ia32_pmovqb128_mask",
+    "llvm.x86.avx512.mask.pmov.qb.256" => "__builtin_ia32_pmovqb256_mask",
+    "llvm.x86.avx512.mask.pmov.qb.512" => "__builtin_ia32_pmovqb512_mask",
+    "llvm.x86.avx512.mask.pmov.qb.mem.128" => "__builtin_ia32_pmovqb128mem_mask",
+    "llvm.x86.avx512.mask.pmov.qb.mem.256" => "__builtin_ia32_pmovqb256mem_mask",
+    "llvm.x86.avx512.mask.pmov.qb.mem.512" => "__builtin_ia32_pmovqb512mem_mask",
+    "llvm.x86.avx512.mask.pmov.qd.128" => "__builtin_ia32_pmovqd128_mask",
+    "llvm.x86.avx512.mask.pmov.qd.256" => "__builtin_ia32_pmovqd256_mask",
+    "llvm.x86.avx512.mask.pmov.qd.512" => "__builtin_ia32_pmovqd512_mask",
+    "llvm.x86.avx512.mask.pmov.qd.mem.128" => "__builtin_ia32_pmovqd128mem_mask",
+    "llvm.x86.avx512.mask.pmov.qd.mem.256" => "__builtin_ia32_pmovqd256mem_mask",
+    "llvm.x86.avx512.mask.pmov.qd.mem.512" => "__builtin_ia32_pmovqd512mem_mask",
+    "llvm.x86.avx512.mask.pmov.qw.128" => "__builtin_ia32_pmovqw128_mask",
+    "llvm.x86.avx512.mask.pmov.qw.256" => "__builtin_ia32_pmovqw256_mask",
+    "llvm.x86.avx512.mask.pmov.qw.512" => "__builtin_ia32_pmovqw512_mask",
+    "llvm.x86.avx512.mask.pmov.qw.mem.128" => "__builtin_ia32_pmovqw128mem_mask",
+    "llvm.x86.avx512.mask.pmov.qw.mem.256" => "__builtin_ia32_pmovqw256mem_mask",
+    "llvm.x86.avx512.mask.pmov.qw.mem.512" => "__builtin_ia32_pmovqw512mem_mask",
+    "llvm.x86.avx512.mask.pmov.wb.128" => "__builtin_ia32_pmovwb128_mask",
+    "llvm.x86.avx512.mask.pmov.wb.256" => "__builtin_ia32_pmovwb256_mask",
+    "llvm.x86.avx512.mask.pmov.wb.512" => "__builtin_ia32_pmovwb512_mask",
+    "llvm.x86.avx512.mask.pmov.wb.mem.128" => "__builtin_ia32_pmovwb128mem_mask",
+    "llvm.x86.avx512.mask.pmov.wb.mem.256" => "__builtin_ia32_pmovwb256mem_mask",
+    "llvm.x86.avx512.mask.pmov.wb.mem.512" => "__builtin_ia32_pmovwb512mem_mask",
+    "llvm.x86.avx512.mask.pmovs.db.128" => "__builtin_ia32_pmovsdb128_mask",
+    "llvm.x86.avx512.mask.pmovs.db.256" => "__builtin_ia32_pmovsdb256_mask",
+    "llvm.x86.avx512.mask.pmovs.db.512" => "__builtin_ia32_pmovsdb512_mask",
+    "llvm.x86.avx512.mask.pmovs.db.mem.128" => "__builtin_ia32_pmovsdb128mem_mask",
+    "llvm.x86.avx512.mask.pmovs.db.mem.256" => "__builtin_ia32_pmovsdb256mem_mask",
+    "llvm.x86.avx512.mask.pmovs.db.mem.512" => "__builtin_ia32_pmovsdb512mem_mask",
+    "llvm.x86.avx512.mask.pmovs.dw.128" => "__builtin_ia32_pmovsdw128_mask",
+    "llvm.x86.avx512.mask.pmovs.dw.256" => "__builtin_ia32_pmovsdw256_mask",
+    "llvm.x86.avx512.mask.pmovs.dw.512" => "__builtin_ia32_pmovsdw512_mask",
+    "llvm.x86.avx512.mask.pmovs.dw.mem.128" => "__builtin_ia32_pmovsdw128mem_mask",
+    "llvm.x86.avx512.mask.pmovs.dw.mem.256" => "__builtin_ia32_pmovsdw256mem_mask",
+    "llvm.x86.avx512.mask.pmovs.dw.mem.512" => "__builtin_ia32_pmovsdw512mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qb.128" => "__builtin_ia32_pmovsqb128_mask",
+    "llvm.x86.avx512.mask.pmovs.qb.256" => "__builtin_ia32_pmovsqb256_mask",
+    "llvm.x86.avx512.mask.pmovs.qb.512" => "__builtin_ia32_pmovsqb512_mask",
+    "llvm.x86.avx512.mask.pmovs.qb.mem.128" => "__builtin_ia32_pmovsqb128mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qb.mem.256" => "__builtin_ia32_pmovsqb256mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qb.mem.512" => "__builtin_ia32_pmovsqb512mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qd.128" => "__builtin_ia32_pmovsqd128_mask",
+    "llvm.x86.avx512.mask.pmovs.qd.256" => "__builtin_ia32_pmovsqd256_mask",
+    "llvm.x86.avx512.mask.pmovs.qd.512" => "__builtin_ia32_pmovsqd512_mask",
+    "llvm.x86.avx512.mask.pmovs.qd.mem.128" => "__builtin_ia32_pmovsqd128mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qd.mem.256" => "__builtin_ia32_pmovsqd256mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qd.mem.512" => "__builtin_ia32_pmovsqd512mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qw.128" => "__builtin_ia32_pmovsqw128_mask",
+    "llvm.x86.avx512.mask.pmovs.qw.256" => "__builtin_ia32_pmovsqw256_mask",
+    "llvm.x86.avx512.mask.pmovs.qw.512" => "__builtin_ia32_pmovsqw512_mask",
+    "llvm.x86.avx512.mask.pmovs.qw.mem.128" => "__builtin_ia32_pmovsqw128mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qw.mem.256" => "__builtin_ia32_pmovsqw256mem_mask",
+    "llvm.x86.avx512.mask.pmovs.qw.mem.512" => "__builtin_ia32_pmovsqw512mem_mask",
+    "llvm.x86.avx512.mask.pmovs.wb.128" => "__builtin_ia32_pmovswb128_mask",
+    "llvm.x86.avx512.mask.pmovs.wb.256" => "__builtin_ia32_pmovswb256_mask",
+    "llvm.x86.avx512.mask.pmovs.wb.512" => "__builtin_ia32_pmovswb512_mask",
+    "llvm.x86.avx512.mask.pmovs.wb.mem.128" => "__builtin_ia32_pmovswb128mem_mask",
+    "llvm.x86.avx512.mask.pmovs.wb.mem.256" => "__builtin_ia32_pmovswb256mem_mask",
+    "llvm.x86.avx512.mask.pmovs.wb.mem.512" => "__builtin_ia32_pmovswb512mem_mask",
+    "llvm.x86.avx512.mask.pmovsxb.d.128" => "__builtin_ia32_pmovsxbd128_mask",
+    "llvm.x86.avx512.mask.pmovsxb.d.256" => "__builtin_ia32_pmovsxbd256_mask",
+    "llvm.x86.avx512.mask.pmovsxb.d.512" => "__builtin_ia32_pmovsxbd512_mask",
+    "llvm.x86.avx512.mask.pmovsxb.q.128" => "__builtin_ia32_pmovsxbq128_mask",
+    "llvm.x86.avx512.mask.pmovsxb.q.256" => "__builtin_ia32_pmovsxbq256_mask",
+    "llvm.x86.avx512.mask.pmovsxb.q.512" => "__builtin_ia32_pmovsxbq512_mask",
+    "llvm.x86.avx512.mask.pmovsxb.w.128" => "__builtin_ia32_pmovsxbw128_mask",
+    "llvm.x86.avx512.mask.pmovsxb.w.256" => "__builtin_ia32_pmovsxbw256_mask",
+    "llvm.x86.avx512.mask.pmovsxb.w.512" => "__builtin_ia32_pmovsxbw512_mask",
+    "llvm.x86.avx512.mask.pmovsxd.q.128" => "__builtin_ia32_pmovsxdq128_mask",
+    "llvm.x86.avx512.mask.pmovsxd.q.256" => "__builtin_ia32_pmovsxdq256_mask",
+    "llvm.x86.avx512.mask.pmovsxd.q.512" => "__builtin_ia32_pmovsxdq512_mask",
+    "llvm.x86.avx512.mask.pmovsxw.d.128" => "__builtin_ia32_pmovsxwd128_mask",
+    "llvm.x86.avx512.mask.pmovsxw.d.256" => "__builtin_ia32_pmovsxwd256_mask",
+    "llvm.x86.avx512.mask.pmovsxw.d.512" => "__builtin_ia32_pmovsxwd512_mask",
+    "llvm.x86.avx512.mask.pmovsxw.q.128" => "__builtin_ia32_pmovsxwq128_mask",
+    "llvm.x86.avx512.mask.pmovsxw.q.256" => "__builtin_ia32_pmovsxwq256_mask",
+    "llvm.x86.avx512.mask.pmovsxw.q.512" => "__builtin_ia32_pmovsxwq512_mask",
+    "llvm.x86.avx512.mask.pmovus.db.128" => "__builtin_ia32_pmovusdb128_mask",
+    "llvm.x86.avx512.mask.pmovus.db.256" => "__builtin_ia32_pmovusdb256_mask",
+    "llvm.x86.avx512.mask.pmovus.db.512" => "__builtin_ia32_pmovusdb512_mask",
+    "llvm.x86.avx512.mask.pmovus.db.mem.128" => "__builtin_ia32_pmovusdb128mem_mask",
+    "llvm.x86.avx512.mask.pmovus.db.mem.256" => "__builtin_ia32_pmovusdb256mem_mask",
+    "llvm.x86.avx512.mask.pmovus.db.mem.512" => "__builtin_ia32_pmovusdb512mem_mask",
+    "llvm.x86.avx512.mask.pmovus.dw.128" => "__builtin_ia32_pmovusdw128_mask",
+    "llvm.x86.avx512.mask.pmovus.dw.256" => "__builtin_ia32_pmovusdw256_mask",
+    "llvm.x86.avx512.mask.pmovus.dw.512" => "__builtin_ia32_pmovusdw512_mask",
+    "llvm.x86.avx512.mask.pmovus.dw.mem.128" => "__builtin_ia32_pmovusdw128mem_mask",
+    "llvm.x86.avx512.mask.pmovus.dw.mem.256" => "__builtin_ia32_pmovusdw256mem_mask",
+    "llvm.x86.avx512.mask.pmovus.dw.mem.512" => "__builtin_ia32_pmovusdw512mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qb.128" => "__builtin_ia32_pmovusqb128_mask",
+    "llvm.x86.avx512.mask.pmovus.qb.256" => "__builtin_ia32_pmovusqb256_mask",
+    "llvm.x86.avx512.mask.pmovus.qb.512" => "__builtin_ia32_pmovusqb512_mask",
+    "llvm.x86.avx512.mask.pmovus.qb.mem.128" => "__builtin_ia32_pmovusqb128mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qb.mem.256" => "__builtin_ia32_pmovusqb256mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qb.mem.512" => "__builtin_ia32_pmovusqb512mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qd.128" => "__builtin_ia32_pmovusqd128_mask",
+    "llvm.x86.avx512.mask.pmovus.qd.256" => "__builtin_ia32_pmovusqd256_mask",
+    "llvm.x86.avx512.mask.pmovus.qd.512" => "__builtin_ia32_pmovusqd512_mask",
+    "llvm.x86.avx512.mask.pmovus.qd.mem.128" => "__builtin_ia32_pmovusqd128mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qd.mem.256" => "__builtin_ia32_pmovusqd256mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qd.mem.512" => "__builtin_ia32_pmovusqd512mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qw.128" => "__builtin_ia32_pmovusqw128_mask",
+    "llvm.x86.avx512.mask.pmovus.qw.256" => "__builtin_ia32_pmovusqw256_mask",
+    "llvm.x86.avx512.mask.pmovus.qw.512" => "__builtin_ia32_pmovusqw512_mask",
+    "llvm.x86.avx512.mask.pmovus.qw.mem.128" => "__builtin_ia32_pmovusqw128mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qw.mem.256" => "__builtin_ia32_pmovusqw256mem_mask",
+    "llvm.x86.avx512.mask.pmovus.qw.mem.512" => "__builtin_ia32_pmovusqw512mem_mask",
+    "llvm.x86.avx512.mask.pmovus.wb.128" => "__builtin_ia32_pmovuswb128_mask",
+    "llvm.x86.avx512.mask.pmovus.wb.256" => "__builtin_ia32_pmovuswb256_mask",
+    "llvm.x86.avx512.mask.pmovus.wb.512" => "__builtin_ia32_pmovuswb512_mask",
+    "llvm.x86.avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask",
+    "llvm.x86.avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask",
+    "llvm.x86.avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask",
+    "llvm.x86.avx512.mask.pmovzxb.d.128" => "__builtin_ia32_pmovzxbd128_mask",
+    "llvm.x86.avx512.mask.pmovzxb.d.256" => "__builtin_ia32_pmovzxbd256_mask",
+    "llvm.x86.avx512.mask.pmovzxb.d.512" => "__builtin_ia32_pmovzxbd512_mask",
+    "llvm.x86.avx512.mask.pmovzxb.q.128" => "__builtin_ia32_pmovzxbq128_mask",
+    "llvm.x86.avx512.mask.pmovzxb.q.256" => "__builtin_ia32_pmovzxbq256_mask",
+    "llvm.x86.avx512.mask.pmovzxb.q.512" => "__builtin_ia32_pmovzxbq512_mask",
+    "llvm.x86.avx512.mask.pmovzxb.w.128" => "__builtin_ia32_pmovzxbw128_mask",
+    "llvm.x86.avx512.mask.pmovzxb.w.256" => "__builtin_ia32_pmovzxbw256_mask",
+    "llvm.x86.avx512.mask.pmovzxb.w.512" => "__builtin_ia32_pmovzxbw512_mask",
+    "llvm.x86.avx512.mask.pmovzxd.q.128" => "__builtin_ia32_pmovzxdq128_mask",
+    "llvm.x86.avx512.mask.pmovzxd.q.256" => "__builtin_ia32_pmovzxdq256_mask",
+    "llvm.x86.avx512.mask.pmovzxd.q.512" => "__builtin_ia32_pmovzxdq512_mask",
+    "llvm.x86.avx512.mask.pmovzxw.d.128" => "__builtin_ia32_pmovzxwd128_mask",
+    "llvm.x86.avx512.mask.pmovzxw.d.256" => "__builtin_ia32_pmovzxwd256_mask",
+    "llvm.x86.avx512.mask.pmovzxw.d.512" => "__builtin_ia32_pmovzxwd512_mask",
+    "llvm.x86.avx512.mask.pmovzxw.q.128" => "__builtin_ia32_pmovzxwq128_mask",
+    "llvm.x86.avx512.mask.pmovzxw.q.256" => "__builtin_ia32_pmovzxwq256_mask",
+    "llvm.x86.avx512.mask.pmovzxw.q.512" => "__builtin_ia32_pmovzxwq512_mask",
+    "llvm.x86.avx512.mask.pmul.dq.128" => "__builtin_ia32_pmuldq128_mask",
+    "llvm.x86.avx512.mask.pmul.dq.256" => "__builtin_ia32_pmuldq256_mask",
+    "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask",
+    "llvm.x86.avx512.mask.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128_mask",
+    "llvm.x86.avx512.mask.pmul.hr.sw.256" => "__builtin_ia32_pmulhrsw256_mask",
+    "llvm.x86.avx512.mask.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512_mask",
+    "llvm.x86.avx512.mask.pmulh.w.128" => "__builtin_ia32_pmulhw128_mask",
+    "llvm.x86.avx512.mask.pmulh.w.256" => "__builtin_ia32_pmulhw256_mask",
+    "llvm.x86.avx512.mask.pmulh.w.512" => "__builtin_ia32_pmulhw512_mask",
+    "llvm.x86.avx512.mask.pmulhu.w.128" => "__builtin_ia32_pmulhuw128_mask",
+    "llvm.x86.avx512.mask.pmulhu.w.256" => "__builtin_ia32_pmulhuw256_mask",
+    "llvm.x86.avx512.mask.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask",
+    "llvm.x86.avx512.mask.pmull.d.128" => "__builtin_ia32_pmulld128_mask",
+    "llvm.x86.avx512.mask.pmull.d.256" => "__builtin_ia32_pmulld256_mask",
+    "llvm.x86.avx512.mask.pmull.d.512" => "__builtin_ia32_pmulld512_mask",
+    "llvm.x86.avx512.mask.pmull.q.128" => "__builtin_ia32_pmullq128_mask",
+    "llvm.x86.avx512.mask.pmull.q.256" => "__builtin_ia32_pmullq256_mask",
+    "llvm.x86.avx512.mask.pmull.q.512" => "__builtin_ia32_pmullq512_mask",
+    "llvm.x86.avx512.mask.pmull.w.128" => "__builtin_ia32_pmullw128_mask",
+    "llvm.x86.avx512.mask.pmull.w.256" => "__builtin_ia32_pmullw256_mask",
+    "llvm.x86.avx512.mask.pmull.w.512" => "__builtin_ia32_pmullw512_mask",
+    "llvm.x86.avx512.mask.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128_mask",
+    "llvm.x86.avx512.mask.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256_mask",
+    "llvm.x86.avx512.mask.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512_mask",
+    "llvm.x86.avx512.mask.pmulu.dq.128" => "__builtin_ia32_pmuludq128_mask",
+    "llvm.x86.avx512.mask.pmulu.dq.256" => "__builtin_ia32_pmuludq256_mask",
+    "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask",
+    "llvm.x86.avx512.mask.prol.d.128" => "__builtin_ia32_prold128_mask",
+    "llvm.x86.avx512.mask.prol.d.256" => "__builtin_ia32_prold256_mask",
+    "llvm.x86.avx512.mask.prol.d.512" => "__builtin_ia32_prold512_mask",
+    "llvm.x86.avx512.mask.prol.q.128" => "__builtin_ia32_prolq128_mask",
+    "llvm.x86.avx512.mask.prol.q.256" => "__builtin_ia32_prolq256_mask",
+    "llvm.x86.avx512.mask.prol.q.512" => "__builtin_ia32_prolq512_mask",
+    "llvm.x86.avx512.mask.prolv.d.128" => "__builtin_ia32_prolvd128_mask",
+    "llvm.x86.avx512.mask.prolv.d.256" => "__builtin_ia32_prolvd256_mask",
+    "llvm.x86.avx512.mask.prolv.d.512" => "__builtin_ia32_prolvd512_mask",
+    "llvm.x86.avx512.mask.prolv.q.128" => "__builtin_ia32_prolvq128_mask",
+    "llvm.x86.avx512.mask.prolv.q.256" => "__builtin_ia32_prolvq256_mask",
+    "llvm.x86.avx512.mask.prolv.q.512" => "__builtin_ia32_prolvq512_mask",
+    "llvm.x86.avx512.mask.pror.d.128" => "__builtin_ia32_prord128_mask",
+    "llvm.x86.avx512.mask.pror.d.256" => "__builtin_ia32_prord256_mask",
+    "llvm.x86.avx512.mask.pror.d.512" => "__builtin_ia32_prord512_mask",
+    "llvm.x86.avx512.mask.pror.q.128" => "__builtin_ia32_prorq128_mask",
+    "llvm.x86.avx512.mask.pror.q.256" => "__builtin_ia32_prorq256_mask",
+    "llvm.x86.avx512.mask.pror.q.512" => "__builtin_ia32_prorq512_mask",
+    "llvm.x86.avx512.mask.prorv.d.128" => "__builtin_ia32_prorvd128_mask",
+    "llvm.x86.avx512.mask.prorv.d.256" => "__builtin_ia32_prorvd256_mask",
+    "llvm.x86.avx512.mask.prorv.d.512" => "__builtin_ia32_prorvd512_mask",
+    "llvm.x86.avx512.mask.prorv.q.128" => "__builtin_ia32_prorvq128_mask",
+    "llvm.x86.avx512.mask.prorv.q.256" => "__builtin_ia32_prorvq256_mask",
+    "llvm.x86.avx512.mask.prorv.q.512" => "__builtin_ia32_prorvq512_mask",
+    "llvm.x86.avx512.mask.pshuf.b.128" => "__builtin_ia32_pshufb128_mask",
+    "llvm.x86.avx512.mask.pshuf.b.256" => "__builtin_ia32_pshufb256_mask",
+    "llvm.x86.avx512.mask.pshuf.b.512" => "__builtin_ia32_pshufb512_mask",
+    "llvm.x86.avx512.mask.psll.d" => "__builtin_ia32_pslld512_mask",
+    "llvm.x86.avx512.mask.psll.d.128" => "__builtin_ia32_pslld128_mask",
+    "llvm.x86.avx512.mask.psll.d.256" => "__builtin_ia32_pslld256_mask",
+    "llvm.x86.avx512.mask.psll.di.128" => "__builtin_ia32_pslldi128_mask",
+    "llvm.x86.avx512.mask.psll.di.256" => "__builtin_ia32_pslldi256_mask",
+    "llvm.x86.avx512.mask.psll.di.512" => "__builtin_ia32_pslldi512_mask",
+    "llvm.x86.avx512.mask.psll.q" => "__builtin_ia32_psllq512_mask",
+    "llvm.x86.avx512.mask.psll.q.128" => "__builtin_ia32_psllq128_mask",
+    "llvm.x86.avx512.mask.psll.q.256" => "__builtin_ia32_psllq256_mask",
+    "llvm.x86.avx512.mask.psll.qi.128" => "__builtin_ia32_psllqi128_mask",
+    "llvm.x86.avx512.mask.psll.qi.256" => "__builtin_ia32_psllqi256_mask",
+    "llvm.x86.avx512.mask.psll.qi.512" => "__builtin_ia32_psllqi512_mask",
+    "llvm.x86.avx512.mask.psll.w.128" => "__builtin_ia32_psllw128_mask",
+    "llvm.x86.avx512.mask.psll.w.256" => "__builtin_ia32_psllw256_mask",
+    "llvm.x86.avx512.mask.psll.w.512" => "__builtin_ia32_psllw512_mask",
+    "llvm.x86.avx512.mask.psll.wi.128" => "__builtin_ia32_psllwi128_mask",
+    "llvm.x86.avx512.mask.psll.wi.256" => "__builtin_ia32_psllwi256_mask",
+    "llvm.x86.avx512.mask.psll.wi.512" => "__builtin_ia32_psllwi512_mask",
+    "llvm.x86.avx512.mask.psllv.d" => "__builtin_ia32_psllv16si_mask",
+    "llvm.x86.avx512.mask.psllv.q" => "__builtin_ia32_psllv8di_mask",
+    "llvm.x86.avx512.mask.psllv16.hi" => "__builtin_ia32_psllv16hi_mask",
+    "llvm.x86.avx512.mask.psllv2.di" => "__builtin_ia32_psllv2di_mask",
+    "llvm.x86.avx512.mask.psllv32hi" => "__builtin_ia32_psllv32hi_mask",
+    "llvm.x86.avx512.mask.psllv4.di" => "__builtin_ia32_psllv4di_mask",
+    "llvm.x86.avx512.mask.psllv4.si" => "__builtin_ia32_psllv4si_mask",
+    "llvm.x86.avx512.mask.psllv8.hi" => "__builtin_ia32_psllv8hi_mask",
+    "llvm.x86.avx512.mask.psllv8.si" => "__builtin_ia32_psllv8si_mask",
+    "llvm.x86.avx512.mask.psra.d" => "__builtin_ia32_psrad512_mask",
+    "llvm.x86.avx512.mask.psra.d.128" => "__builtin_ia32_psrad128_mask",
+    "llvm.x86.avx512.mask.psra.d.256" => "__builtin_ia32_psrad256_mask",
+    "llvm.x86.avx512.mask.psra.di.128" => "__builtin_ia32_psradi128_mask",
+    "llvm.x86.avx512.mask.psra.di.256" => "__builtin_ia32_psradi256_mask",
+    "llvm.x86.avx512.mask.psra.di.512" => "__builtin_ia32_psradi512_mask",
+    "llvm.x86.avx512.mask.psra.q" => "__builtin_ia32_psraq512_mask",
+    "llvm.x86.avx512.mask.psra.q.128" => "__builtin_ia32_psraq128_mask",
+    "llvm.x86.avx512.mask.psra.q.256" => "__builtin_ia32_psraq256_mask",
+    "llvm.x86.avx512.mask.psra.qi.128" => "__builtin_ia32_psraqi128_mask",
+    "llvm.x86.avx512.mask.psra.qi.256" => "__builtin_ia32_psraqi256_mask",
+    "llvm.x86.avx512.mask.psra.qi.512" => "__builtin_ia32_psraqi512_mask",
+    "llvm.x86.avx512.mask.psra.w.128" => "__builtin_ia32_psraw128_mask",
+    "llvm.x86.avx512.mask.psra.w.256" => "__builtin_ia32_psraw256_mask",
+    "llvm.x86.avx512.mask.psra.w.512" => "__builtin_ia32_psraw512_mask",
+    "llvm.x86.avx512.mask.psra.wi.128" => "__builtin_ia32_psrawi128_mask",
+    "llvm.x86.avx512.mask.psra.wi.256" => "__builtin_ia32_psrawi256_mask",
+    "llvm.x86.avx512.mask.psra.wi.512" => "__builtin_ia32_psrawi512_mask",
+    "llvm.x86.avx512.mask.psrav.d" => "__builtin_ia32_psrav16si_mask",
+    "llvm.x86.avx512.mask.psrav.q" => "__builtin_ia32_psrav8di_mask",
+    "llvm.x86.avx512.mask.psrav.q.128" => "__builtin_ia32_psravq128_mask",
+    "llvm.x86.avx512.mask.psrav.q.256" => "__builtin_ia32_psravq256_mask",
+    "llvm.x86.avx512.mask.psrav16.hi" => "__builtin_ia32_psrav16hi_mask",
+    "llvm.x86.avx512.mask.psrav32.hi" => "__builtin_ia32_psrav32hi_mask",
+    "llvm.x86.avx512.mask.psrav4.si" => "__builtin_ia32_psrav4si_mask",
+    "llvm.x86.avx512.mask.psrav8.hi" => "__builtin_ia32_psrav8hi_mask",
+    "llvm.x86.avx512.mask.psrav8.si" => "__builtin_ia32_psrav8si_mask",
+    "llvm.x86.avx512.mask.psrl.d" => "__builtin_ia32_psrld512_mask",
+    "llvm.x86.avx512.mask.psrl.d.128" => "__builtin_ia32_psrld128_mask",
+    "llvm.x86.avx512.mask.psrl.d.256" => "__builtin_ia32_psrld256_mask",
+    "llvm.x86.avx512.mask.psrl.di.128" => "__builtin_ia32_psrldi128_mask",
+    "llvm.x86.avx512.mask.psrl.di.256" => "__builtin_ia32_psrldi256_mask",
+    "llvm.x86.avx512.mask.psrl.di.512" => "__builtin_ia32_psrldi512_mask",
+    "llvm.x86.avx512.mask.psrl.q" => "__builtin_ia32_psrlq512_mask",
+    "llvm.x86.avx512.mask.psrl.q.128" => "__builtin_ia32_psrlq128_mask",
+    "llvm.x86.avx512.mask.psrl.q.256" => "__builtin_ia32_psrlq256_mask",
+    "llvm.x86.avx512.mask.psrl.qi.128" => "__builtin_ia32_psrlqi128_mask",
+    "llvm.x86.avx512.mask.psrl.qi.256" => "__builtin_ia32_psrlqi256_mask",
+    "llvm.x86.avx512.mask.psrl.qi.512" => "__builtin_ia32_psrlqi512_mask",
+    "llvm.x86.avx512.mask.psrl.w.128" => "__builtin_ia32_psrlw128_mask",
+    "llvm.x86.avx512.mask.psrl.w.256" => "__builtin_ia32_psrlw256_mask",
+    "llvm.x86.avx512.mask.psrl.w.512" => "__builtin_ia32_psrlw512_mask",
+    "llvm.x86.avx512.mask.psrl.wi.128" => "__builtin_ia32_psrlwi128_mask",
+    "llvm.x86.avx512.mask.psrl.wi.256" => "__builtin_ia32_psrlwi256_mask",
+    "llvm.x86.avx512.mask.psrl.wi.512" => "__builtin_ia32_psrlwi512_mask",
+    "llvm.x86.avx512.mask.psrlv.d" => "__builtin_ia32_psrlv16si_mask",
+    "llvm.x86.avx512.mask.psrlv.q" => "__builtin_ia32_psrlv8di_mask",
+    "llvm.x86.avx512.mask.psrlv16.hi" => "__builtin_ia32_psrlv16hi_mask",
+    "llvm.x86.avx512.mask.psrlv2.di" => "__builtin_ia32_psrlv2di_mask",
+    "llvm.x86.avx512.mask.psrlv32hi" => "__builtin_ia32_psrlv32hi_mask",
+    "llvm.x86.avx512.mask.psrlv4.di" => "__builtin_ia32_psrlv4di_mask",
+    "llvm.x86.avx512.mask.psrlv4.si" => "__builtin_ia32_psrlv4si_mask",
+    "llvm.x86.avx512.mask.psrlv8.hi" => "__builtin_ia32_psrlv8hi_mask",
+    "llvm.x86.avx512.mask.psrlv8.si" => "__builtin_ia32_psrlv8si_mask",
+    "llvm.x86.avx512.mask.psub.b.128" => "__builtin_ia32_psubb128_mask",
+    "llvm.x86.avx512.mask.psub.b.256" => "__builtin_ia32_psubb256_mask",
+    "llvm.x86.avx512.mask.psub.b.512" => "__builtin_ia32_psubb512_mask",
+    "llvm.x86.avx512.mask.psub.d.128" => "__builtin_ia32_psubd128_mask",
+    "llvm.x86.avx512.mask.psub.d.256" => "__builtin_ia32_psubd256_mask",
+    "llvm.x86.avx512.mask.psub.d.512" => "__builtin_ia32_psubd512_mask",
+    "llvm.x86.avx512.mask.psub.q.128" => "__builtin_ia32_psubq128_mask",
+    "llvm.x86.avx512.mask.psub.q.256" => "__builtin_ia32_psubq256_mask",
+    "llvm.x86.avx512.mask.psub.q.512" => "__builtin_ia32_psubq512_mask",
+    "llvm.x86.avx512.mask.psub.w.128" => "__builtin_ia32_psubw128_mask",
+    "llvm.x86.avx512.mask.psub.w.256" => "__builtin_ia32_psubw256_mask",
+    "llvm.x86.avx512.mask.psub.w.512" => "__builtin_ia32_psubw512_mask",
+    "llvm.x86.avx512.mask.psubs.b.128" => "__builtin_ia32_psubsb128_mask",
+    "llvm.x86.avx512.mask.psubs.b.256" => "__builtin_ia32_psubsb256_mask",
+    "llvm.x86.avx512.mask.psubs.b.512" => "__builtin_ia32_psubsb512_mask",
+    "llvm.x86.avx512.mask.psubs.w.128" => "__builtin_ia32_psubsw128_mask",
+    "llvm.x86.avx512.mask.psubs.w.256" => "__builtin_ia32_psubsw256_mask",
+    "llvm.x86.avx512.mask.psubs.w.512" => "__builtin_ia32_psubsw512_mask",
+    "llvm.x86.avx512.mask.psubus.b.128" => "__builtin_ia32_psubusb128_mask",
+    "llvm.x86.avx512.mask.psubus.b.256" => "__builtin_ia32_psubusb256_mask",
+    "llvm.x86.avx512.mask.psubus.b.512" => "__builtin_ia32_psubusb512_mask",
+    "llvm.x86.avx512.mask.psubus.w.128" => "__builtin_ia32_psubusw128_mask",
+    "llvm.x86.avx512.mask.psubus.w.256" => "__builtin_ia32_psubusw256_mask",
+    "llvm.x86.avx512.mask.psubus.w.512" => "__builtin_ia32_psubusw512_mask",
+    "llvm.x86.avx512.mask.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask",
+    "llvm.x86.avx512.mask.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask",
+    "llvm.x86.avx512.mask.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask",
+    "llvm.x86.avx512.mask.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask",
+    "llvm.x86.avx512.mask.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask",
+    "llvm.x86.avx512.mask.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask",
+    "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512",
+    "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512",
+    "llvm.x86.avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask",
+    "llvm.x86.avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask",
+    "llvm.x86.avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask",
+    "llvm.x86.avx512.mask.range.ps.128" => "__builtin_ia32_rangeps128_mask",
+    "llvm.x86.avx512.mask.range.ps.256" => "__builtin_ia32_rangeps256_mask",
+    "llvm.x86.avx512.mask.range.ps.512" => "__builtin_ia32_rangeps512_mask",
+    "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask",
+    "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask",
+    "llvm.x86.avx512.mask.reduce.pd.128" => "__builtin_ia32_reducepd128_mask",
+    "llvm.x86.avx512.mask.reduce.pd.256" => "__builtin_ia32_reducepd256_mask",
+    "llvm.x86.avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask",
+    "llvm.x86.avx512.mask.reduce.ps.128" => "__builtin_ia32_reduceps128_mask",
+    "llvm.x86.avx512.mask.reduce.ps.256" => "__builtin_ia32_reduceps256_mask",
+    "llvm.x86.avx512.mask.reduce.ps.512" => "__builtin_ia32_reduceps512_mask",
+    "llvm.x86.avx512.mask.reduce.sd" => "__builtin_ia32_reducesd_mask",
+    "llvm.x86.avx512.mask.reduce.ss" => "__builtin_ia32_reducess_mask",
+    "llvm.x86.avx512.mask.rndscale.pd.128" => "__builtin_ia32_rndscalepd_128_mask",
+    "llvm.x86.avx512.mask.rndscale.pd.256" => "__builtin_ia32_rndscalepd_256_mask",
+    "llvm.x86.avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask",
+    "llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask",
+    "llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask",
+    "llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask",
+    "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask",
+    "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask",
+    "llvm.x86.avx512.mask.scalef.pd.128" => "__builtin_ia32_scalefpd128_mask",
+    "llvm.x86.avx512.mask.scalef.pd.256" => "__builtin_ia32_scalefpd256_mask",
+    "llvm.x86.avx512.mask.scalef.pd.512" => "__builtin_ia32_scalefpd512_mask",
+    "llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask",
+    "llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask",
+    "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask",
+    "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask",
+    "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask",
+    "llvm.x86.avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask",
+    "llvm.x86.avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask",
+    "llvm.x86.avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask",
+    "llvm.x86.avx512.mask.shuf.f64x2.256" => "__builtin_ia32_shuf_f64x2_256_mask",
+    "llvm.x86.avx512.mask.shuf.i32x4" => "__builtin_ia32_shuf_i32x4_mask",
+    "llvm.x86.avx512.mask.shuf.i32x4.256" => "__builtin_ia32_shuf_i32x4_256_mask",
+    "llvm.x86.avx512.mask.shuf.i64x2" => "__builtin_ia32_shuf_i64x2_mask",
+    "llvm.x86.avx512.mask.shuf.i64x2.256" => "__builtin_ia32_shuf_i64x2_256_mask",
+    "llvm.x86.avx512.mask.shuf.pd.128" => "__builtin_ia32_shufpd128_mask",
+    "llvm.x86.avx512.mask.shuf.pd.256" => "__builtin_ia32_shufpd256_mask",
+    "llvm.x86.avx512.mask.shuf.pd.512" => "__builtin_ia32_shufpd512_mask",
+    "llvm.x86.avx512.mask.shuf.ps.128" => "__builtin_ia32_shufps128_mask",
+    "llvm.x86.avx512.mask.shuf.ps.256" => "__builtin_ia32_shufps256_mask",
+    "llvm.x86.avx512.mask.shuf.ps.512" => "__builtin_ia32_shufps512_mask",
+    "llvm.x86.avx512.mask.sqrt.pd.128" => "__builtin_ia32_sqrtpd128_mask",
+    "llvm.x86.avx512.mask.sqrt.pd.256" => "__builtin_ia32_sqrtpd256_mask",
+    "llvm.x86.avx512.mask.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask",
+    "llvm.x86.avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask",
+    "llvm.x86.avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask",
+    "llvm.x86.avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
+    "llvm.x86.avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask",
+    "llvm.x86.avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask",
+    "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask",
+    "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask",
+    "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask",
+    "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask",
+    "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask",
+    "llvm.x86.avx512.mask.sub.pd.128" => "__builtin_ia32_subpd128_mask",
+    "llvm.x86.avx512.mask.sub.pd.256" => "__builtin_ia32_subpd256_mask",
+    "llvm.x86.avx512.mask.sub.pd.512" => "__builtin_ia32_subpd512_mask",
+    "llvm.x86.avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask",
+    "llvm.x86.avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask",
+    "llvm.x86.avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask",
+    "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask",
+    "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask",
+    "llvm.x86.avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask",
+    "llvm.x86.avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask",
+    "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask",
+    "llvm.x86.avx512.mask.valign.q.128" => "__builtin_ia32_alignq128_mask",
+    "llvm.x86.avx512.mask.valign.q.256" => "__builtin_ia32_alignq256_mask",
+    "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask",
+    "llvm.x86.avx512.mask.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps_mask",
+    "llvm.x86.avx512.mask.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256_mask",
+    "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask",
+    "llvm.x86.avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask",
+    "llvm.x86.avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask",
+    "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask",
+    "llvm.x86.avx512.mask.vextractf32x4.256" => "__builtin_ia32_extractf32x4_256_mask",
+    "llvm.x86.avx512.mask.vextractf32x4.512" => "__builtin_ia32_extractf32x4_mask",
+    "llvm.x86.avx512.mask.vextractf32x8.512" => "__builtin_ia32_extractf32x8_mask",
+    "llvm.x86.avx512.mask.vextractf64x2.256" => "__builtin_ia32_extractf64x2_256_mask",
+    "llvm.x86.avx512.mask.vextractf64x2.512" => "__builtin_ia32_extractf64x2_512_mask",
+    "llvm.x86.avx512.mask.vextractf64x4.512" => "__builtin_ia32_extractf64x4_mask",
+    "llvm.x86.avx512.mask.vextracti32x4.256" => "__builtin_ia32_extracti32x4_256_mask",
+    "llvm.x86.avx512.mask.vextracti32x4.512" => "__builtin_ia32_extracti32x4_mask",
+    "llvm.x86.avx512.mask.vextracti32x8.512" => "__builtin_ia32_extracti32x8_mask",
+    "llvm.x86.avx512.mask.vextracti64x2.256" => "__builtin_ia32_extracti64x2_256_mask",
+    "llvm.x86.avx512.mask.vextracti64x2.512" => "__builtin_ia32_extracti64x2_512_mask",
+    "llvm.x86.avx512.mask.vextracti64x4.512" => "__builtin_ia32_extracti64x4_mask",
+    "llvm.x86.avx512.mask.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask",
+    "llvm.x86.avx512.mask.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask",
+    "llvm.x86.avx512.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask",
+    "llvm.x86.avx512.mask.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask",
+    "llvm.x86.avx512.mask.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask",
+    "llvm.x86.avx512.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask",
+    "llvm.x86.avx512.mask.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask",
+    "llvm.x86.avx512.mask.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask",
+    "llvm.x86.avx512.mask.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask",
+    "llvm.x86.avx512.mask.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask",
+    "llvm.x86.avx512.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask",
+    "llvm.x86.avx512.mask.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask",
+    "llvm.x86.avx512.mask.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask",
+    "llvm.x86.avx512.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask",
+    "llvm.x86.avx512.mask.vfnmadd.pd.128" => "__builtin_ia32_vfnmaddpd128_mask",
+    "llvm.x86.avx512.mask.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256_mask",
+    "llvm.x86.avx512.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask",
+    "llvm.x86.avx512.mask.vfnmadd.ps.128" => "__builtin_ia32_vfnmaddps128_mask",
+    "llvm.x86.avx512.mask.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256_mask",
+    "llvm.x86.avx512.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask",
+    "llvm.x86.avx512.mask.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask",
+    "llvm.x86.avx512.mask.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask",
+    "llvm.x86.avx512.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask",
+    "llvm.x86.avx512.mask.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask",
+    "llvm.x86.avx512.mask.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask",
+    "llvm.x86.avx512.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask",
+    "llvm.x86.avx512.mask.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128_mask",
+    "llvm.x86.avx512.mask.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256_mask",
+    "llvm.x86.avx512.mask.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512_mask",
+    "llvm.x86.avx512.mask.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128_mask",
+    "llvm.x86.avx512.mask.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256_mask",
+    "llvm.x86.avx512.mask.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512_mask",
+    "llvm.x86.avx512.mask.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128_mask",
+    "llvm.x86.avx512.mask.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256_mask",
+    "llvm.x86.avx512.mask.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512_mask",
+    "llvm.x86.avx512.mask.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128_mask",
+    "llvm.x86.avx512.mask.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256_mask",
+    "llvm.x86.avx512.mask.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512_mask",
+    "llvm.x86.avx512.mask.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128_mask",
+    "llvm.x86.avx512.mask.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256_mask",
+    "llvm.x86.avx512.mask.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512_mask",
+    "llvm.x86.avx512.mask.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128_mask",
+    "llvm.x86.avx512.mask.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256_mask",
+    "llvm.x86.avx512.mask.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512_mask",
+    "llvm.x86.avx512.mask.vpermilvar.pd.128" => "__builtin_ia32_vpermilvarpd_mask",
+    "llvm.x86.avx512.mask.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256_mask",
+    "llvm.x86.avx512.mask.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512_mask",
+    "llvm.x86.avx512.mask.vpermilvar.ps.128" => "__builtin_ia32_vpermilvarps_mask",
+    "llvm.x86.avx512.mask.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256_mask",
+    "llvm.x86.avx512.mask.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512_mask",
+    "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask",
+    "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask",
+    "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask",
+    "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask",
+    "llvm.x86.avx512.mask.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_mask",
+    "llvm.x86.avx512.mask.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_mask",
+    "llvm.x86.avx512.mask.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_mask",
+    "llvm.x86.avx512.mask.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_mask",
+    "llvm.x86.avx512.mask.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_mask",
+    "llvm.x86.avx512.mask.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_mask",
+    "llvm.x86.avx512.mask.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_mask",
+    "llvm.x86.avx512.mask.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_mask",
+    "llvm.x86.avx512.mask.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_mask",
+    "llvm.x86.avx512.mask.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_mask",
+    "llvm.x86.avx512.mask.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_mask",
+    "llvm.x86.avx512.mask.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_mask",
+    "llvm.x86.avx512.mask.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_mask",
+    "llvm.x86.avx512.mask.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_mask",
+    "llvm.x86.avx512.mask.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_mask",
+    "llvm.x86.avx512.mask.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_mask",
+    "llvm.x86.avx512.mask.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_mask",
+    "llvm.x86.avx512.mask.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_mask",
+    "llvm.x86.avx512.mask.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask",
+    "llvm.x86.avx512.mask.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask",
+    "llvm.x86.avx512.mask.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask",
+    "llvm.x86.avx512.mask.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_mask",
+    "llvm.x86.avx512.mask.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask",
+    "llvm.x86.avx512.mask.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask",
+    "llvm.x86.avx512.mask.xor.pd.128" => "__builtin_ia32_xorpd128_mask",
+    "llvm.x86.avx512.mask.xor.pd.256" => "__builtin_ia32_xorpd256_mask",
+    "llvm.x86.avx512.mask.xor.pd.512" => "__builtin_ia32_xorpd512_mask",
+    "llvm.x86.avx512.mask.xor.ps.128" => "__builtin_ia32_xorps128_mask",
+    "llvm.x86.avx512.mask.xor.ps.256" => "__builtin_ia32_xorps256_mask",
+    "llvm.x86.avx512.mask.xor.ps.512" => "__builtin_ia32_xorps512_mask",
+    "llvm.x86.avx512.mask3.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask3",
+    "llvm.x86.avx512.mask3.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask3",
+    "llvm.x86.avx512.mask3.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask3",
+    "llvm.x86.avx512.mask3.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask3",
+    "llvm.x86.avx512.mask3.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask3",
+    "llvm.x86.avx512.mask3.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask3",
+    "llvm.x86.avx512.mask3.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask3",
+    "llvm.x86.avx512.mask3.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask3",
+    "llvm.x86.avx512.mask3.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask3",
+    "llvm.x86.avx512.mask3.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask3",
+    "llvm.x86.avx512.mask3.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask3",
+    "llvm.x86.avx512.mask3.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask3",
+    "llvm.x86.avx512.mask3.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask3",
+    "llvm.x86.avx512.mask3.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask3",
+    "llvm.x86.avx512.mask3.vfmsub.pd.128" => "__builtin_ia32_vfmsubpd128_mask3",
+    "llvm.x86.avx512.mask3.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256_mask3",
+    "llvm.x86.avx512.mask3.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask3",
+    "llvm.x86.avx512.mask3.vfmsub.ps.128" => "__builtin_ia32_vfmsubps128_mask3",
+    "llvm.x86.avx512.mask3.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256_mask3",
+    "llvm.x86.avx512.mask3.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask3",
+    "llvm.x86.avx512.mask3.vfmsubadd.pd.128" => "__builtin_ia32_vfmsubaddpd128_mask3",
+    "llvm.x86.avx512.mask3.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256_mask3",
+    "llvm.x86.avx512.mask3.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask3",
+    "llvm.x86.avx512.mask3.vfmsubadd.ps.128" => "__builtin_ia32_vfmsubaddps128_mask3",
+    "llvm.x86.avx512.mask3.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256_mask3",
+    "llvm.x86.avx512.mask3.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask3",
+    "llvm.x86.avx512.mask3.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask3",
+    "llvm.x86.avx512.mask3.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask3",
+    "llvm.x86.avx512.mask3.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask3",
+    "llvm.x86.avx512.mask3.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask3",
+    "llvm.x86.avx512.mask3.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask3",
+    "llvm.x86.avx512.mask3.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask3",
+    "llvm.x86.avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz",
+    "llvm.x86.avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz",
+    "llvm.x86.avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz",
+    "llvm.x86.avx512.maskz.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_maskz",
+    "llvm.x86.avx512.maskz.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_maskz",
+    "llvm.x86.avx512.maskz.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_maskz",
+    "llvm.x86.avx512.maskz.fixupimm.sd" => "__builtin_ia32_fixupimmsd_maskz",
+    "llvm.x86.avx512.maskz.fixupimm.ss" => "__builtin_ia32_fixupimmss_maskz",
+    "llvm.x86.avx512.maskz.pternlog.d.128" => "__builtin_ia32_pternlogd128_maskz",
+    "llvm.x86.avx512.maskz.pternlog.d.256" => "__builtin_ia32_pternlogd256_maskz",
+    "llvm.x86.avx512.maskz.pternlog.d.512" => "__builtin_ia32_pternlogd512_maskz",
+    "llvm.x86.avx512.maskz.pternlog.q.128" => "__builtin_ia32_pternlogq128_maskz",
+    "llvm.x86.avx512.maskz.pternlog.q.256" => "__builtin_ia32_pternlogq256_maskz",
+    "llvm.x86.avx512.maskz.pternlog.q.512" => "__builtin_ia32_pternlogq512_maskz",
+    "llvm.x86.avx512.maskz.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_maskz",
+    "llvm.x86.avx512.maskz.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_maskz",
+    "llvm.x86.avx512.maskz.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_maskz",
+    "llvm.x86.avx512.maskz.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_maskz",
+    "llvm.x86.avx512.maskz.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_maskz",
+    "llvm.x86.avx512.maskz.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_maskz",
+    "llvm.x86.avx512.maskz.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_maskz",
+    "llvm.x86.avx512.maskz.vfmadd.ss" => "__builtin_ia32_vfmaddss3_maskz",
+    "llvm.x86.avx512.maskz.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_maskz",
+    "llvm.x86.avx512.maskz.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_maskz",
+    "llvm.x86.avx512.maskz.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_maskz",
+    "llvm.x86.avx512.maskz.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_maskz",
+    "llvm.x86.avx512.maskz.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_maskz",
+    "llvm.x86.avx512.maskz.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_maskz",
+    "llvm.x86.avx512.maskz.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_maskz",
+    "llvm.x86.avx512.maskz.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_maskz",
+    "llvm.x86.avx512.maskz.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_maskz",
+    "llvm.x86.avx512.maskz.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_maskz",
+    "llvm.x86.avx512.maskz.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_maskz",
+    "llvm.x86.avx512.maskz.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_maskz",
+    "llvm.x86.avx512.maskz.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_maskz",
+    "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512",
+    "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512",
+    "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512",
+    "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512",
+    "llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512",
+    "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512",
+    "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512",
+    "llvm.x86.avx512.packssdw.512" => "__builtin_ia32_packssdw512",
+    "llvm.x86.avx512.packsswb.512" => "__builtin_ia32_packsswb512",
+    "llvm.x86.avx512.packusdw.512" => "__builtin_ia32_packusdw512",
+    "llvm.x86.avx512.packuswb.512" => "__builtin_ia32_packuswb512",
+    "llvm.x86.avx512.pavg.b.512" => "__builtin_ia32_pavgb512",
+    "llvm.x86.avx512.pavg.w.512" => "__builtin_ia32_pavgw512",
+    "llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512",
+    "llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512",
+    "llvm.x86.avx512.permvar.df.256" => "__builtin_ia32_permvardf256",
+    "llvm.x86.avx512.permvar.df.512" => "__builtin_ia32_permvardf512",
+    "llvm.x86.avx512.permvar.di.256" => "__builtin_ia32_permvardi256",
+    "llvm.x86.avx512.permvar.di.512" => "__builtin_ia32_permvardi512",
+    "llvm.x86.avx512.permvar.hi.128" => "__builtin_ia32_permvarhi128",
+    "llvm.x86.avx512.permvar.hi.256" => "__builtin_ia32_permvarhi256",
+    "llvm.x86.avx512.permvar.hi.512" => "__builtin_ia32_permvarhi512",
+    "llvm.x86.avx512.permvar.qi.128" => "__builtin_ia32_permvarqi128",
+    "llvm.x86.avx512.permvar.qi.256" => "__builtin_ia32_permvarqi256",
+    "llvm.x86.avx512.permvar.qi.512" => "__builtin_ia32_permvarqi512",
+    "llvm.x86.avx512.permvar.sf.512" => "__builtin_ia32_permvarsf512",
+    "llvm.x86.avx512.permvar.si.512" => "__builtin_ia32_permvarsi512",
+    "llvm.x86.avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512",
+    "llvm.x86.avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512",
+    "llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512",
+    "llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512",
+    "llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512",
+    "llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512",
+    "llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512",
+    "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512",
+    "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512",
+    "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512",
+    "llvm.x86.avx512.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128",
+    "llvm.x86.avx512.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256",
+    "llvm.x86.avx512.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512",
+    "llvm.x86.avx512.psad.bw.512" => "__builtin_ia32_psadbw512",
+    "llvm.x86.avx512.pshuf.b.512" => "__builtin_ia32_pshufb512",
+    "llvm.x86.avx512.psll.d.512" => "__builtin_ia32_pslld512",
+    "llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512",
+    "llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift",
+    "llvm.x86.avx512.psll.q.512" => "__builtin_ia32_psllq512",
+    "llvm.x86.avx512.psll.w.512" => "__builtin_ia32_psllw512",
+    "llvm.x86.avx512.pslli.d.512" => "__builtin_ia32_pslldi512",
+    "llvm.x86.avx512.pslli.q.512" => "__builtin_ia32_psllqi512",
+    "llvm.x86.avx512.pslli.w.512" => "__builtin_ia32_psllwi512",
+    "llvm.x86.avx512.psllv.d.512" => "__builtin_ia32_psllv16si",
+    "llvm.x86.avx512.psllv.q.512" => "__builtin_ia32_psllv8di",
+    "llvm.x86.avx512.psllv.w.128" => "__builtin_ia32_psllv8hi",
+    "llvm.x86.avx512.psllv.w.256" => "__builtin_ia32_psllv16hi",
+    "llvm.x86.avx512.psllv.w.512" => "__builtin_ia32_psllv32hi",
+    "llvm.x86.avx512.psra.d.512" => "__builtin_ia32_psrad512",
+    "llvm.x86.avx512.psra.q.128" => "__builtin_ia32_psraq128",
+    "llvm.x86.avx512.psra.q.256" => "__builtin_ia32_psraq256",
+    "llvm.x86.avx512.psra.q.512" => "__builtin_ia32_psraq512",
+    "llvm.x86.avx512.psra.w.512" => "__builtin_ia32_psraw512",
+    "llvm.x86.avx512.psrai.d.512" => "__builtin_ia32_psradi512",
+    "llvm.x86.avx512.psrai.q.128" => "__builtin_ia32_psraqi128",
+    "llvm.x86.avx512.psrai.q.256" => "__builtin_ia32_psraqi256",
+    "llvm.x86.avx512.psrai.q.512" => "__builtin_ia32_psraqi512",
+    "llvm.x86.avx512.psrai.w.512" => "__builtin_ia32_psrawi512",
+    "llvm.x86.avx512.psrav.d.512" => "__builtin_ia32_psrav16si",
+    "llvm.x86.avx512.psrav.q.128" => "__builtin_ia32_psravq128",
+    "llvm.x86.avx512.psrav.q.256" => "__builtin_ia32_psravq256",
+    "llvm.x86.avx512.psrav.q.512" => "__builtin_ia32_psrav8di",
+    "llvm.x86.avx512.psrav.w.128" => "__builtin_ia32_psrav8hi",
+    "llvm.x86.avx512.psrav.w.256" => "__builtin_ia32_psrav16hi",
+    "llvm.x86.avx512.psrav.w.512" => "__builtin_ia32_psrav32hi",
+    "llvm.x86.avx512.psrl.d.512" => "__builtin_ia32_psrld512",
+    "llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512",
+    "llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift",
+    "llvm.x86.avx512.psrl.q.512" => "__builtin_ia32_psrlq512",
+    "llvm.x86.avx512.psrl.w.512" => "__builtin_ia32_psrlw512",
+    "llvm.x86.avx512.psrli.d.512" => "__builtin_ia32_psrldi512",
+    "llvm.x86.avx512.psrli.q.512" => "__builtin_ia32_psrlqi512",
+    "llvm.x86.avx512.psrli.w.512" => "__builtin_ia32_psrlwi512",
+    "llvm.x86.avx512.psrlv.d.512" => "__builtin_ia32_psrlv16si",
+    "llvm.x86.avx512.psrlv.q.512" => "__builtin_ia32_psrlv8di",
+    "llvm.x86.avx512.psrlv.w.128" => "__builtin_ia32_psrlv8hi",
+    "llvm.x86.avx512.psrlv.w.256" => "__builtin_ia32_psrlv16hi",
+    "llvm.x86.avx512.psrlv.w.512" => "__builtin_ia32_psrlv32hi",
+    "llvm.x86.avx512.pternlog.d.128" => "__builtin_ia32_pternlogd128",
+    "llvm.x86.avx512.pternlog.d.256" => "__builtin_ia32_pternlogd256",
+    "llvm.x86.avx512.pternlog.d.512" => "__builtin_ia32_pternlogd512",
+    "llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128",
+    "llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256",
+    "llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512",
+    "llvm.x86.avx512.ptestm.b.128" => "__builtin_ia32_ptestmb128",
+    "llvm.x86.avx512.ptestm.b.256" => "__builtin_ia32_ptestmb256",
+    "llvm.x86.avx512.ptestm.b.512" => "__builtin_ia32_ptestmb512",
+    "llvm.x86.avx512.ptestm.d.128" => "__builtin_ia32_ptestmd128",
+    "llvm.x86.avx512.ptestm.d.256" => "__builtin_ia32_ptestmd256",
+    "llvm.x86.avx512.ptestm.d.512" => "__builtin_ia32_ptestmd512",
+    "llvm.x86.avx512.ptestm.q.128" => "__builtin_ia32_ptestmq128",
+    "llvm.x86.avx512.ptestm.q.256" => "__builtin_ia32_ptestmq256",
+    "llvm.x86.avx512.ptestm.q.512" => "__builtin_ia32_ptestmq512",
+    "llvm.x86.avx512.ptestm.w.128" => "__builtin_ia32_ptestmw128",
+    "llvm.x86.avx512.ptestm.w.256" => "__builtin_ia32_ptestmw256",
+    "llvm.x86.avx512.ptestm.w.512" => "__builtin_ia32_ptestmw512",
+    "llvm.x86.avx512.ptestnm.b.128" => "__builtin_ia32_ptestnmb128",
+    "llvm.x86.avx512.ptestnm.b.256" => "__builtin_ia32_ptestnmb256",
+    "llvm.x86.avx512.ptestnm.b.512" => "__builtin_ia32_ptestnmb512",
+    "llvm.x86.avx512.ptestnm.d.128" => "__builtin_ia32_ptestnmd128",
+    "llvm.x86.avx512.ptestnm.d.256" => "__builtin_ia32_ptestnmd256",
+    "llvm.x86.avx512.ptestnm.d.512" => "__builtin_ia32_ptestnmd512",
+    "llvm.x86.avx512.ptestnm.q.128" => "__builtin_ia32_ptestnmq128",
+    "llvm.x86.avx512.ptestnm.q.256" => "__builtin_ia32_ptestnmq256",
+    "llvm.x86.avx512.ptestnm.q.512" => "__builtin_ia32_ptestnmq512",
+    "llvm.x86.avx512.ptestnm.w.128" => "__builtin_ia32_ptestnmw128",
+    "llvm.x86.avx512.ptestnm.w.256" => "__builtin_ia32_ptestnmw256",
+    "llvm.x86.avx512.ptestnm.w.512" => "__builtin_ia32_ptestnmw512",
+    "llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask",
+    "llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask",
+    "llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask",
+    "llvm.x86.avx512.rcp14.ps.128" => "__builtin_ia32_rcp14ps128_mask",
+    "llvm.x86.avx512.rcp14.ps.256" => "__builtin_ia32_rcp14ps256_mask",
+    "llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask",
+    "llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask",
+    "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask",
+    "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask",
+    "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask",
+    "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask",
+    // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask",
+    "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask",
+    // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask",
+    "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd",
+    "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless",
+    "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask",
+    "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask",
+    "llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask",
+    "llvm.x86.avx512.rsqrt14.ps.128" => "__builtin_ia32_rsqrt14ps128_mask",
+    "llvm.x86.avx512.rsqrt14.ps.256" => "__builtin_ia32_rsqrt14ps256_mask",
+    "llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask",
+    "llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask",
+    "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask",
+    "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask",
+    "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask",
+    "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask",
+    // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask",
+    "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask",
+    // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask",
+    "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df",
+    "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si",
+    "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di",
+    "llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf",
+    "llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df",
+    "llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si",
+    "llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di",
+    "llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf",
+    "llvm.x86.avx512.scatterdiv2.df" => "__builtin_ia32_scatterdiv2df",
+    "llvm.x86.avx512.scatterdiv2.di" => "__builtin_ia32_scatterdiv2di",
+    "llvm.x86.avx512.scatterdiv4.df" => "__builtin_ia32_scatterdiv4df",
+    "llvm.x86.avx512.scatterdiv4.di" => "__builtin_ia32_scatterdiv4di",
+    "llvm.x86.avx512.scatterdiv4.sf" => "__builtin_ia32_scatterdiv4sf",
+    "llvm.x86.avx512.scatterdiv4.si" => "__builtin_ia32_scatterdiv4si",
+    "llvm.x86.avx512.scatterdiv8.sf" => "__builtin_ia32_scatterdiv8sf",
+    "llvm.x86.avx512.scatterdiv8.si" => "__builtin_ia32_scatterdiv8si",
+    "llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd",
+    "llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps",
+    "llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd",
+    "llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps",
+    "llvm.x86.avx512.scattersiv2.df" => "__builtin_ia32_scattersiv2df",
+    "llvm.x86.avx512.scattersiv2.di" => "__builtin_ia32_scattersiv2di",
+    "llvm.x86.avx512.scattersiv4.df" => "__builtin_ia32_scattersiv4df",
+    "llvm.x86.avx512.scattersiv4.di" => "__builtin_ia32_scattersiv4di",
+    "llvm.x86.avx512.scattersiv4.sf" => "__builtin_ia32_scattersiv4sf",
+    "llvm.x86.avx512.scattersiv4.si" => "__builtin_ia32_scattersiv4si",
+    "llvm.x86.avx512.scattersiv8.sf" => "__builtin_ia32_scattersiv8sf",
+    "llvm.x86.avx512.scattersiv8.si" => "__builtin_ia32_scattersiv8si",
+    "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask",
+    "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
+    "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd",
+    "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss",
+    "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512",
+    "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512",
+    "llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512",
+    "llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512",
+    "llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512",
+    "llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512",
+    "llvm.x86.avx512.vcomi.sd" => "__builtin_ia32_vcomisd",
+    "llvm.x86.avx512.vcomi.ss" => "__builtin_ia32_vcomiss",
+    "llvm.x86.avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32",
+    "llvm.x86.avx512.vcvtsd2si64" => "__builtin_ia32_vcvtsd2si64",
+    "llvm.x86.avx512.vcvtsd2usi32" => "__builtin_ia32_vcvtsd2usi32",
+    "llvm.x86.avx512.vcvtsd2usi64" => "__builtin_ia32_vcvtsd2usi64",
+    "llvm.x86.avx512.vcvtss2si32" => "__builtin_ia32_vcvtss2si32",
+    "llvm.x86.avx512.vcvtss2si64" => "__builtin_ia32_vcvtss2si64",
+    "llvm.x86.avx512.vcvtss2usi32" => "__builtin_ia32_vcvtss2usi32",
+    "llvm.x86.avx512.vcvtss2usi64" => "__builtin_ia32_vcvtss2usi64",
+    "llvm.x86.avx512.vpdpbusd.128" => "__builtin_ia32_vpdpbusd128",
+    "llvm.x86.avx512.vpdpbusd.256" => "__builtin_ia32_vpdpbusd256",
+    "llvm.x86.avx512.vpdpbusd.512" => "__builtin_ia32_vpdpbusd512",
+    "llvm.x86.avx512.vpdpbusds.128" => "__builtin_ia32_vpdpbusds128",
+    "llvm.x86.avx512.vpdpbusds.256" => "__builtin_ia32_vpdpbusds256",
+    "llvm.x86.avx512.vpdpbusds.512" => "__builtin_ia32_vpdpbusds512",
+    "llvm.x86.avx512.vpdpwssd.128" => "__builtin_ia32_vpdpwssd128",
+    "llvm.x86.avx512.vpdpwssd.256" => "__builtin_ia32_vpdpwssd256",
+    "llvm.x86.avx512.vpdpwssd.512" => "__builtin_ia32_vpdpwssd512",
+    "llvm.x86.avx512.vpdpwssds.128" => "__builtin_ia32_vpdpwssds128",
+    "llvm.x86.avx512.vpdpwssds.256" => "__builtin_ia32_vpdpwssds256",
+    "llvm.x86.avx512.vpdpwssds.512" => "__builtin_ia32_vpdpwssds512",
+    "llvm.x86.avx512.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128",
+    "llvm.x86.avx512.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256",
+    "llvm.x86.avx512.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512",
+    "llvm.x86.avx512.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128",
+    "llvm.x86.avx512.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256",
+    "llvm.x86.avx512.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512",
+    "llvm.x86.avx512.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128",
+    "llvm.x86.avx512.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256",
+    "llvm.x86.avx512.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512",
+    "llvm.x86.avx512.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128",
+    "llvm.x86.avx512.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256",
+    "llvm.x86.avx512.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512",
+    "llvm.x86.avx512.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128",
+    "llvm.x86.avx512.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256",
+    "llvm.x86.avx512.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512",
+    "llvm.x86.avx512.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128",
+    "llvm.x86.avx512.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256",
+    "llvm.x86.avx512.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512",
+    "llvm.x86.avx512.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512",
+    "llvm.x86.avx512.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512",
+    "llvm.x86.avx512.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128",
+    "llvm.x86.avx512.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256",
+    "llvm.x86.avx512.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512",
+    "llvm.x86.avx512.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128",
+    "llvm.x86.avx512.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256",
+    "llvm.x86.avx512.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512",
+    "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_128",
+    "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_256",
+    "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_512",
+    "llvm.x86.avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_256",
+    "llvm.x86.avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_512",
+    "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_128",
+    "llvm.x86.avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_256",
+    "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_512",
+    "llvm.x86.avx512fp16.add.ph.512" => "__builtin_ia32_addph512",
+    "llvm.x86.avx512fp16.div.ph.512" => "__builtin_ia32_divph512",
+    "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask",
+    "llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask",
+    "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask",
+    "llvm.x86.avx512fp16.mask.fpclass.sh" => "__builtin_ia32_fpclasssh_mask",
+    "llvm.x86.avx512fp16.mask.getexp.ph.128" => "__builtin_ia32_getexpph128_mask",
+    "llvm.x86.avx512fp16.mask.getexp.ph.256" => "__builtin_ia32_getexpph256_mask",
+    "llvm.x86.avx512fp16.mask.getexp.ph.512" => "__builtin_ia32_getexpph512_mask",
+    "llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask",
+    "llvm.x86.avx512fp16.mask.getmant.ph.128" => "__builtin_ia32_getmantph128_mask",
+    "llvm.x86.avx512fp16.mask.getmant.ph.256" => "__builtin_ia32_getmantph256_mask",
+    "llvm.x86.avx512fp16.mask.getmant.ph.512" => "__builtin_ia32_getmantph512_mask",
+    "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask",
+    "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask",
+    "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask",
+    "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask",
+    "llvm.x86.avx512fp16.mask.rcp.ph.128" => "__builtin_ia32_rcpph128_mask",
+    "llvm.x86.avx512fp16.mask.rcp.ph.256" => "__builtin_ia32_rcpph256_mask",
+    "llvm.x86.avx512fp16.mask.rcp.ph.512" => "__builtin_ia32_rcpph512_mask",
+    "llvm.x86.avx512fp16.mask.rcp.sh" => "__builtin_ia32_rcpsh_mask",
+    "llvm.x86.avx512fp16.mask.reduce.ph.128" => "__builtin_ia32_reduceph128_mask",
+    "llvm.x86.avx512fp16.mask.reduce.ph.256" => "__builtin_ia32_reduceph256_mask",
+    "llvm.x86.avx512fp16.mask.reduce.ph.512" => "__builtin_ia32_reduceph512_mask",
+    "llvm.x86.avx512fp16.mask.reduce.sh" => "__builtin_ia32_reducesh_mask",
+    "llvm.x86.avx512fp16.mask.rndscale.ph.128" => "__builtin_ia32_rndscaleph_128_mask",
+    "llvm.x86.avx512fp16.mask.rndscale.ph.256" => "__builtin_ia32_rndscaleph_256_mask",
+    "llvm.x86.avx512fp16.mask.rndscale.ph.512" => "__builtin_ia32_rndscaleph_mask",
+    "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask",
+    "llvm.x86.avx512fp16.mask.rsqrt.ph.128" => "__builtin_ia32_rsqrtph128_mask",
+    "llvm.x86.avx512fp16.mask.rsqrt.ph.256" => "__builtin_ia32_rsqrtph256_mask",
+    "llvm.x86.avx512fp16.mask.rsqrt.ph.512" => "__builtin_ia32_rsqrtph512_mask",
+    "llvm.x86.avx512fp16.mask.rsqrt.sh" => "__builtin_ia32_rsqrtsh_mask",
+    "llvm.x86.avx512fp16.mask.scalef.ph.128" => "__builtin_ia32_scalefph128_mask",
+    "llvm.x86.avx512fp16.mask.scalef.ph.256" => "__builtin_ia32_scalefph256_mask",
+    "llvm.x86.avx512fp16.mask.scalef.ph.512" => "__builtin_ia32_scalefph512_mask",
+    "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask",
+    "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask",
+    "llvm.x86.avx512fp16.mask.vcvtdq2ph.128" => "__builtin_ia32_vcvtdq2ph128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtpd2ph.128" => "__builtin_ia32_vcvtpd2ph128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtpd2ph.256" => "__builtin_ia32_vcvtpd2ph256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtpd2ph.512" => "__builtin_ia32_vcvtpd2ph512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2dq.128" => "__builtin_ia32_vcvtph2dq128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2dq.256" => "__builtin_ia32_vcvtph2dq256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2dq.512" => "__builtin_ia32_vcvtph2dq512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2pd.128" => "__builtin_ia32_vcvtph2pd128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2pd.256" => "__builtin_ia32_vcvtph2pd256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2pd.512" => "__builtin_ia32_vcvtph2pd512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2psx.128" => "__builtin_ia32_vcvtph2psx128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2psx.256" => "__builtin_ia32_vcvtph2psx256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2psx.512" => "__builtin_ia32_vcvtph2psx512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2qq.128" => "__builtin_ia32_vcvtph2qq128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2qq.256" => "__builtin_ia32_vcvtph2qq256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2qq.512" => "__builtin_ia32_vcvtph2qq512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2udq.128" => "__builtin_ia32_vcvtph2udq128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2udq.256" => "__builtin_ia32_vcvtph2udq256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2udq.512" => "__builtin_ia32_vcvtph2udq512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2uqq.128" => "__builtin_ia32_vcvtph2uqq128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2uqq.256" => "__builtin_ia32_vcvtph2uqq256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2uqq.512" => "__builtin_ia32_vcvtph2uqq512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2uw.128" => "__builtin_ia32_vcvtph2uw128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2uw.256" => "__builtin_ia32_vcvtph2uw256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2uw.512" => "__builtin_ia32_vcvtph2uw512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2w.128" => "__builtin_ia32_vcvtph2w128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2w.256" => "__builtin_ia32_vcvtph2w256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtph2w.512" => "__builtin_ia32_vcvtph2w512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtps2phx.128" => "__builtin_ia32_vcvtps2phx128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtps2phx.256" => "__builtin_ia32_vcvtps2phx256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtps2phx.512" => "__builtin_ia32_vcvtps2phx512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtqq2ph.128" => "__builtin_ia32_vcvtqq2ph128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtqq2ph.256" => "__builtin_ia32_vcvtqq2ph256_mask",
+    "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask",
+    "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask",
+    "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask",
+    "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2dq.128" => "__builtin_ia32_vcvttph2dq128_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2dq.256" => "__builtin_ia32_vcvttph2dq256_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2dq.512" => "__builtin_ia32_vcvttph2dq512_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2qq.128" => "__builtin_ia32_vcvttph2qq128_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2qq.256" => "__builtin_ia32_vcvttph2qq256_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2qq.512" => "__builtin_ia32_vcvttph2qq512_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2udq.128" => "__builtin_ia32_vcvttph2udq128_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2udq.256" => "__builtin_ia32_vcvttph2udq256_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2udq.512" => "__builtin_ia32_vcvttph2udq512_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2uqq.128" => "__builtin_ia32_vcvttph2uqq128_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2uqq.256" => "__builtin_ia32_vcvttph2uqq256_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2uqq.512" => "__builtin_ia32_vcvttph2uqq512_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2uw.128" => "__builtin_ia32_vcvttph2uw128_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2uw.256" => "__builtin_ia32_vcvttph2uw256_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2uw.512" => "__builtin_ia32_vcvttph2uw512_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2w.128" => "__builtin_ia32_vcvttph2w128_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2w.256" => "__builtin_ia32_vcvttph2w256_mask",
+    "llvm.x86.avx512fp16.mask.vcvttph2w.512" => "__builtin_ia32_vcvttph2w512_mask",
+    "llvm.x86.avx512fp16.mask.vcvtudq2ph.128" => "__builtin_ia32_vcvtudq2ph128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtuqq2ph.128" => "__builtin_ia32_vcvtuqq2ph128_mask",
+    "llvm.x86.avx512fp16.mask.vcvtuqq2ph.256" => "__builtin_ia32_vcvtuqq2ph256_mask",
+    "llvm.x86.avx512fp16.mask.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_mask",
+    "llvm.x86.avx512fp16.mask.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_mask",
+    "llvm.x86.avx512fp16.mask.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_mask3",
+    "llvm.x86.avx512fp16.mask.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_mask",
+    "llvm.x86.avx512fp16.mask.vfcmul.cph.128" => "__builtin_ia32_vfcmulcph128_mask",
+    "llvm.x86.avx512fp16.mask.vfcmul.cph.256" => "__builtin_ia32_vfcmulcph256_mask",
+    "llvm.x86.avx512fp16.mask.vfcmul.cph.512" => "__builtin_ia32_vfcmulcph512_mask",
+    "llvm.x86.avx512fp16.mask.vfcmul.csh" => "__builtin_ia32_vfcmulcsh_mask",
+    "llvm.x86.avx512fp16.mask.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_mask",
+    "llvm.x86.avx512fp16.mask.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_mask",
+    "llvm.x86.avx512fp16.mask.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_mask3",
+    "llvm.x86.avx512fp16.mask.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_mask",
+    "llvm.x86.avx512fp16.mask.vfmul.cph.128" => "__builtin_ia32_vfmulcph128_mask",
+    "llvm.x86.avx512fp16.mask.vfmul.cph.256" => "__builtin_ia32_vfmulcph256_mask",
+    "llvm.x86.avx512fp16.mask.vfmul.cph.512" => "__builtin_ia32_vfmulcph512_mask",
+    "llvm.x86.avx512fp16.mask.vfmul.csh" => "__builtin_ia32_vfmulcsh_mask",
+    "llvm.x86.avx512fp16.maskz.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_maskz",
+    "llvm.x86.avx512fp16.maskz.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_maskz",
+    "llvm.x86.avx512fp16.maskz.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_maskz",
+    "llvm.x86.avx512fp16.maskz.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_maskz",
+    "llvm.x86.avx512fp16.maskz.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_maskz",
+    "llvm.x86.avx512fp16.maskz.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_maskz",
+    "llvm.x86.avx512fp16.maskz.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_maskz",
+    "llvm.x86.avx512fp16.maskz.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_maskz",
+    "llvm.x86.avx512fp16.max.ph.128" => "__builtin_ia32_maxph128",
+    "llvm.x86.avx512fp16.max.ph.256" => "__builtin_ia32_maxph256",
+    "llvm.x86.avx512fp16.max.ph.512" => "__builtin_ia32_maxph512",
+    "llvm.x86.avx512fp16.min.ph.128" => "__builtin_ia32_minph128",
+    "llvm.x86.avx512fp16.min.ph.256" => "__builtin_ia32_minph256",
+    "llvm.x86.avx512fp16.min.ph.512" => "__builtin_ia32_minph512",
+    "llvm.x86.avx512fp16.mul.ph.512" => "__builtin_ia32_mulph512",
+    "llvm.x86.avx512fp16.sub.ph.512" => "__builtin_ia32_subph512",
+    "llvm.x86.avx512fp16.vcomi.sh" => "__builtin_ia32_vcomish",
+    "llvm.x86.avx512fp16.vcvtsh2si32" => "__builtin_ia32_vcvtsh2si32",
+    "llvm.x86.avx512fp16.vcvtsh2si64" => "__builtin_ia32_vcvtsh2si64",
+    "llvm.x86.avx512fp16.vcvtsh2usi32" => "__builtin_ia32_vcvtsh2usi32",
+    "llvm.x86.avx512fp16.vcvtsh2usi64" => "__builtin_ia32_vcvtsh2usi64",
+    "llvm.x86.avx512fp16.vcvtsi2sh" => "__builtin_ia32_vcvtsi2sh",
+    "llvm.x86.avx512fp16.vcvtsi642sh" => "__builtin_ia32_vcvtsi642sh",
+    "llvm.x86.avx512fp16.vcvttsh2si32" => "__builtin_ia32_vcvttsh2si32",
+    "llvm.x86.avx512fp16.vcvttsh2si64" => "__builtin_ia32_vcvttsh2si64",
+    "llvm.x86.avx512fp16.vcvttsh2usi32" => "__builtin_ia32_vcvttsh2usi32",
+    "llvm.x86.avx512fp16.vcvttsh2usi64" => "__builtin_ia32_vcvttsh2usi64",
+    "llvm.x86.avx512fp16.vcvtusi2sh" => "__builtin_ia32_vcvtusi2sh",
+    "llvm.x86.avx512fp16.vcvtusi642sh" => "__builtin_ia32_vcvtusi642sh",
+    "llvm.x86.avx512fp16.vfmaddsub.ph.128" => "__builtin_ia32_vfmaddsubph",
+    "llvm.x86.avx512fp16.vfmaddsub.ph.256" => "__builtin_ia32_vfmaddsubph256",
+    "llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32",
+    "llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64",
+    "llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si",
+    "llvm.x86.bmi.bzhi.64" => "__builtin_ia32_bzhi_di",
+    "llvm.x86.bmi.pdep.32" => "__builtin_ia32_pdep_si",
+    "llvm.x86.bmi.pdep.64" => "__builtin_ia32_pdep_di",
+    "llvm.x86.bmi.pext.32" => "__builtin_ia32_pext_si",
+    "llvm.x86.bmi.pext.64" => "__builtin_ia32_pext_di",
+    "llvm.x86.cldemote" => "__builtin_ia32_cldemote",
+    "llvm.x86.clflushopt" => "__builtin_ia32_clflushopt",
+    "llvm.x86.clrssbsy" => "__builtin_ia32_clrssbsy",
+    "llvm.x86.clui" => "__builtin_ia32_clui",
+    "llvm.x86.clwb" => "__builtin_ia32_clwb",
+    "llvm.x86.clzero" => "__builtin_ia32_clzero",
+    "llvm.x86.directstore32" => "__builtin_ia32_directstore_u32",
+    "llvm.x86.directstore64" => "__builtin_ia32_directstore_u64",
+    "llvm.x86.enqcmd" => "__builtin_ia32_enqcmd",
+    "llvm.x86.enqcmds" => "__builtin_ia32_enqcmds",
+    "llvm.x86.flags.read.u32" => "__builtin_ia32_readeflags_u32",
+    "llvm.x86.flags.read.u64" => "__builtin_ia32_readeflags_u64",
+    "llvm.x86.flags.write.u32" => "__builtin_ia32_writeeflags_u32",
+    "llvm.x86.flags.write.u64" => "__builtin_ia32_writeeflags_u64",
+    "llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask",
+    "llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask",
+    "llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask",
+    "llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask",
+    "llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask",
+    "llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask",
+    "llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask",
+    "llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask",
+    "llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask",
+    "llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask",
+    "llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask",
+    "llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask",
+    "llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd",
+    "llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256",
+    "llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps",
+    "llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256",
+    "llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd",
+    "llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss",
+    "llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd",
+    "llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256",
+    "llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps",
+    "llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256",
+    "llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd",
+    "llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256",
+    "llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps",
+    "llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256",
+    "llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd",
+    "llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss",
+    "llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd",
+    "llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256",
+    "llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps",
+    "llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256",
+    "llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd",
+    "llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256",
+    "llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps",
+    "llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256",
+    "llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd",
+    "llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss",
+    "llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd",
+    "llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256",
+    "llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps",
+    "llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256",
+    "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd",
+    "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss",
+    "llvm.x86.fxrstor" => "__builtin_ia32_fxrstor",
+    "llvm.x86.fxrstor64" => "__builtin_ia32_fxrstor64",
+    "llvm.x86.fxsave" => "__builtin_ia32_fxsave",
+    "llvm.x86.fxsave64" => "__builtin_ia32_fxsave64",
+    "llvm.x86.incsspd" => "__builtin_ia32_incsspd",
+    "llvm.x86.incsspq" => "__builtin_ia32_incsspq",
+    "llvm.x86.invpcid" => "__builtin_ia32_invpcid",
+    "llvm.x86.ldtilecfg" => "__builtin_ia32_tile_loadconfig",
+    "llvm.x86.ldtilecfg.internal" => "__builtin_ia32_tile_loadconfig_internal",
+    "llvm.x86.llwpcb" => "__builtin_ia32_llwpcb",
+    "llvm.x86.loadiwkey" => "__builtin_ia32_loadiwkey",
+    "llvm.x86.lwpins32" => "__builtin_ia32_lwpins32",
+    "llvm.x86.lwpins64" => "__builtin_ia32_lwpins64",
+    "llvm.x86.lwpval32" => "__builtin_ia32_lwpval32",
+    "llvm.x86.lwpval64" => "__builtin_ia32_lwpval64",
+    "llvm.x86.mmx.emms" => "__builtin_ia32_emms",
+    "llvm.x86.mmx.femms" => "__builtin_ia32_femms",
+    "llvm.x86.mmx.maskmovq" => "__builtin_ia32_maskmovq",
+    "llvm.x86.mmx.movnt.dq" => "__builtin_ia32_movntq",
+    "llvm.x86.mmx.packssdw" => "__builtin_ia32_packssdw",
+    "llvm.x86.mmx.packsswb" => "__builtin_ia32_packsswb",
+    "llvm.x86.mmx.packuswb" => "__builtin_ia32_packuswb",
+    "llvm.x86.mmx.padd.b" => "__builtin_ia32_paddb",
+    "llvm.x86.mmx.padd.d" => "__builtin_ia32_paddd",
+    "llvm.x86.mmx.padd.q" => "__builtin_ia32_paddq",
+    "llvm.x86.mmx.padd.w" => "__builtin_ia32_paddw",
+    "llvm.x86.mmx.padds.b" => "__builtin_ia32_paddsb",
+    "llvm.x86.mmx.padds.w" => "__builtin_ia32_paddsw",
+    "llvm.x86.mmx.paddus.b" => "__builtin_ia32_paddusb",
+    "llvm.x86.mmx.paddus.w" => "__builtin_ia32_paddusw",
+    "llvm.x86.mmx.palignr.b" => "__builtin_ia32_palignr",
+    "llvm.x86.mmx.pand" => "__builtin_ia32_pand",
+    "llvm.x86.mmx.pandn" => "__builtin_ia32_pandn",
+    "llvm.x86.mmx.pavg.b" => "__builtin_ia32_pavgb",
+    "llvm.x86.mmx.pavg.w" => "__builtin_ia32_pavgw",
+    "llvm.x86.mmx.pcmpeq.b" => "__builtin_ia32_pcmpeqb",
+    "llvm.x86.mmx.pcmpeq.d" => "__builtin_ia32_pcmpeqd",
+    "llvm.x86.mmx.pcmpeq.w" => "__builtin_ia32_pcmpeqw",
+    "llvm.x86.mmx.pcmpgt.b" => "__builtin_ia32_pcmpgtb",
+    "llvm.x86.mmx.pcmpgt.d" => "__builtin_ia32_pcmpgtd",
+    "llvm.x86.mmx.pcmpgt.w" => "__builtin_ia32_pcmpgtw",
+    "llvm.x86.mmx.pextr.w" => "__builtin_ia32_vec_ext_v4hi",
+    "llvm.x86.mmx.pinsr.w" => "__builtin_ia32_vec_set_v4hi",
+    "llvm.x86.mmx.pmadd.wd" => "__builtin_ia32_pmaddwd",
+    "llvm.x86.mmx.pmaxs.w" => "__builtin_ia32_pmaxsw",
+    "llvm.x86.mmx.pmaxu.b" => "__builtin_ia32_pmaxub",
+    "llvm.x86.mmx.pmins.w" => "__builtin_ia32_pminsw",
+    "llvm.x86.mmx.pminu.b" => "__builtin_ia32_pminub",
+    "llvm.x86.mmx.pmovmskb" => "__builtin_ia32_pmovmskb",
+    "llvm.x86.mmx.pmulh.w" => "__builtin_ia32_pmulhw",
+    "llvm.x86.mmx.pmulhu.w" => "__builtin_ia32_pmulhuw",
+    "llvm.x86.mmx.pmull.w" => "__builtin_ia32_pmullw",
+    "llvm.x86.mmx.pmulu.dq" => "__builtin_ia32_pmuludq",
+    "llvm.x86.mmx.por" => "__builtin_ia32_por",
+    "llvm.x86.mmx.psad.bw" => "__builtin_ia32_psadbw",
+    "llvm.x86.mmx.psll.d" => "__builtin_ia32_pslld",
+    "llvm.x86.mmx.psll.q" => "__builtin_ia32_psllq",
+    "llvm.x86.mmx.psll.w" => "__builtin_ia32_psllw",
+    "llvm.x86.mmx.pslli.d" => "__builtin_ia32_pslldi",
+    "llvm.x86.mmx.pslli.q" => "__builtin_ia32_psllqi",
+    "llvm.x86.mmx.pslli.w" => "__builtin_ia32_psllwi",
+    "llvm.x86.mmx.psra.d" => "__builtin_ia32_psrad",
+    "llvm.x86.mmx.psra.w" => "__builtin_ia32_psraw",
+    "llvm.x86.mmx.psrai.d" => "__builtin_ia32_psradi",
+    "llvm.x86.mmx.psrai.w" => "__builtin_ia32_psrawi",
+    "llvm.x86.mmx.psrl.d" => "__builtin_ia32_psrld",
+    "llvm.x86.mmx.psrl.q" => "__builtin_ia32_psrlq",
+    "llvm.x86.mmx.psrl.w" => "__builtin_ia32_psrlw",
+    "llvm.x86.mmx.psrli.d" => "__builtin_ia32_psrldi",
+    "llvm.x86.mmx.psrli.q" => "__builtin_ia32_psrlqi",
+    "llvm.x86.mmx.psrli.w" => "__builtin_ia32_psrlwi",
+    "llvm.x86.mmx.psub.b" => "__builtin_ia32_psubb",
+    "llvm.x86.mmx.psub.d" => "__builtin_ia32_psubd",
+    "llvm.x86.mmx.psub.q" => "__builtin_ia32_psubq",
+    "llvm.x86.mmx.psub.w" => "__builtin_ia32_psubw",
+    "llvm.x86.mmx.psubs.b" => "__builtin_ia32_psubsb",
+    "llvm.x86.mmx.psubs.w" => "__builtin_ia32_psubsw",
+    "llvm.x86.mmx.psubus.b" => "__builtin_ia32_psubusb",
+    "llvm.x86.mmx.psubus.w" => "__builtin_ia32_psubusw",
+    "llvm.x86.mmx.punpckhbw" => "__builtin_ia32_punpckhbw",
+    "llvm.x86.mmx.punpckhdq" => "__builtin_ia32_punpckhdq",
+    "llvm.x86.mmx.punpckhwd" => "__builtin_ia32_punpckhwd",
+    "llvm.x86.mmx.punpcklbw" => "__builtin_ia32_punpcklbw",
+    "llvm.x86.mmx.punpckldq" => "__builtin_ia32_punpckldq",
+    "llvm.x86.mmx.punpcklwd" => "__builtin_ia32_punpcklwd",
+    "llvm.x86.mmx.pxor" => "__builtin_ia32_pxor",
+    "llvm.x86.monitorx" => "__builtin_ia32_monitorx",
+    "llvm.x86.movdir64b" => "__builtin_ia32_movdir64b",
+    "llvm.x86.mwaitx" => "__builtin_ia32_mwaitx",
+    "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128",
+    "llvm.x86.pclmulqdq.256" => "__builtin_ia32_pclmulqdq256",
+    "llvm.x86.pclmulqdq.512" => "__builtin_ia32_pclmulqdq512",
+    "llvm.x86.ptwrite32" => "__builtin_ia32_ptwrite32",
+    "llvm.x86.ptwrite64" => "__builtin_ia32_ptwrite64",
+    "llvm.x86.rdfsbase.32" => "__builtin_ia32_rdfsbase32",
+    "llvm.x86.rdfsbase.64" => "__builtin_ia32_rdfsbase64",
+    "llvm.x86.rdgsbase.32" => "__builtin_ia32_rdgsbase32",
+    "llvm.x86.rdgsbase.64" => "__builtin_ia32_rdgsbase64",
+    "llvm.x86.rdpid" => "__builtin_ia32_rdpid",
+    "llvm.x86.rdpkru" => "__builtin_ia32_rdpkru",
+    "llvm.x86.rdpmc" => "__builtin_ia32_rdpmc",
+    "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd",
+    "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq",
+    "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc",
+    "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp",
+    "llvm.x86.rstorssp" => "__builtin_ia32_rstorssp",
+    "llvm.x86.saveprevssp" => "__builtin_ia32_saveprevssp",
+    "llvm.x86.senduipi" => "__builtin_ia32_senduipi",
+    "llvm.x86.serialize" => "__builtin_ia32_serialize",
+    "llvm.x86.setssbsy" => "__builtin_ia32_setssbsy",
+    "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1",
+    "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2",
+    "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte",
+    "llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4",
+    "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1",
+    "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2",
+    "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2",
+    "llvm.x86.slwpcb" => "__builtin_ia32_slwpcb",
+    "llvm.x86.sse.add.ss" => "__builtin_ia32_addss",
+    "llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps",
+    "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss",
+    "llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq",
+    "llvm.x86.sse.comige.ss" => "__builtin_ia32_comige",
+    "llvm.x86.sse.comigt.ss" => "__builtin_ia32_comigt",
+    "llvm.x86.sse.comile.ss" => "__builtin_ia32_comile",
+    "llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt",
+    "llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq",
+    "llvm.x86.sse.cvtpd2pi" => "__builtin_ia32_cvtpd2pi",
+    "llvm.x86.sse.cvtpi2pd" => "__builtin_ia32_cvtpi2pd",
+    "llvm.x86.sse.cvtpi2ps" => "__builtin_ia32_cvtpi2ps",
+    "llvm.x86.sse.cvtps2pi" => "__builtin_ia32_cvtps2pi",
+    "llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss",
+    "llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss",
+    "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si",
+    "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64",
+    "llvm.x86.sse.cvttpd2pi" => "__builtin_ia32_cvttpd2pi",
+    "llvm.x86.sse.cvttps2pi" => "__builtin_ia32_cvttps2pi",
+    "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si",
+    "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64",
+    "llvm.x86.sse.div.ss" => "__builtin_ia32_divss",
+    "llvm.x86.sse.max.ps" => "__builtin_ia32_maxps",
+    "llvm.x86.sse.max.ss" => "__builtin_ia32_maxss",
+    "llvm.x86.sse.min.ps" => "__builtin_ia32_minps",
+    "llvm.x86.sse.min.ss" => "__builtin_ia32_minss",
+    "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps",
+    "llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss",
+    "llvm.x86.sse.pshuf.w" => "__builtin_ia32_pshufw",
+    "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps",
+    "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss",
+    "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps",
+    "llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss",
+    "llvm.x86.sse.sfence" => "__builtin_ia32_sfence",
+    "llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps",
+    "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss",
+    "llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups",
+    "llvm.x86.sse.sub.ss" => "__builtin_ia32_subss",
+    "llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq",
+    "llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige",
+    "llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt",
+    "llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile",
+    "llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt",
+    "llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq",
+    "llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd",
+    "llvm.x86.sse2.clflush" => "__builtin_ia32_clflush",
+    "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd",
+    "llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd",
+    "llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq",
+    "llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge",
+    "llvm.x86.sse2.comigt.sd" => "__builtin_ia32_comisdgt",
+    "llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle",
+    "llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt",
+    "llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq",
+    "llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd",
+    "llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps",
+    "llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq",
+    "llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps",
+    "llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq",
+    "llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd",
+    "llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si",
+    "llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64",
+    "llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss",
+    "llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd",
+    "llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd",
+    "llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd",
+    "llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq",
+    "llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq",
+    "llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si",
+    "llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64",
+    "llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd",
+    "llvm.x86.sse2.lfence" => "__builtin_ia32_lfence",
+    "llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu",
+    "llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd",
+    "llvm.x86.sse2.max.sd" => "__builtin_ia32_maxsd",
+    "llvm.x86.sse2.mfence" => "__builtin_ia32_mfence",
+    "llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd",
+    "llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd",
+    "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd",
+    "llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd",
+    "llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128",
+    "llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128",
+    "llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128",
+    "llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128",
+    "llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128",
+    "llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128",
+    "llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128",
+    "llvm.x86.sse2.pause" => "__builtin_ia32_pause",
+    "llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128",
+    "llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128",
+    "llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128",
+    "llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128",
+    "llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128",
+    "llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128",
+    "llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128",
+    "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128",
+    "llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128",
+    "llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128",
+    "llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128",
+    "llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128",
+    "llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd",
+    "llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw",
+    "llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw",
+    "llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128",
+    "llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128",
+    "llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift",
+    "llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128",
+    "llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128",
+    "llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128",
+    "llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128",
+    "llvm.x86.sse2.pslli.w" => "__builtin_ia32_psllwi128",
+    "llvm.x86.sse2.psra.d" => "__builtin_ia32_psrad128",
+    "llvm.x86.sse2.psra.w" => "__builtin_ia32_psraw128",
+    "llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128",
+    "llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128",
+    "llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128",
+    "llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128",
+    "llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift",
+    "llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128",
+    "llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128",
+    "llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128",
+    "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128",
+    "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128",
+    "llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128",
+    "llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128",
+    "llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128",
+    "llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128",
+    "llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd",
+    "llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd",
+    "llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si",
+    "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu",
+    "llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd",
+    "llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd",
+    "llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq",
+    "llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge",
+    "llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt",
+    "llvm.x86.sse2.ucomile.sd" => "__builtin_ia32_ucomisdle",
+    "llvm.x86.sse2.ucomilt.sd" => "__builtin_ia32_ucomisdlt",
+    "llvm.x86.sse2.ucomineq.sd" => "__builtin_ia32_ucomisdneq",
+    "llvm.x86.sse3.addsub.pd" => "__builtin_ia32_addsubpd",
+    "llvm.x86.sse3.addsub.ps" => "__builtin_ia32_addsubps",
+    "llvm.x86.sse3.hadd.pd" => "__builtin_ia32_haddpd",
+    "llvm.x86.sse3.hadd.ps" => "__builtin_ia32_haddps",
+    "llvm.x86.sse3.hsub.pd" => "__builtin_ia32_hsubpd",
+    "llvm.x86.sse3.hsub.ps" => "__builtin_ia32_hsubps",
+    "llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu",
+    "llvm.x86.sse3.monitor" => "__builtin_ia32_monitor",
+    "llvm.x86.sse3.mwait" => "__builtin_ia32_mwait",
+    "llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd",
+    "llvm.x86.sse41.blendps" => "__builtin_ia32_blendps",
+    "llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd",
+    "llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps",
+    "llvm.x86.sse41.dppd" => "__builtin_ia32_dppd",
+    "llvm.x86.sse41.dpps" => "__builtin_ia32_dpps",
+    "llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128",
+    "llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128",
+    "llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa",
+    "llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128",
+    "llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128",
+    "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128",
+    "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128",
+    "llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128",
+    "llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128",
+    "llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128",
+    "llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128",
+    "llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128",
+    "llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128",
+    "llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128",
+    "llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128",
+    "llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128",
+    "llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128",
+    "llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128",
+    "llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128",
+    "llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128",
+    "llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128",
+    "llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128",
+    "llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128",
+    "llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128",
+    "llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128",
+    "llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128",
+    "llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128",
+    "llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128",
+    "llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128",
+    "llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128",
+    "llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128",
+    "llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128",
+    "llvm.x86.sse41.round.pd" => "__builtin_ia32_roundpd",
+    "llvm.x86.sse41.round.ps" => "__builtin_ia32_roundps",
+    "llvm.x86.sse41.round.sd" => "__builtin_ia32_roundsd",
+    "llvm.x86.sse41.round.ss" => "__builtin_ia32_roundss",
+    "llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi",
+    "llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si",
+    "llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi",
+    "llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di",
+    "llvm.x86.sse42.pcmpestri128" => "__builtin_ia32_pcmpestri128",
+    "llvm.x86.sse42.pcmpestria128" => "__builtin_ia32_pcmpestria128",
+    "llvm.x86.sse42.pcmpestric128" => "__builtin_ia32_pcmpestric128",
+    "llvm.x86.sse42.pcmpestrio128" => "__builtin_ia32_pcmpestrio128",
+    "llvm.x86.sse42.pcmpestris128" => "__builtin_ia32_pcmpestris128",
+    "llvm.x86.sse42.pcmpestriz128" => "__builtin_ia32_pcmpestriz128",
+    "llvm.x86.sse42.pcmpestrm128" => "__builtin_ia32_pcmpestrm128",
+    "llvm.x86.sse42.pcmpistri128" => "__builtin_ia32_pcmpistri128",
+    "llvm.x86.sse42.pcmpistria128" => "__builtin_ia32_pcmpistria128",
+    "llvm.x86.sse42.pcmpistric128" => "__builtin_ia32_pcmpistric128",
+    "llvm.x86.sse42.pcmpistrio128" => "__builtin_ia32_pcmpistrio128",
+    "llvm.x86.sse42.pcmpistris128" => "__builtin_ia32_pcmpistris128",
+    "llvm.x86.sse42.pcmpistriz128" => "__builtin_ia32_pcmpistriz128",
+    "llvm.x86.sse42.pcmpistrm128" => "__builtin_ia32_pcmpistrm128",
+    "llvm.x86.sse4a.extrq" => "__builtin_ia32_extrq",
+    "llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi",
+    "llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq",
+    "llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi",
+    "llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd",
+    "llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss",
+    "llvm.x86.ssse3.pabs.b" => "__builtin_ia32_pabsb",
+    "llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128",
+    "llvm.x86.ssse3.pabs.d" => "__builtin_ia32_pabsd",
+    "llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128",
+    "llvm.x86.ssse3.pabs.w" => "__builtin_ia32_pabsw",
+    "llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128",
+    "llvm.x86.ssse3.phadd.d" => "__builtin_ia32_phaddd",
+    "llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128",
+    "llvm.x86.ssse3.phadd.sw" => "__builtin_ia32_phaddsw",
+    "llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128",
+    "llvm.x86.ssse3.phadd.w" => "__builtin_ia32_phaddw",
+    "llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128",
+    "llvm.x86.ssse3.phsub.d" => "__builtin_ia32_phsubd",
+    "llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128",
+    "llvm.x86.ssse3.phsub.sw" => "__builtin_ia32_phsubsw",
+    "llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128",
+    "llvm.x86.ssse3.phsub.w" => "__builtin_ia32_phsubw",
+    "llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128",
+    "llvm.x86.ssse3.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw",
+    "llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128",
+    "llvm.x86.ssse3.pmul.hr.sw" => "__builtin_ia32_pmulhrsw",
+    "llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128",
+    "llvm.x86.ssse3.pshuf.b" => "__builtin_ia32_pshufb",
+    "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128",
+    "llvm.x86.ssse3.psign.b" => "__builtin_ia32_psignb",
+    "llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128",
+    "llvm.x86.ssse3.psign.d" => "__builtin_ia32_psignd",
+    "llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128",
+    "llvm.x86.ssse3.psign.w" => "__builtin_ia32_psignw",
+    "llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128",
+    "llvm.x86.sttilecfg" => "__builtin_ia32_tile_storeconfig",
+    "llvm.x86.stui" => "__builtin_ia32_stui",
+    "llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32",
+    "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64",
+    "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32",
+    "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64",
+    "llvm.x86.tdpbf16ps" => "__builtin_ia32_tdpbf16ps",
+    "llvm.x86.tdpbf16ps.internal" => "__builtin_ia32_tdpbf16ps_internal",
+    "llvm.x86.tdpbssd" => "__builtin_ia32_tdpbssd",
+    "llvm.x86.tdpbssd.internal" => "__builtin_ia32_tdpbssd_internal",
+    "llvm.x86.tdpbsud" => "__builtin_ia32_tdpbsud",
+    "llvm.x86.tdpbsud.internal" => "__builtin_ia32_tdpbsud_internal",
+    "llvm.x86.tdpbusd" => "__builtin_ia32_tdpbusd",
+    "llvm.x86.tdpbusd.internal" => "__builtin_ia32_tdpbusd_internal",
+    "llvm.x86.tdpbuud" => "__builtin_ia32_tdpbuud",
+    "llvm.x86.tdpbuud.internal" => "__builtin_ia32_tdpbuud_internal",
+    "llvm.x86.testui" => "__builtin_ia32_testui",
+    "llvm.x86.tileloadd64" => "__builtin_ia32_tileloadd64",
+    "llvm.x86.tileloadd64.internal" => "__builtin_ia32_tileloadd64_internal",
+    "llvm.x86.tileloaddt164" => "__builtin_ia32_tileloaddt164",
+    "llvm.x86.tileloaddt164.internal" => "__builtin_ia32_tileloaddt164_internal",
+    "llvm.x86.tilerelease" => "__builtin_ia32_tilerelease",
+    "llvm.x86.tilestored64" => "__builtin_ia32_tilestored64",
+    "llvm.x86.tilestored64.internal" => "__builtin_ia32_tilestored64_internal",
+    "llvm.x86.tilezero" => "__builtin_ia32_tilezero",
+    "llvm.x86.tilezero.internal" => "__builtin_ia32_tilezero_internal",
+    "llvm.x86.tpause" => "__builtin_ia32_tpause",
+    "llvm.x86.umonitor" => "__builtin_ia32_umonitor",
+    "llvm.x86.umwait" => "__builtin_ia32_umwait",
+    "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps",
+    "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256",
+    "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph",
+    "llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256",
+    "llvm.x86.vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi",
+    "llvm.x86.vgf2p8affineinvqb.256" => "__builtin_ia32_vgf2p8affineinvqb_v32qi",
+    "llvm.x86.vgf2p8affineinvqb.512" => "__builtin_ia32_vgf2p8affineinvqb_v64qi",
+    "llvm.x86.vgf2p8affineqb.128" => "__builtin_ia32_vgf2p8affineqb_v16qi",
+    "llvm.x86.vgf2p8affineqb.256" => "__builtin_ia32_vgf2p8affineqb_v32qi",
+    "llvm.x86.vgf2p8affineqb.512" => "__builtin_ia32_vgf2p8affineqb_v64qi",
+    "llvm.x86.vgf2p8mulb.128" => "__builtin_ia32_vgf2p8mulb_v16qi",
+    "llvm.x86.vgf2p8mulb.256" => "__builtin_ia32_vgf2p8mulb_v32qi",
+    "llvm.x86.vgf2p8mulb.512" => "__builtin_ia32_vgf2p8mulb_v64qi",
+    "llvm.x86.wbinvd" => "__builtin_ia32_wbinvd",
+    "llvm.x86.wbnoinvd" => "__builtin_ia32_wbnoinvd",
+    "llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32",
+    "llvm.x86.wrfsbase.64" => "__builtin_ia32_wrfsbase64",
+    "llvm.x86.wrgsbase.32" => "__builtin_ia32_wrgsbase32",
+    "llvm.x86.wrgsbase.64" => "__builtin_ia32_wrgsbase64",
+    "llvm.x86.wrpkru" => "__builtin_ia32_wrpkru",
+    "llvm.x86.wrssd" => "__builtin_ia32_wrssd",
+    "llvm.x86.wrssq" => "__builtin_ia32_wrssq",
+    "llvm.x86.wrussd" => "__builtin_ia32_wrussd",
+    "llvm.x86.wrussq" => "__builtin_ia32_wrussq",
+    "llvm.x86.xabort" => "__builtin_ia32_xabort",
+    "llvm.x86.xbegin" => "__builtin_ia32_xbegin",
+    "llvm.x86.xend" => "__builtin_ia32_xend",
+    "llvm.x86.xop.vfrcz.pd" => "__builtin_ia32_vfrczpd",
+    "llvm.x86.xop.vfrcz.pd.256" => "__builtin_ia32_vfrczpd256",
+    "llvm.x86.xop.vfrcz.ps" => "__builtin_ia32_vfrczps",
+    "llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256",
+    "llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd",
+    "llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss",
+    "llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov",
+    "llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256",
+    "llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb",
+    "llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd",
+    "llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq",
+    "llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub",
+    "llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud",
+    "llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq",
+    "llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw",
+    "llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw",
+    "llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd",
+    "llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256",
+    "llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps",
+    "llvm.x86.xop.vpermil2ps.256" => "__builtin_ia32_vpermil2ps256",
+    "llvm.x86.xop.vphaddbd" => "__builtin_ia32_vphaddbd",
+    "llvm.x86.xop.vphaddbq" => "__builtin_ia32_vphaddbq",
+    "llvm.x86.xop.vphaddbw" => "__builtin_ia32_vphaddbw",
+    "llvm.x86.xop.vphadddq" => "__builtin_ia32_vphadddq",
+    "llvm.x86.xop.vphaddubd" => "__builtin_ia32_vphaddubd",
+    "llvm.x86.xop.vphaddubq" => "__builtin_ia32_vphaddubq",
+    "llvm.x86.xop.vphaddubw" => "__builtin_ia32_vphaddubw",
+    "llvm.x86.xop.vphaddudq" => "__builtin_ia32_vphaddudq",
+    "llvm.x86.xop.vphadduwd" => "__builtin_ia32_vphadduwd",
+    "llvm.x86.xop.vphadduwq" => "__builtin_ia32_vphadduwq",
+    "llvm.x86.xop.vphaddwd" => "__builtin_ia32_vphaddwd",
+    "llvm.x86.xop.vphaddwq" => "__builtin_ia32_vphaddwq",
+    "llvm.x86.xop.vphsubbw" => "__builtin_ia32_vphsubbw",
+    "llvm.x86.xop.vphsubdq" => "__builtin_ia32_vphsubdq",
+    "llvm.x86.xop.vphsubwd" => "__builtin_ia32_vphsubwd",
+    "llvm.x86.xop.vpmacsdd" => "__builtin_ia32_vpmacsdd",
+    "llvm.x86.xop.vpmacsdqh" => "__builtin_ia32_vpmacsdqh",
+    "llvm.x86.xop.vpmacsdql" => "__builtin_ia32_vpmacsdql",
+    "llvm.x86.xop.vpmacssdd" => "__builtin_ia32_vpmacssdd",
+    "llvm.x86.xop.vpmacssdqh" => "__builtin_ia32_vpmacssdqh",
+    "llvm.x86.xop.vpmacssdql" => "__builtin_ia32_vpmacssdql",
+    "llvm.x86.xop.vpmacsswd" => "__builtin_ia32_vpmacsswd",
+    "llvm.x86.xop.vpmacssww" => "__builtin_ia32_vpmacssww",
+    "llvm.x86.xop.vpmacswd" => "__builtin_ia32_vpmacswd",
+    "llvm.x86.xop.vpmacsww" => "__builtin_ia32_vpmacsww",
+    "llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd",
+    "llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd",
+    "llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm",
+    "llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb",
+    "llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi",
+    "llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd",
+    "llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi",
+    "llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq",
+    "llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi",
+    "llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw",
+    "llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi",
+    "llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab",
+    "llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad",
+    "llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq",
+    "llvm.x86.xop.vpshaw" => "__builtin_ia32_vpshaw",
+    "llvm.x86.xop.vpshlb" => "__builtin_ia32_vpshlb",
+    "llvm.x86.xop.vpshld" => "__builtin_ia32_vpshld",
+    "llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq",
+    "llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw",
+    "llvm.x86.xresldtrk" => "__builtin_ia32_xresldtrk",
+    "llvm.x86.xsusldtrk" => "__builtin_ia32_xsusldtrk",
+    "llvm.x86.xtest" => "__builtin_ia32_xtest",
+    // xcore
+    "llvm.xcore.bitrev" => "__builtin_bitrev",
+    "llvm.xcore.getid" => "__builtin_getid",
+    "llvm.xcore.getps" => "__builtin_getps",
+    "llvm.xcore.setps" => "__builtin_setps",
+    _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),
+}

diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs b/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs
index b074febc521ebe03263fadb044fed62c48759900..1b089f08f764a066127b5669de791d39a466e047 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs
+++ b/compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs
@@ -1,22 +1,250 @@
-use gccjit::Function;
+use std::borrow::Cow;
 
-use crate::context::CodegenCx;
+use gccjit::{Function, FunctionPtrType, RValue, ToRValue};
 
-pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> {
-    let _gcc_name =
-        match name {
-            "llvm.x86.xgetbv" => {
-                let gcc_name = "__builtin_trap";
-                let func = cx.context.get_builtin_function(gcc_name);
-                cx.functions.borrow_mut().insert(gcc_name.to_string(), func);
-                return func;
+use crate::{context::CodegenCx, builder::Builder};
+
+pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc, 'tcx>, gcc_func: FunctionPtrType<'gcc>, mut args: Cow<'b, [RValue<'gcc>]>, func_name: &str) -> Cow<'b, [RValue<'gcc>]> {
+    // Some LLVM intrinsics do not map 1-to-1 to GCC intrinsics, so we add the missing
+    // arguments here.
+    if gcc_func.get_param_count() != args.len() {
+        match &*func_name {
+            "__builtin_ia32_pmuldq512_mask" | "__builtin_ia32_pmuludq512_mask"
+                // FIXME(antoyo): the following intrinsics has 4 (or 5) arguments according to the doc, but is defined with 2 (or 3) arguments in library/stdarch/crates/core_arch/src/x86/avx512f.rs.
+                | "__builtin_ia32_pmaxsd512_mask" | "__builtin_ia32_pmaxsq512_mask" | "__builtin_ia32_pmaxsq256_mask"
+                | "__builtin_ia32_pmaxsq128_mask" | "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
+                | "__builtin_ia32_pmaxud512_mask" | "__builtin_ia32_pmaxuq512_mask" | "__builtin_ia32_pmaxuq256_mask"
+                | "__builtin_ia32_pmaxuq128_mask"
+                | "__builtin_ia32_pminsd512_mask" | "__builtin_ia32_pminsq512_mask" | "__builtin_ia32_pminsq256_mask"
+                | "__builtin_ia32_pminsq128_mask" | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask"
+                | "__builtin_ia32_pminud512_mask" | "__builtin_ia32_pminuq512_mask" | "__builtin_ia32_pminuq256_mask"
+                | "__builtin_ia32_pminuq128_mask" | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask"
+                => {
+                    // TODO: refactor by separating those intrinsics outside of this branch.
+                    let add_before_last_arg =
+                        match &*func_name {
+                            "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
+                                | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask"
+                                | "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => true,
+                            _ => false,
+                        };
+                    let new_first_arg_is_zero =
+                        match &*func_name {
+                            "__builtin_ia32_pmaxuq256_mask" | "__builtin_ia32_pmaxuq128_mask"
+                                | "__builtin_ia32_pminuq256_mask" | "__builtin_ia32_pminuq128_mask" => true,
+                            _ => false
+                        };
+                    let arg3_index =
+                        match &*func_name {
+                            "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 1,
+                            _ => 2,
+                        };
+                    let mut new_args = args.to_vec();
+                    let arg3_type = gcc_func.get_param_type(arg3_index);
+                    let first_arg =
+                        if new_first_arg_is_zero {
+                            let vector_type = arg3_type.dyncast_vector().expect("vector type");
+                            let zero = builder.context.new_rvalue_zero(vector_type.get_element_type());
+                            let num_units = vector_type.get_num_units();
+                            builder.context.new_rvalue_from_vector(None, arg3_type, &vec![zero; num_units])
+                        }
+                        else {
+                            builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue()
+                        };
+                    if add_before_last_arg {
+                        new_args.insert(new_args.len() - 1, first_arg);
+                    }
+                    else {
+                        new_args.push(first_arg);
+                    }
+                    let arg4_index =
+                        match &*func_name {
+                            "__builtin_ia32_sqrtps512_mask" | "__builtin_ia32_sqrtpd512_mask" => 2,
+                            _ => 3,
+                        };
+                    let arg4_type = gcc_func.get_param_type(arg4_index);
+                    let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
+                    if add_before_last_arg {
+                        new_args.insert(new_args.len() - 1, minus_one);
+                    }
+                    else {
+                        new_args.push(minus_one);
+                    }
+                    args = new_args.into();
+                },
+                "__builtin_ia32_pternlogd512_mask" | "__builtin_ia32_pternlogd256_mask"
+                    | "__builtin_ia32_pternlogd128_mask" | "__builtin_ia32_pternlogq512_mask"
+                    | "__builtin_ia32_pternlogq256_mask" | "__builtin_ia32_pternlogq128_mask" => {
+                        let mut new_args = args.to_vec();
+                        let arg5_type = gcc_func.get_param_type(4);
+                        let minus_one = builder.context.new_rvalue_from_int(arg5_type, -1);
+                        new_args.push(minus_one);
+                        args = new_args.into();
+                    },
+                    "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => {
+                        let mut new_args = args.to_vec();
+
+                        let mut last_arg = None;
+                        if args.len() == 4 {
+                            last_arg = new_args.pop();
+                        }
+
+                        let arg4_type = gcc_func.get_param_type(3);
+                        let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
+                        new_args.push(minus_one);
+
+                        if args.len() == 3 {
+                            // Both llvm.fma.v16f32 and llvm.x86.avx512.vfmadd.ps.512 maps to
+                            // the same GCC intrinsic, but the former has 3 parameters and the
+                            // latter has 4 so it doesn't require this additional argument.
+                            let arg5_type = gcc_func.get_param_type(4);
+                            new_args.push(builder.context.new_rvalue_from_int(arg5_type, 4));
+                        }
+
+                        if let Some(last_arg) = last_arg {
+                            new_args.push(last_arg);
+                        }
+
+                        args = new_args.into();
+                    },
+                    "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask"
+                        | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask"
+                        | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask"
+                        | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask" => {
+                        let mut new_args = args.to_vec();
+                        let last_arg = new_args.pop().expect("last arg");
+                        let arg3_type = gcc_func.get_param_type(2);
+                        let undefined = builder.current_func().new_local(None, arg3_type, "undefined_for_intrinsic").to_rvalue();
+                        new_args.push(undefined);
+                        let arg4_type = gcc_func.get_param_type(3);
+                        let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
+                        new_args.push(minus_one);
+                        new_args.push(last_arg);
+                        args = new_args.into();
+                    },
+                    "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => {
+                        let mut new_args = args.to_vec();
+                        let last_arg = new_args.pop().expect("last arg");
+                        let arg4_type = gcc_func.get_param_type(3);
+                        let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
+                        new_args.push(minus_one);
+                        new_args.push(last_arg);
+                        args = new_args.into();
+                    },
+                    _ => (),
+        }
+    }
+
+    args
+}
+
+pub fn ignore_arg_cast(func_name: &str, index: usize, args_len: usize) -> bool {
+    // NOTE: these intrinsics have missing parameters before the last one, so ignore the
+    // last argument type check.
+    // FIXME(antoyo): find a way to refactor in order to avoid this hack.
+    match func_name {
+        "__builtin_ia32_maxps512_mask" | "__builtin_ia32_maxpd512_mask"
+            | "__builtin_ia32_minps512_mask" | "__builtin_ia32_minpd512_mask" | "__builtin_ia32_sqrtps512_mask"
+            | "__builtin_ia32_sqrtpd512_mask" | "__builtin_ia32_addps512_mask" | "__builtin_ia32_addpd512_mask"
+            | "__builtin_ia32_subps512_mask" | "__builtin_ia32_subpd512_mask"
+            | "__builtin_ia32_mulps512_mask" | "__builtin_ia32_mulpd512_mask"
+            | "__builtin_ia32_divps512_mask" | "__builtin_ia32_divpd512_mask"
+            | "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => {
+                if index == args_len - 1 {
+                    return true;
+                }
             },
-            // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html
-            "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd",
-            "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd",
-            "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128",
-            _ => unimplemented!("unsupported LLVM intrinsic {}", name)
-        };
-
-    unimplemented!();
+        "__builtin_ia32_vfmaddps512_mask" | "__builtin_ia32_vfmaddpd512_mask" => {
+            // Since there are two LLVM intrinsics that map to each of these GCC builtins and only
+            // one of them has a missing parameter before the last one, we check the number of
+            // arguments to distinguish those cases.
+            if args_len == 4 && index == args_len - 1 {
+                return true;
+            }
+        },
+        _ => (),
+    }
+
+    false
+}
+
+#[cfg(not(feature="master"))]
+pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> {
+    match name {
+        "llvm.x86.xgetbv" => {
+            let gcc_name = "__builtin_trap";
+            let func = cx.context.get_builtin_function(gcc_name);
+            cx.functions.borrow_mut().insert(gcc_name.to_string(), func);
+            return func;
+        },
+        _ => unimplemented!("unsupported LLVM intrinsic {}", name),
+    }
+}
+
+#[cfg(feature="master")]
+pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> {
+    let gcc_name = match name {
+        "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv",
+        // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html
+        "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd",
+        "llvm.x86.avx512.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask",
+        "llvm.x86.avx512.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask",
+        "llvm.x86.avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask",
+        "llvm.x86.avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask",
+        "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512_mask",
+        "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512_mask",
+        "llvm.x86.avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask",
+        "llvm.x86.avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask",
+        "llvm.x86.avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask",
+        "llvm.x86.avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask",
+        "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512_mask",
+        "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512_mask",
+        "llvm.x86.avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask",
+        "llvm.x86.avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask",
+        "llvm.fma.v16f32" => "__builtin_ia32_vfmaddps512_mask",
+        "llvm.fma.v8f64" => "__builtin_ia32_vfmaddpd512_mask",
+        "llvm.x86.avx512.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask",
+        "llvm.x86.avx512.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask",
+        "llvm.x86.avx512.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask",
+        "llvm.x86.avx512.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask",
+        "llvm.x86.avx512.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask",
+        "llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask",
+        "llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask",
+        "llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask",
+        "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512_mask",
+        "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512_mask",
+        "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512_mask",
+        "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512_mask",
+        "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512_mask",
+        "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512_mask",
+        "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512_mask",
+        "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512_mask",
+        "llvm.x86.avx512.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask",
+        "llvm.x86.avx512.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask",
+
+        // The above doc points to unknown builtins for the following, so override them:
+        "llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si",
+        "llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gathersiv8si",
+        "llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gathersiv4sf",
+        "llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gathersiv8sf",
+        "llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gathersiv2di",
+        "llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gathersiv4di",
+        "llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gathersiv2df",
+        "llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gathersiv4df",
+        "llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherdiv4si",
+        "llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherdiv4si256",
+        "llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherdiv4sf",
+        "llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherdiv4sf256",
+        "llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherdiv2di",
+        "llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherdiv4di",
+        "llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherdiv2df",
+        "llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherdiv4df",
+        "" => "",
+        // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py
+        _ => include!("archs.rs"),
+    };
+
+    let func = cx.context.get_target_builtin_function(gcc_name);
+    cx.functions.borrow_mut().insert(gcc_name.to_string(), func);
+    func
 }

diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs b/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs
index 68a05d95ef7346bb69d208bf6ac03b712292fc19..c6681de68e2672b6d2f9f1f01cb15901d0dba305 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs
+++ b/compiler/rustc_codegen_gcc/src/intrinsic/mod.rs
@@ -967,34 +967,55 @@ fn rotate_right(&mut self, value: RValue<'gcc>, shift: RValue<'gcc>, width: u64)
     }
 
     fn saturating_add(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>, signed: bool, width: u64) -> RValue<'gcc> {
-        let func = self.current_func.borrow().expect("func");
-
+        let result_type = lhs.get_type();
         if signed {
-            // Algorithm from: https://stackoverflow.com/a/56531252/389119
-            let after_block = func.new_block("after");
-            let func_name =
-                match width {
-                    8 => "__builtin_add_overflow",
-                    16 => "__builtin_add_overflow",
-                    32 => "__builtin_sadd_overflow",
-                    64 => "__builtin_saddll_overflow",
-                    128 => "__builtin_add_overflow",
-                    _ => unreachable!(),
-                };
-            let overflow_func = self.context.get_builtin_function(func_name);
-            let result_type = lhs.get_type();
+            // Based on algorithm from: https://stackoverflow.com/a/56531252/389119
+            let func = self.current_func.borrow().expect("func");
             let res = func.new_local(None, result_type, "saturating_sum");
-            let overflow = self.overflow_call(overflow_func, &[lhs, rhs, res.get_address(None)], None);
+            let supports_native_type = self.is_native_int_type(result_type);
+            let overflow =
+                if supports_native_type {
+                    let func_name =
+                        match width {
+                            8 => "__builtin_add_overflow",
+                            16 => "__builtin_add_overflow",
+                            32 => "__builtin_sadd_overflow",
+                            64 => "__builtin_saddll_overflow",
+                            128 => "__builtin_add_overflow",
+                            _ => unreachable!(),
+                        };
+                    let overflow_func = self.context.get_builtin_function(func_name);
+                    self.overflow_call(overflow_func, &[lhs, rhs, res.get_address(None)], None)
+                }
+                else {
+                    let func_name =
+                        match width {
+                            128 => "__rust_i128_addo",
+                            _ => unreachable!(),
+                        };
+                    let param_a = self.context.new_parameter(None, result_type, "a");
+                    let param_b = self.context.new_parameter(None, result_type, "b");
+                    let result_field = self.context.new_field(None, result_type, "result");
+                    let overflow_field = self.context.new_field(None, self.bool_type, "overflow");
+                    let return_type = self.context.new_struct_type(None, "result_overflow", &[result_field, overflow_field]);
+                    let func = self.context.new_function(None, FunctionType::Extern, return_type.as_type(), &[param_a, param_b], func_name, false);
+                    let result = self.context.new_call(None, func, &[lhs, rhs]);
+                    let overflow = result.access_field(None, overflow_field);
+                    let int_result = result.access_field(None, result_field);
+                    self.llbb().add_assignment(None, res, int_result);
+                    overflow
+                };
 
             let then_block = func.new_block("then");
+            let after_block = func.new_block("after");
 
-            let unsigned_type = self.context.new_int_type(width as i32 / 8, false);
-            let shifted = self.context.new_cast(None, lhs, unsigned_type) >> self.context.new_rvalue_from_int(unsigned_type, width as i32 - 1);
-            let uint_max = self.context.new_unary_op(None, UnaryOp::BitwiseNegate, unsigned_type,
-                self.context.new_rvalue_from_int(unsigned_type, 0)
-            );
-            let int_max = uint_max >> self.context.new_rvalue_one(unsigned_type);
-            then_block.add_assignment(None, res, self.context.new_cast(None, shifted + int_max, result_type));
+            // Return `result_type`'s maximum or minimum value on overflow
+            // NOTE: convert the type to unsigned to have an unsigned shift.
+            let unsigned_type = result_type.to_unsigned(&self.cx);
+            let shifted = self.gcc_lshr(self.gcc_int_cast(lhs, unsigned_type), self.gcc_int(unsigned_type, width as i64 - 1));
+            let uint_max = self.gcc_not(self.gcc_int(unsigned_type, 0));
+            let int_max = self.gcc_lshr(uint_max, self.gcc_int(unsigned_type, 1));
+            then_block.add_assignment(None, res, self.gcc_int_cast(self.gcc_add(shifted, int_max), result_type));
             then_block.end_with_jump(None, after_block);
 
             self.llbb().end_with_conditional(None, overflow, then_block, after_block);
@@ -1007,19 +1028,18 @@ fn saturating_add(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>, signed: bool,
         }
         else {
             // Algorithm from: http://locklessinc.com/articles/sat_arithmetic/
-            let res = lhs + rhs;
-            let res_type = res.get_type();
-            let cond = self.context.new_comparison(None, ComparisonOp::LessThan, res, lhs);
-            let value = self.context.new_unary_op(None, UnaryOp::Minus, res_type, self.context.new_cast(None, cond, res_type));
-            res | value
+            let res = self.gcc_add(lhs, rhs);
+            let cond = self.gcc_icmp(IntPredicate::IntULT, res, lhs);
+            let value = self.gcc_neg(self.gcc_int_cast(cond, result_type));
+            self.gcc_or(res, value)
         }
     }
 
     // Algorithm from: https://locklessinc.com/articles/sat_arithmetic/
     fn saturating_sub(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>, signed: bool, width: u64) -> RValue<'gcc> {
+        let result_type = lhs.get_type();
         if signed {
-            // Also based on algorithm from: https://stackoverflow.com/a/56531252/389119
-            let result_type = lhs.get_type();
+            // Based on algorithm from: https://stackoverflow.com/a/56531252/389119
             let func = self.current_func.borrow().expect("func");
             let res = func.new_local(None, result_type, "saturating_diff");
             let supports_native_type = self.is_native_int_type(result_type);
@@ -1059,6 +1079,7 @@ fn saturating_sub(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>, signed: bool,
             let then_block = func.new_block("then");
             let after_block = func.new_block("after");
 
+            // Return `result_type`'s maximum or minimum value on overflow
             // NOTE: convert the type to unsigned to have an unsigned shift.
             let unsigned_type = result_type.to_unsigned(&self.cx);
             let shifted = self.gcc_lshr(self.gcc_int_cast(lhs, unsigned_type), self.gcc_int(unsigned_type, width as i64 - 1));
@@ -1076,11 +1097,10 @@ fn saturating_sub(&mut self, lhs: RValue<'gcc>, rhs: RValue<'gcc>, signed: bool,
             res.to_rvalue()
         }
         else {
-            let res = lhs - rhs;
-            let comparison = self.context.new_comparison(None, ComparisonOp::LessThanEquals, res, lhs);
-            let comparison = self.context.new_cast(None, comparison, lhs.get_type());
-            let unary_op = self.context.new_unary_op(None, UnaryOp::Minus, comparison.get_type(), comparison);
-            self.and(res, unary_op)
+            let res = self.gcc_sub(lhs, rhs);
+            let comparison = self.gcc_icmp(IntPredicate::IntULE, res, lhs);
+            let value = self.gcc_neg(self.gcc_int_cast(comparison, result_type));
+            self.gcc_and(res, value)
         }
     }
 }

diff --git a/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs b/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs
index a613e117904ebb37e1d56b1b726b4898f827a4ec..870e9f776a4f08b4b9dbe2f2eec439a356a5ce1d 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs
+++ b/compiler/rustc_codegen_gcc/src/intrinsic/simd.rs
@@ -1,15 +1,20 @@
-use gccjit::{RValue, Type};
+use std::cmp::Ordering;
+
+use gccjit::{BinaryOp, RValue, Type, ToRValue};
 use rustc_codegen_ssa::base::compare_simd_types;
 use rustc_codegen_ssa::common::{TypeKind, span_invalid_monomorphization_error};
 use rustc_codegen_ssa::mir::operand::OperandRef;
+use rustc_codegen_ssa::mir::place::PlaceRef;
 use rustc_codegen_ssa::traits::{BaseTypeMethods, BuilderMethods};
 use rustc_hir as hir;
 use rustc_middle::span_bug;
 use rustc_middle::ty::layout::HasTyCtxt;
 use rustc_middle::ty::{self, Ty};
 use rustc_span::{Span, Symbol, sym};
+use rustc_target::abi::Align;
 
 use crate::builder::Builder;
+use crate::intrinsic;
 
 pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(bx: &mut Builder<'a, 'gcc, 'tcx>, name: Symbol, callee_ty: Ty<'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], ret_ty: Ty<'tcx>, llret_ty: Type<'gcc>, span: Span) -> Result<RValue<'gcc>, ()> {
     // macros for error handling:
@@ -53,7 +58,53 @@ macro_rules! require_simd {
     let sig =
         tcx.normalize_erasing_late_bound_regions(ty::ParamEnv::reveal_all(), callee_ty.fn_sig(tcx));
     let arg_tys = sig.inputs();
-    let name_str = name.as_str();
+
+    if name == sym::simd_select_bitmask {
+        require_simd!(arg_tys[1], "argument");
+        let (len, _) = arg_tys[1].simd_size_and_type(bx.tcx());
+
+        let expected_int_bits = (len.max(8) - 1).next_power_of_two();
+        let expected_bytes = len / 8 + ((len % 8 > 0) as u64);
+
+        let mask_ty = arg_tys[0];
+        let mut mask = match mask_ty.kind() {
+            ty::Int(i) if i.bit_width() == Some(expected_int_bits) => args[0].immediate(),
+            ty::Uint(i) if i.bit_width() == Some(expected_int_bits) => args[0].immediate(),
+            ty::Array(elem, len)
+                if matches!(elem.kind(), ty::Uint(ty::UintTy::U8))
+                    && len.try_eval_usize(bx.tcx, ty::ParamEnv::reveal_all())
+                        == Some(expected_bytes) =>
+            {
+                let place = PlaceRef::alloca(bx, args[0].layout);
+                args[0].val.store(bx, place);
+                let int_ty = bx.type_ix(expected_bytes * 8);
+                let ptr = bx.pointercast(place.llval, bx.cx.type_ptr_to(int_ty));
+                bx.load(int_ty, ptr, Align::ONE)
+            }
+            _ => return_error!(
+                "invalid bitmask `{}`, expected `u{}` or `[u8; {}]`",
+                mask_ty,
+                expected_int_bits,
+                expected_bytes
+            ),
+        };
+
+        let arg1 = args[1].immediate();
+        let arg1_type = arg1.get_type();
+        let arg1_vector_type = arg1_type.unqualified().dyncast_vector().expect("vector type");
+        let arg1_element_type = arg1_vector_type.get_element_type();
+
+        let mut elements = vec![];
+        let one = bx.context.new_rvalue_one(mask.get_type());
+        for _ in 0..len {
+            let element = bx.context.new_cast(None, mask & one, arg1_element_type);
+            elements.push(element);
+            mask = mask >> one;
+        }
+        let vector_mask = bx.context.new_rvalue_from_vector(None, arg1_type, &elements);
+
+        return Ok(bx.vector_select(vector_mask, arg1, args[2].immediate()));
+    }
 
     // every intrinsic below takes a SIMD vector as its first argument
     require_simd!(arg_tys[0], "input");
@@ -100,10 +151,28 @@ macro_rules! require_simd {
         ));
     }
 
-    if let Some(stripped) = name_str.strip_prefix("simd_shuffle") {
-        let n: u64 = stripped.parse().unwrap_or_else(|_| {
-            span_bug!(span, "bad `simd_shuffle` instruction only caught in codegen?")
-        });
+    if let Some(stripped) = name.as_str().strip_prefix("simd_shuffle") {
+        let n: u64 =
+            if stripped.is_empty() {
+                // Make sure this is actually an array, since typeck only checks the length-suffixed
+                // version of this intrinsic.
+                match args[2].layout.ty.kind() {
+                    ty::Array(ty, len) if matches!(ty.kind(), ty::Uint(ty::UintTy::U32)) => {
+                        len.try_eval_usize(bx.cx.tcx, ty::ParamEnv::reveal_all()).unwrap_or_else(|| {
+                            span_bug!(span, "could not evaluate shuffle index array length")
+                        })
+                    }
+                    _ => return_error!(
+                        "simd_shuffle index must be an array of `u32`, got `{}`",
+                        args[2].layout.ty
+                    ),
+                }
+            }
+            else {
+                stripped.parse().unwrap_or_else(|_| {
+                    span_bug!(span, "bad `simd_shuffle` instruction only caught in codegen?")
+                })
+            };
 
         require_simd!(ret_ty, "return");
 
@@ -134,6 +203,225 @@ macro_rules! require_simd {
         ));
     }
 
+    #[cfg(feature="master")]
+    if name == sym::simd_insert {
+        require!(
+            in_elem == arg_tys[2],
+            "expected inserted type `{}` (element of input `{}`), found `{}`",
+            in_elem,
+            in_ty,
+            arg_tys[2]
+        );
+        let vector = args[0].immediate();
+        let index = args[1].immediate();
+        let value = args[2].immediate();
+        // TODO(antoyo): use a recursive unqualified() here.
+        let vector_type = vector.get_type().unqualified().dyncast_vector().expect("vector type");
+        let element_type = vector_type.get_element_type();
+        // NOTE: we cannot cast to an array and assign to its element here because the value might
+        // not be an l-value. So, call a builtin to set the element.
+        // TODO(antoyo): perhaps we could create a new vector or maybe there's a GIMPLE instruction for that?
+        // TODO(antoyo): don't use target specific builtins here.
+        let func_name =
+            match in_len {
+                2 => {
+                    if element_type == bx.i64_type {
+                        "__builtin_ia32_vec_set_v2di"
+                    }
+                    else {
+                        unimplemented!();
+                    }
+                },
+                4 => {
+                    if element_type == bx.i32_type {
+                        "__builtin_ia32_vec_set_v4si"
+                    }
+                    else {
+                        unimplemented!();
+                    }
+                },
+                8 => {
+                    if element_type == bx.i16_type {
+                        "__builtin_ia32_vec_set_v8hi"
+                    }
+                    else {
+                        unimplemented!();
+                    }
+                },
+                _ => unimplemented!("Len: {}", in_len),
+            };
+        let builtin = bx.context.get_target_builtin_function(func_name);
+        let param1_type = builtin.get_param(0).to_rvalue().get_type();
+        // TODO(antoyo): perhaps use __builtin_convertvector for vector casting.
+        let vector = bx.cx.bitcast_if_needed(vector, param1_type);
+        let result = bx.context.new_call(None, builtin, &[vector, value, bx.context.new_cast(None, index, bx.int_type)]);
+        // TODO(antoyo): perhaps use __builtin_convertvector for vector casting.
+        return Ok(bx.context.new_bitcast(None, result, vector.get_type()));
+    }
+
+    #[cfg(feature="master")]
+    if name == sym::simd_extract {
+        require!(
+            ret_ty == in_elem,
+            "expected return type `{}` (element of input `{}`), found `{}`",
+            in_elem,
+            in_ty,
+            ret_ty
+        );
+        let vector = args[0].immediate();
+        return Ok(bx.context.new_vector_access(None, vector, args[1].immediate()).to_rvalue());
+    }
+
+    if name == sym::simd_select {
+        let m_elem_ty = in_elem;
+        let m_len = in_len;
+        require_simd!(arg_tys[1], "argument");
+        let (v_len, _) = arg_tys[1].simd_size_and_type(bx.tcx());
+        require!(
+            m_len == v_len,
+            "mismatched lengths: mask length `{}` != other vector length `{}`",
+            m_len,
+            v_len
+        );
+        match m_elem_ty.kind() {
+            ty::Int(_) => {}
+            _ => return_error!("mask element type is `{}`, expected `i_`", m_elem_ty),
+        }
+        return Ok(bx.vector_select(args[0].immediate(), args[1].immediate(), args[2].immediate()));
+    }
+
+    if name == sym::simd_cast {
+        require_simd!(ret_ty, "return");
+        let (out_len, out_elem) = ret_ty.simd_size_and_type(bx.tcx());
+        require!(
+            in_len == out_len,
+            "expected return type with length {} (same as input type `{}`), \
+                  found `{}` with length {}",
+            in_len,
+            in_ty,
+            ret_ty,
+            out_len
+        );
+        // casting cares about nominal type, not just structural type
+        if in_elem == out_elem {
+            return Ok(args[0].immediate());
+        }
+
+        enum Style {
+            Float,
+            Int(/* is signed? */ bool),
+            Unsupported,
+        }
+
+        let (in_style, in_width) = match in_elem.kind() {
+            // vectors of pointer-sized integers should've been
+            // disallowed before here, so this unwrap is safe.
+            ty::Int(i) => (
+                Style::Int(true),
+                i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(),
+            ),
+            ty::Uint(u) => (
+                Style::Int(false),
+                u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(),
+            ),
+            ty::Float(f) => (Style::Float, f.bit_width()),
+            _ => (Style::Unsupported, 0),
+        };
+        let (out_style, out_width) = match out_elem.kind() {
+            ty::Int(i) => (
+                Style::Int(true),
+                i.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(),
+            ),
+            ty::Uint(u) => (
+                Style::Int(false),
+                u.normalize(bx.tcx().sess.target.pointer_width).bit_width().unwrap(),
+            ),
+            ty::Float(f) => (Style::Float, f.bit_width()),
+            _ => (Style::Unsupported, 0),
+        };
+
+        let extend = |in_type, out_type| {
+            let vector_type = bx.context.new_vector_type(out_type, 8);
+            let vector = args[0].immediate();
+            let array_type = bx.context.new_array_type(None, in_type, 8);
+            // TODO(antoyo): switch to using new_vector_access or __builtin_convertvector for vector casting.
+            let array = bx.context.new_bitcast(None, vector, array_type);
+
+            let cast_vec_element = |index| {
+                let index = bx.context.new_rvalue_from_int(bx.int_type, index);
+                bx.context.new_cast(None, bx.context.new_array_access(None, array, index).to_rvalue(), out_type)
+            };
+
+            bx.context.new_rvalue_from_vector(None, vector_type, &[
+                cast_vec_element(0),
+                cast_vec_element(1),
+                cast_vec_element(2),
+                cast_vec_element(3),
+                cast_vec_element(4),
+                cast_vec_element(5),
+                cast_vec_element(6),
+                cast_vec_element(7),
+            ])
+        };
+
+        match (in_style, out_style) {
+            (Style::Int(in_is_signed), Style::Int(_)) => {
+                return Ok(match in_width.cmp(&out_width) {
+                    Ordering::Greater => bx.trunc(args[0].immediate(), llret_ty),
+                    Ordering::Equal => args[0].immediate(),
+                    Ordering::Less => {
+                        if in_is_signed {
+                            match (in_width, out_width) {
+                                // FIXME(antoyo): the function _mm_cvtepi8_epi16 should directly
+                                // call an intrinsic equivalent to __builtin_ia32_pmovsxbw128 so that
+                                // we can generate a call to it.
+                                (8, 16) => extend(bx.i8_type, bx.i16_type),
+                                (8, 32) => extend(bx.i8_type, bx.i32_type),
+                                (8, 64) => extend(bx.i8_type, bx.i64_type),
+                                (16, 32) => extend(bx.i16_type, bx.i32_type),
+                                (32, 64) => extend(bx.i32_type, bx.i64_type),
+                                (16, 64) => extend(bx.i16_type, bx.i64_type),
+                                _ => unimplemented!("in: {}, out: {}", in_width, out_width),
+                            }
+                        } else {
+                            match (in_width, out_width) {
+                                (8, 16) => extend(bx.u8_type, bx.u16_type),
+                                (8, 32) => extend(bx.u8_type, bx.u32_type),
+                                (8, 64) => extend(bx.u8_type, bx.u64_type),
+                                (16, 32) => extend(bx.u16_type, bx.u32_type),
+                                (16, 64) => extend(bx.u16_type, bx.u64_type),
+                                (32, 64) => extend(bx.u32_type, bx.u64_type),
+                                _ => unimplemented!("in: {}, out: {}", in_width, out_width),
+                            }
+                        }
+                    }
+                });
+            }
+            (Style::Int(_), Style::Float) => {
+                // TODO: add support for internal functions in libgccjit to get access to IFN_VEC_CONVERT which is
+                // doing like __builtin_convertvector?
+                // Or maybe provide convert_vector as an API since it might not easy to get the
+                // types of internal functions.
+                unimplemented!();
+            }
+            (Style::Float, Style::Int(_)) => {
+                unimplemented!();
+            }
+            (Style::Float, Style::Float) => {
+                unimplemented!();
+            }
+            _ => { /* Unsupported. Fallthrough. */ }
+        }
+        require!(
+            false,
+            "unsupported cast from `{}` with element `{}` to `{}` with element `{}`",
+            in_ty,
+            in_elem,
+            ret_ty,
+            out_elem
+        );
+    }
+
     macro_rules! arith_binary {
         ($($name: ident: $($($p: ident),* => $call: ident),*;)*) => {
             $(if name == sym::$name {
@@ -151,6 +439,105 @@ macro_rules! arith_binary {
         }
     }
 
+    fn simd_simple_float_intrinsic<'gcc, 'tcx>(
+        name: Symbol,
+        in_elem: Ty<'_>,
+        in_ty: Ty<'_>,
+        in_len: u64,
+        bx: &mut Builder<'_, 'gcc, 'tcx>,
+        span: Span,
+        args: &[OperandRef<'tcx, RValue<'gcc>>],
+    ) -> Result<RValue<'gcc>, ()> {
+        macro_rules! emit_error {
+            ($msg: tt) => {
+                emit_error!($msg, )
+            };
+            ($msg: tt, $($fmt: tt)*) => {
+                span_invalid_monomorphization_error(
+                    bx.sess(), span,
+                    &format!(concat!("invalid monomorphization of `{}` intrinsic: ", $msg),
+                             name, $($fmt)*));
+            }
+        }
+        macro_rules! return_error {
+            ($($fmt: tt)*) => {
+                {
+                    emit_error!($($fmt)*);
+                    return Err(());
+                }
+            }
+        }
+
+        let (elem_ty_str, elem_ty) =
+            if let ty::Float(f) = in_elem.kind() {
+                let elem_ty = bx.cx.type_float_from_ty(*f);
+                match f.bit_width() {
+                    32 => ("f32", elem_ty),
+                    64 => ("f64", elem_ty),
+                    _ => {
+                        return_error!(
+                            "unsupported element type `{}` of floating-point vector `{}`",
+                            f.name_str(),
+                            in_ty
+                        );
+                    }
+                }
+            }
+            else {
+                return_error!("`{}` is not a floating-point type", in_ty);
+            };
+
+        let vec_ty = bx.cx.type_vector(elem_ty, in_len);
+
+        let (intr_name, fn_ty) =
+            match name {
+                sym::simd_ceil => ("ceil", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_fabs => ("fabs", bx.type_func(&[vec_ty], vec_ty)), // TODO(antoyo): pand with 170141183420855150465331762880109871103
+                sym::simd_fcos => ("cos", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_fexp2 => ("exp2", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_fexp => ("exp", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_flog10 => ("log10", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_flog2 => ("log2", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_flog => ("log", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_floor => ("floor", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_fma => ("fma", bx.type_func(&[vec_ty, vec_ty, vec_ty], vec_ty)),
+                sym::simd_fpowi => ("powi", bx.type_func(&[vec_ty, bx.type_i32()], vec_ty)),
+                sym::simd_fpow => ("pow", bx.type_func(&[vec_ty, vec_ty], vec_ty)),
+                sym::simd_fsin => ("sin", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_fsqrt => ("sqrt", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_round => ("round", bx.type_func(&[vec_ty], vec_ty)),
+                sym::simd_trunc => ("trunc", bx.type_func(&[vec_ty], vec_ty)),
+                _ => return_error!("unrecognized intrinsic `{}`", name),
+            };
+        let llvm_name = &format!("llvm.{0}.v{1}{2}", intr_name, in_len, elem_ty_str);
+        let function = intrinsic::llvm::intrinsic(llvm_name, &bx.cx);
+        let function: RValue<'gcc> = unsafe { std::mem::transmute(function) };
+        let c = bx.call(fn_ty, function, &args.iter().map(|arg| arg.immediate()).collect::<Vec<_>>(), None);
+        Ok(c)
+    }
+
+    if std::matches!(
+        name,
+        sym::simd_ceil
+            | sym::simd_fabs
+            | sym::simd_fcos
+            | sym::simd_fexp2
+            | sym::simd_fexp
+            | sym::simd_flog10
+            | sym::simd_flog2
+            | sym::simd_flog
+            | sym::simd_floor
+            | sym::simd_fma
+            | sym::simd_fpow
+            | sym::simd_fpowi
+            | sym::simd_fsin
+            | sym::simd_fsqrt
+            | sym::simd_round
+            | sym::simd_trunc
+    ) {
+        return simd_simple_float_intrinsic(name, in_elem, in_ty, in_len, bx, span, args);
+    }
+
     arith_binary! {
         simd_add: Uint, Int => add, Float => fadd;
         simd_sub: Uint, Int => sub, Float => fsub;
@@ -185,5 +572,183 @@ macro_rules! arith_unary {
         simd_neg: Int => neg, Float => fneg;
     }
 
+    #[cfg(feature="master")]
+    if name == sym::simd_saturating_add || name == sym::simd_saturating_sub {
+        let lhs = args[0].immediate();
+        let rhs = args[1].immediate();
+        let is_add = name == sym::simd_saturating_add;
+        let ptr_bits = bx.tcx().data_layout.pointer_size.bits() as _;
+        let (signed, elem_width, elem_ty) = match *in_elem.kind() {
+            ty::Int(i) => (true, i.bit_width().unwrap_or(ptr_bits), bx.cx.type_int_from_ty(i)),
+            ty::Uint(i) => (false, i.bit_width().unwrap_or(ptr_bits), bx.cx.type_uint_from_ty(i)),
+            _ => {
+                return_error!(
+                    "expected element type `{}` of vector type `{}` \
+                     to be a signed or unsigned integer type",
+                    arg_tys[0].simd_size_and_type(bx.tcx()).1,
+                    arg_tys[0]
+                );
+            }
+        };
+        let builtin_name =
+            match (signed, is_add, in_len, elem_width) {
+                (true, true, 32, 8) => "__builtin_ia32_paddsb256", // TODO(antoyo): cast arguments to unsigned.
+                (false, true, 32, 8) => "__builtin_ia32_paddusb256",
+                (true, true, 16, 16) => "__builtin_ia32_paddsw256",
+                (false, true, 16, 16) => "__builtin_ia32_paddusw256",
+                (true, false, 16, 16) => "__builtin_ia32_psubsw256",
+                (false, false, 16, 16) => "__builtin_ia32_psubusw256",
+                (true, false, 32, 8) => "__builtin_ia32_psubsb256",
+                (false, false, 32, 8) => "__builtin_ia32_psubusb256",
+                _ => unimplemented!("signed: {}, is_add: {}, in_len: {}, elem_width: {}", signed, is_add, in_len, elem_width),
+            };
+        let vec_ty = bx.cx.type_vector(elem_ty, in_len as u64);
+
+        let func = bx.context.get_target_builtin_function(builtin_name);
+        let param1_type = func.get_param(0).to_rvalue().get_type();
+        let param2_type = func.get_param(1).to_rvalue().get_type();
+        let lhs = bx.cx.bitcast_if_needed(lhs, param1_type);
+        let rhs = bx.cx.bitcast_if_needed(rhs, param2_type);
+        let result = bx.context.new_call(None, func, &[lhs, rhs]);
+        // TODO(antoyo): perhaps use __builtin_convertvector for vector casting.
+        return Ok(bx.context.new_bitcast(None, result, vec_ty));
+    }
+
+    macro_rules! arith_red {
+        ($name:ident : $vec_op:expr, $float_reduce:ident, $ordered:expr, $op:ident,
+         $identity:expr) => {
+            if name == sym::$name {
+                require!(
+                    ret_ty == in_elem,
+                    "expected return type `{}` (element of input `{}`), found `{}`",
+                    in_elem,
+                    in_ty,
+                    ret_ty
+                );
+                return match in_elem.kind() {
+                    ty::Int(_) | ty::Uint(_) => {
+                        let r = bx.vector_reduce_op(args[0].immediate(), $vec_op);
+                        if $ordered {
+                            // if overflow occurs, the result is the
+                            // mathematical result modulo 2^n:
+                            Ok(bx.$op(args[1].immediate(), r))
+                        }
+                        else {
+                            Ok(bx.vector_reduce_op(args[0].immediate(), $vec_op))
+                        }
+                    }
+                    ty::Float(_) => {
+                        if $ordered {
+                            // ordered arithmetic reductions take an accumulator
+                            let acc = args[1].immediate();
+                            Ok(bx.$float_reduce(acc, args[0].immediate()))
+                        }
+                        else {
+                            Ok(bx.vector_reduce_op(args[0].immediate(), $vec_op))
+                        }
+                    }
+                    _ => return_error!(
+                        "unsupported {} from `{}` with element `{}` to `{}`",
+                        sym::$name,
+                        in_ty,
+                        in_elem,
+                        ret_ty
+                    ),
+                };
+            }
+        };
+    }
+
+    arith_red!(
+        simd_reduce_add_unordered: BinaryOp::Plus,
+        vector_reduce_fadd_fast,
+        false,
+        add,
+        0.0 // TODO: Use this argument.
+    );
+    arith_red!(
+        simd_reduce_mul_unordered: BinaryOp::Mult,
+        vector_reduce_fmul_fast,
+        false,
+        mul,
+        1.0
+    );
+
+    macro_rules! minmax_red {
+        ($name:ident: $reduction:ident) => {
+            if name == sym::$name {
+                require!(
+                    ret_ty == in_elem,
+                    "expected return type `{}` (element of input `{}`), found `{}`",
+                    in_elem,
+                    in_ty,
+                    ret_ty
+                );
+                return match in_elem.kind() {
+                    ty::Int(_) | ty::Uint(_) | ty::Float(_) => Ok(bx.$reduction(args[0].immediate())),
+                    _ => return_error!(
+                        "unsupported {} from `{}` with element `{}` to `{}`",
+                        sym::$name,
+                        in_ty,
+                        in_elem,
+                        ret_ty
+                    ),
+                };
+            }
+        };
+    }
+
+    minmax_red!(simd_reduce_min: vector_reduce_min);
+    minmax_red!(simd_reduce_max: vector_reduce_max);
+
+    macro_rules! bitwise_red {
+        ($name:ident : $op:expr, $boolean:expr) => {
+            if name == sym::$name {
+                let input = if !$boolean {
+                    require!(
+                        ret_ty == in_elem,
+                        "expected return type `{}` (element of input `{}`), found `{}`",
+                        in_elem,
+                        in_ty,
+                        ret_ty
+                    );
+                    args[0].immediate()
+                } else {
+                    match in_elem.kind() {
+                        ty::Int(_) | ty::Uint(_) => {}
+                        _ => return_error!(
+                            "unsupported {} from `{}` with element `{}` to `{}`",
+                            sym::$name,
+                            in_ty,
+                            in_elem,
+                            ret_ty
+                        ),
+                    }
+
+                    // boolean reductions operate on vectors of i1s:
+                    let i1 = bx.type_i1();
+                    let i1xn = bx.type_vector(i1, in_len as u64);
+                    bx.trunc(args[0].immediate(), i1xn)
+                };
+                return match in_elem.kind() {
+                    ty::Int(_) | ty::Uint(_) => {
+                        let r = bx.vector_reduce_op(input, $op);
+                        Ok(if !$boolean { r } else { bx.zext(r, bx.type_bool()) })
+                    }
+                    _ => return_error!(
+                        "unsupported {} from `{}` with element `{}` to `{}`",
+                        sym::$name,
+                        in_ty,
+                        in_elem,
+                        ret_ty
+                    ),
+                };
+            }
+        };
+    }
+
+    bitwise_red!(simd_reduce_and: BinaryOp::BitwiseAnd, false);
+    bitwise_red!(simd_reduce_or: BinaryOp::BitwiseOr, false);
+
     unimplemented!("simd {}", name);
 }

diff --git a/compiler/rustc_codegen_gcc/src/lib.rs b/compiler/rustc_codegen_gcc/src/lib.rs
index 58996a9db78ad4e0dfbd315ea85af833e7137413..5bfdeb8b93a484fc4077f1efad4372155e5c6137 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/lib.rs
+++ b/compiler/rustc_codegen_gcc/src/lib.rs
@@ -203,7 +203,7 @@ impl WriteBackendMethods for GccCodegenBackend {
     fn run_fat_lto(_cgcx: &CodegenContext<Self>, mut modules: Vec<FatLTOInput<Self>>, _cached_modules: Vec<(SerializedModule<Self::ModuleBuffer>, WorkProduct)>) -> Result<LtoModuleCodegen<Self>, FatalError> {
         // TODO(antoyo): implement LTO by sending -flto to libgccjit and adding the appropriate gcc linker plugins.
         // NOTE: implemented elsewhere.
-        // TODO: what is implemented elsewhere ^ ?
+        // TODO(antoyo): what is implemented elsewhere ^ ?
         let module =
             match modules.remove(0) {
                 FatLTOInput::InMemory(module) => module,
@@ -301,7 +301,22 @@ pub fn target_features(sess: &Session) -> Vec<Symbol> {
         )
         .filter(|_feature| {
             // TODO(antoyo): implement a way to get enabled feature in libgccjit.
-            false
+            // Probably using the equivalent of __builtin_cpu_supports.
+            #[cfg(feature="master")]
+            {
+                _feature.contains("sse") || _feature.contains("avx")
+            }
+            #[cfg(not(feature="master"))]
+            {
+                false
+            }
+            /*
+               adx, aes, avx, avx2, avx512bf16, avx512bitalg, avx512bw, avx512cd, avx512dq, avx512er, avx512f, avx512gfni,
+               avx512ifma, avx512pf, avx512vaes, avx512vbmi, avx512vbmi2, avx512vl, avx512vnni, avx512vp2intersect, avx512vpclmulqdq,
+               avx512vpopcntdq, bmi1, bmi2, cmpxchg16b, ermsb, f16c, fma, fxsr, lzcnt, movbe, pclmulqdq, popcnt, rdrand, rdseed, rtm,
+               sha, sse, sse2, sse3, sse4.1, sse4.2, sse4a, ssse3, tbm, xsave, xsavec, xsaveopt, xsaves
+             */
+            //false
         })
         .map(|feature| Symbol::intern(feature))
         .collect()

diff --git a/compiler/rustc_codegen_gcc/src/type_.rs b/compiler/rustc_codegen_gcc/src/type_.rs
index e95058085216e94aa9482e579ad4b21097e29b33..002b95db36deef85e6b2a145bfe1e1415d8c1eb5 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/type_.rs
+++ b/compiler/rustc_codegen_gcc/src/type_.rs
@@ -3,10 +3,11 @@
 use gccjit::{RValue, Struct, Type};
 use rustc_codegen_ssa::traits::{BaseTypeMethods, DerivedTypeMethods};
 use rustc_codegen_ssa::common::TypeKind;
-use rustc_middle::bug;
+use rustc_middle::{bug, ty};
 use rustc_middle::ty::layout::TyAndLayout;
 use rustc_target::abi::{AddressSpace, Align, Integer, Size};
 
+use crate::common::TypeReflection;
 use crate::context::CodegenCx;
 use crate::type_of::LayoutGccExt;
 
@@ -60,6 +61,17 @@ pub fn type_pointee_for_align(&self, align: Align) -> Type<'gcc> {
         let ity = Integer::approximate_align(self, align);
         self.type_from_integer(ity)
     }
+
+    pub fn type_vector(&self, ty: Type<'gcc>, len: u64) -> Type<'gcc> {
+        self.context.new_vector_type(ty, len)
+    }
+
+    pub fn type_float_from_ty(&self, t: ty::FloatTy) -> Type<'gcc> {
+        match t {
+            ty::FloatTy::F32 => self.type_f32(),
+            ty::FloatTy::F64 => self.type_f64(),
+        }
+    }
 }
 
 impl<'gcc, 'tcx> BaseTypeMethods<'tcx> for CodegenCx<'gcc, 'tcx> {
@@ -103,7 +115,7 @@ fn type_func(&self, params: &[Type<'gcc>], return_type: Type<'gcc>) -> Type<'gcc
         self.context.new_function_pointer_type(None, return_type, params, false)
     }
 
-    fn type_struct(&self, fields: &[Type<'gcc>], _packed: bool) -> Type<'gcc> {
+    fn type_struct(&self, fields: &[Type<'gcc>], packed: bool) -> Type<'gcc> {
         let types = fields.to_vec();
         if let Some(typ) = self.struct_types.borrow().get(fields) {
             return typ.clone();
@@ -111,8 +123,11 @@ fn type_struct(&self, fields: &[Type<'gcc>], _packed: bool) -> Type<'gcc> {
         let fields: Vec<_> = fields.iter().enumerate()
             .map(|(index, field)| self.context.new_field(None, *field, &format!("field{}_TODO", index)))
             .collect();
-        // TODO(antoyo): use packed.
         let typ = self.context.new_struct_type(None, "struct", &fields).as_type();
+        if packed {
+            #[cfg(feature="master")]
+            typ.set_packed();
+        }
         self.struct_types.borrow_mut().insert(types, typ);
         typ
     }
@@ -127,7 +142,7 @@ fn type_kind(&self, typ: Type<'gcc>) -> TypeKind {
         else if typ.is_compatible_with(self.double_type) {
             TypeKind::Double
         }
-        else if typ.dyncast_vector().is_some() {
+        else if typ.is_vector() {
             TypeKind::Vector
         }
         else {
@@ -141,7 +156,7 @@ fn type_ptr_to(&self, ty: Type<'gcc>) -> Type<'gcc> {
     }
 
     fn type_ptr_to_ext(&self, ty: Type<'gcc>, _address_space: AddressSpace) -> Type<'gcc> {
-        // TODO(antoyo): use address_space
+        // TODO(antoyo): use address_space, perhaps with TYPE_ADDR_SPACE?
         ty.make_pointer()
     }
 
@@ -167,10 +182,10 @@ fn vector_length(&self, _ty: Type<'gcc>) -> usize {
     fn float_width(&self, typ: Type<'gcc>) -> usize {
         let f32 = self.context.new_type::<f32>();
         let f64 = self.context.new_type::<f64>();
-        if typ == f32 {
+        if typ.is_compatible_with(f32) {
             32
         }
-        else if typ == f64 {
+        else if typ.is_compatible_with(f64) {
             64
         }
         else {
@@ -197,12 +212,15 @@ pub fn type_padding_filler(&self, size: Size, align: Align) -> Type<'gcc> {
         self.type_array(self.type_from_integer(unit), size / unit_size)
     }
 
-    pub fn set_struct_body(&self, typ: Struct<'gcc>, fields: &[Type<'gcc>], _packed: bool) {
-        // TODO(antoyo): use packed.
+    pub fn set_struct_body(&self, typ: Struct<'gcc>, fields: &[Type<'gcc>], packed: bool) {
         let fields: Vec<_> = fields.iter().enumerate()
             .map(|(index, field)| self.context.new_field(None, *field, &format!("field_{}", index)))
             .collect();
         typ.set_fields(None, &fields);
+        if packed {
+            #[cfg(feature="master")]
+            typ.as_type().set_packed();
+        }
     }
 
     pub fn type_named_struct(&self, name: &str) -> Struct<'gcc> {
@@ -229,6 +247,10 @@ pub fn type_array(&self, ty: Type<'gcc>, mut len: u64) -> Type<'gcc> {
 
         self.context.new_array_type(None, ty, len)
     }
+
+    pub fn type_bool(&self) -> Type<'gcc> {
+        self.context.new_type::<bool>()
+    }
 }
 
 pub fn struct_fields<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>) -> (Vec<Type<'gcc>>, bool) {

diff --git a/compiler/rustc_codegen_gcc/src/type_of.rs b/compiler/rustc_codegen_gcc/src/type_of.rs
index 2c042ba4e3a9e99780bb9c900a0fe91a60b5422b..569ee2925b13c1785c9695ca80f708c912478774 100644 (file)
--- a/compiler/rustc_codegen_gcc/src/type_of.rs
+++ b/compiler/rustc_codegen_gcc/src/type_of.rs
@@ -24,6 +24,30 @@ fn type_from_unsigned_integer(&self, i: Integer) -> Type<'gcc> {
             I128 => self.type_u128(),
         }
     }
+
+    #[cfg(feature="master")]
+    pub fn type_int_from_ty(&self, t: ty::IntTy) -> Type<'gcc> {
+        match t {
+            ty::IntTy::Isize => self.type_isize(),
+            ty::IntTy::I8 => self.type_i8(),
+            ty::IntTy::I16 => self.type_i16(),
+            ty::IntTy::I32 => self.type_i32(),
+            ty::IntTy::I64 => self.type_i64(),
+            ty::IntTy::I128 => self.type_i128(),
+        }
+    }
+
+    #[cfg(feature="master")]
+    pub fn type_uint_from_ty(&self, t: ty::UintTy) -> Type<'gcc> {
+        match t {
+            ty::UintTy::Usize => self.type_isize(),
+            ty::UintTy::U8 => self.type_i8(),
+            ty::UintTy::U16 => self.type_i16(),
+            ty::UintTy::U32 => self.type_i32(),
+            ty::UintTy::U64 => self.type_i64(),
+            ty::UintTy::U128 => self.type_i128(),
+        }
+    }
 }
 
 pub fn uncached_gcc_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, layout: TyAndLayout<'tcx>, defer: &mut Option<(Struct<'gcc>, TyAndLayout<'tcx>)>) -> Type<'gcc> {

diff --git a/compiler/rustc_codegen_gcc/test.sh b/compiler/rustc_codegen_gcc/test.sh
index 1beeee136df3106401aed9afdbde9919c8238fd8..8b390f95a4b9b54a8cbe7512723b89d82750f266 100755 (executable)
--- a/compiler/rustc_codegen_gcc/test.sh
+++ b/compiler/rustc_codegen_gcc/test.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 # TODO(antoyo): rewrite to cargo-make (or just) or something like that to only rebuild the sysroot when needed?
 
@@ -14,25 +14,87 @@ fi
 export LD_LIBRARY_PATH="$GCC_PATH"
 export LIBRARY_PATH="$GCC_PATH"
 
-features=
-
-if [[ "$1" == "--features" ]]; then
-    shift
-    features="--features $1"
-    shift
-fi
-
-if [[ "$1" == "--release" ]]; then
+flags=
+gcc_master_branch=1
+channel="debug"
+func=all
+build_only=0
+
+while [[ $# -gt 0 ]]; do
+    case $1 in
+        --release)
+            codegen_channel=release
+            shift
+            ;;
+        --release-sysroot)
+            sysroot_channel=release
+            shift
+            ;;
+        --no-default-features)
+            gcc_master_branch=0
+            flags="$flags --no-default-features"
+            shift
+            ;;
+        --features)
+            shift
+            flags="$flags --features $1"
+            shift
+            ;;
+        --release)
+            channel="release"
+            shift
+            ;;
+        "--test-rustc")
+            func=test_rustc
+            shift
+            ;;
+
+        "--test-libcore")
+            func=test_libcore
+            shift
+            ;;
+
+        "--clean-ui-tests")
+            func=clean_ui_tests
+            shift
+            ;;
+
+        "--std-tests")
+            func=std_tests
+            shift
+            ;;
+
+        "--extended-tests")
+            func=extended_sysroot_tests
+            shift
+            ;;
+
+        "--build-sysroot")
+            func=build_sysroot
+            shift
+            ;;
+        "--build")
+            build_only=1
+            shift
+            ;;
+        *)
+            echo "Unknown option $1"
+            exit 1
+            ;;
+    esac
+done
+
+if [[ $channel == "release" ]]; then
     export CHANNEL='release'
-    CARGO_INCREMENTAL=1 cargo rustc --release $features
+    CARGO_INCREMENTAL=1 cargo rustc --release $flags
     shift
 else
     echo $LD_LIBRARY_PATH
     export CHANNEL='debug'
-    cargo rustc $features
+    cargo rustc $flags
 fi
 
-if [[ "$1" == "--build" ]]; then
+if (( $build_only == 1 )); then
     exit
 fi
 
@@ -78,7 +140,11 @@ function std_tests() {
     $RUN_WRAPPER ./target/out/dst_field_align || (echo $?; false)
 
     echo "[AOT] std_example"
-    $RUSTC example/std_example.rs --crate-type bin --target $TARGET_TRIPLE
+    std_flags="--cfg feature=\"master\""
+    if (( $gcc_master_branch == 0 )); then
+        std_flags=""
+    fi
+    $RUSTC example/std_example.rs --crate-type bin --target $TARGET_TRIPLE $std_flags
     $RUN_WRAPPER ./target/out/std_example --target $TARGET_TRIPLE
 
     echo "[AOT] subslice-patterns-const-eval"
@@ -97,25 +163,6 @@ function std_tests() {
 #echo "[BUILD] sysroot in release mode"
 #./build_sysroot/build_sysroot.sh --release
 
-# TODO(antoyo): uncomment when it works.
-#pushd simple-raytracer
-#if [[ "$HOST_TRIPLE" = "$TARGET_TRIPLE" ]]; then
-    #echo "[BENCH COMPILE] ebobby/simple-raytracer"
-    #hyperfine --runs ${RUN_RUNS:-10} --warmup 1 --prepare "rm -r target/*/debug || true" \
-    #"RUSTFLAGS='' cargo build --target $TARGET_TRIPLE" \
-    #"../cargo.sh build"
-
-    #echo "[BENCH RUN] ebobby/simple-raytracer"
-    #cp ./target/*/debug/main ./raytracer_cg_gccjit
-    #hyperfine --runs ${RUN_RUNS:-10} ./raytracer_cg_llvm ./raytracer_cg_gccjit
-#else
-    #echo "[BENCH COMPILE] ebobby/simple-raytracer (skipped)"
-    #echo "[COMPILE] ebobby/simple-raytracer"
-    #../cargo.sh build
-    #echo "[BENCH RUN] ebobby/simple-raytracer (skipped)"
-#fi
-#popd
-
 function test_libcore() {
     pushd build_sysroot/sysroot_src/library/core/tests
     echo "[TEST] libcore"
@@ -124,19 +171,6 @@ function test_libcore() {
     popd
 }
 
-# TODO(antoyo): uncomment when it works.
-#pushd regex
-#echo "[TEST] rust-lang/regex example shootout-regex-dna"
-#../cargo.sh clean
-## Make sure `[codegen mono items] start` doesn't poison the diff
-#../cargo.sh build --example shootout-regex-dna
-#cat examples/regexdna-input.txt | ../cargo.sh run --example shootout-regex-dna | grep -v "Spawned thread" > res.txt
-#diff -u res.txt examples/regexdna-output.txt
-
-#echo "[TEST] rust-lang/regex tests"
-#../cargo.sh test --tests -- --exclude-should-panic --test-threads 1 -Zunstable-options
-#popd
-
 #echo
 #echo "[BENCH COMPILE] mod_bench"
 
@@ -153,6 +187,44 @@ function test_libcore() {
 #echo "[BENCH RUN] mod_bench"
 #hyperfine --runs ${RUN_RUNS:-10} ./target/out/mod_bench{,_inline} ./target/out/mod_bench_llvm_*
 
+function extended_sysroot_tests() {
+    if (( $gcc_master_branch == 0 )); then
+        return
+    fi
+
+    pushd rand
+    cargo clean
+    echo "[TEST] rust-random/rand"
+    ../cargo.sh test --workspace
+    popd
+
+    #pushd simple-raytracer
+    #echo "[BENCH COMPILE] ebobby/simple-raytracer"
+    #hyperfine --runs "${RUN_RUNS:-10}" --warmup 1 --prepare "cargo clean" \
+    #"RUSTC=rustc RUSTFLAGS='' cargo build" \
+    #"../cargo.sh build"
+
+    #echo "[BENCH RUN] ebobby/simple-raytracer"
+    #cp ./target/debug/main ./raytracer_cg_gcc
+    #hyperfine --runs "${RUN_RUNS:-10}" ./raytracer_cg_llvm ./raytracer_cg_gcc
+    #popd
+
+    pushd regex
+    echo "[TEST] rust-lang/regex example shootout-regex-dna"
+    cargo clean
+    export CG_RUSTFLAGS="--cap-lints warn" # newer aho_corasick versions throw a deprecation warning
+    # Make sure `[codegen mono items] start` doesn't poison the diff
+    ../cargo.sh build --example shootout-regex-dna
+    cat examples/regexdna-input.txt \
+        | ../cargo.sh run --example shootout-regex-dna \
+        | grep -v "Spawned thread" > res.txt
+    diff -u res.txt examples/regexdna-output.txt
+
+    echo "[TEST] rust-lang/regex tests"
+    ../cargo.sh test --tests -- --exclude-should-panic --test-threads 1 -Zunstable-options -q
+    popd
+}
+
 function test_rustc() {
     echo
     echo "[TEST] rust-lang/rust"
@@ -165,23 +237,7 @@ function test_rustc() {
     git checkout $(rustc -V | cut -d' ' -f3 | tr -d '(')
     export RUSTFLAGS=
 
-    git apply - <<EOF
-diff --git a/src/tools/compiletest/src/header.rs b/src/tools/compiletest/src/header.rs
-index 887d27fd6dca4..2c2239f2b83d1 100644
---- a/src/tools/compiletest/src/header.rs
-+++ b/src/tools/compiletest/src/header.rs
-@@ -806,8 +806,8 @@ pub fn make_test_description<R: Read>(
-     cfg: Option<&str>,
- ) -> test::TestDesc {
-     let mut ignore = false;
-     #[cfg(not(bootstrap))]
--    let ignore_message: Option<String> = None;
-+    let ignore_message: Option<&str> = None;
-     let mut should_fail = false;
-
-     let rustc_has_profiler_support = env::var_os("RUSTC_PROFILER_SUPPORT").is_some();
-
-EOF
+    git apply ../rustc_patches/compile_test.patch || true
 
     rm config.toml || true
 
@@ -205,7 +261,7 @@ EOF
 
     git checkout -- src/test/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed
 
-    rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,simd*,borrowck/,test*,*lto*.rs} || true
+    rm -r src/test/ui/{abi*,extern/,panic-runtime/,panics/,unsized-locals/,proc-macro/,threads-sendsync/,thinlto/,borrowck/,test*,*lto*.rs} || true
     for test in $(rg --files-with-matches "catch_unwind|should_panic|thread|lto" src/test/ui); do
       rm $test
     done
@@ -222,33 +278,14 @@ function clean_ui_tests() {
     find rust/build/x86_64-unknown-linux-gnu/test/ui/ -name stamp -exec rm -rf {} \;
 }
 
-case $1 in
-    "--test-rustc")
-        test_rustc
-        ;;
-
-    "--test-libcore")
-        test_libcore
-        ;;
-
-    "--clean-ui-tests")
-        clean_ui_tests
-        ;;
-
-    "--std-tests")
-        std_tests
-        ;;
-
-    "--build-sysroot")
-        build_sysroot
-        ;;
-
-    *)
-        clean
-        mini_tests
-        build_sysroot
-        std_tests
-        test_libcore
-        test_rustc
-        ;;
-esac
+function all() {
+    clean
+    mini_tests
+    build_sysroot
+    std_tests
+    test_libcore
+    extended_sysroot_tests
+    test_rustc
+}
+
+$func

diff --git a/compiler/rustc_codegen_gcc/tests/lang_tests_common.rs b/compiler/rustc_codegen_gcc/tests/lang_tests_common.rs
new file mode 100644 (file)
index 0000000..8e37817
--- /dev/null
+++ b/compiler/rustc_codegen_gcc/tests/lang_tests_common.rs
@@ -0,0 +1,68 @@
+//! The common code for `tests/lang_tests_*.rs`
+use std::{
+    env::{self, current_dir},
+    path::PathBuf,
+    process::Command,
+};
+
+use lang_tester::LangTester;
+use tempfile::TempDir;
+
+/// Controls the compile options (e.g., optimization level) used to compile
+/// test code.
+#[allow(dead_code)] // Each test crate picks one variant
+pub enum Profile {
+    Debug,
+    Release,
+}
+
+pub fn main_inner(profile: Profile) {
+    let tempdir = TempDir::new().expect("temp dir");
+    let current_dir = current_dir().expect("current dir");
+    let current_dir = current_dir.to_str().expect("current dir").to_string();
+    let gcc_path = include_str!("../gcc_path");
+    let gcc_path = gcc_path.trim();
+    env::set_var("LD_LIBRARY_PATH", gcc_path);
+    LangTester::new()
+        .test_dir("tests/run")
+        .test_file_filter(|path| path.extension().expect("extension").to_str().expect("to_str") == "rs")
+        .test_extract(|source| {
+            let lines =
+                source.lines()
+                    .skip_while(|l| !l.starts_with("//"))
+                    .take_while(|l| l.starts_with("//"))
+                    .map(|l| &l[2..])
+                    .collect::<Vec<_>>()
+                    .join("\n");
+            Some(lines)
+        })
+        .test_cmds(move |path| {
+            // Test command 1: Compile `x.rs` into `tempdir/x`.
+            let mut exe = PathBuf::new();
+            exe.push(&tempdir);
+            exe.push(path.file_stem().expect("file_stem"));
+            let mut compiler = Command::new("rustc");
+            compiler.args(&[
+                &format!("-Zcodegen-backend={}/target/debug/librustc_codegen_gcc.so", current_dir),
+                "--sysroot", &format!("{}/build_sysroot/sysroot/", current_dir),
+                "-Zno-parallel-llvm",
+                "-C", "panic=abort",
+                "-C", "link-arg=-lc",
+                "-o", exe.to_str().expect("to_str"),
+                path.to_str().expect("to_str"),
+            ]);
+            match profile {
+                Profile::Debug => {}
+                Profile::Release => {
+                    compiler.args(&[
+                        "-C", "opt-level=3",
+                        "-C", "lto=no",
+                    ]);
+                }
+            }
+            // Test command 2: run `tempdir/x`.
+            let runtime = Command::new(exe);
+            vec![("Compiler", compiler), ("Run-time", runtime)]
+        })
+        .run();
+}

diff --git a/compiler/rustc_codegen_gcc/tests/lang_tests_debug.rs b/compiler/rustc_codegen_gcc/tests/lang_tests_debug.rs
new file mode 100644 (file)
index 0000000..96bd748
--- /dev/null
+++ b/compiler/rustc_codegen_gcc/tests/lang_tests_debug.rs
@@ -0,0 +1,5 @@
+mod lang_tests_common;
+
+fn main() {
+    lang_tests_common::main_inner(lang_tests_common::Profile::Debug);
+}

diff --git a/compiler/rustc_codegen_gcc/tests/lang_tests_release.rs b/compiler/rustc_codegen_gcc/tests/lang_tests_release.rs
new file mode 100644 (file)
index 0000000..35d5d60
--- /dev/null
+++ b/compiler/rustc_codegen_gcc/tests/lang_tests_release.rs
@@ -0,0 +1,5 @@
+mod lang_tests_common;
+
+fn main() {
+    lang_tests_common::main_inner(lang_tests_common::Profile::Release);
+}

diff --git a/compiler/rustc_codegen_gcc/tests/lib.rs b/compiler/rustc_codegen_gcc/tests/lib.rs
deleted file mode 100644 (file)
index 8ee35b3..0000000
--- a/compiler/rustc_codegen_gcc/tests/lib.rs
+++ /dev/null
@@ -1,50 +0,0 @@
-use std::{
-    env::{self, current_dir},
-    path::PathBuf,
-    process::Command,
-};
-
-use lang_tester::LangTester;
-use tempfile::TempDir;
-
-fn main() {
-    let tempdir = TempDir::new().expect("temp dir");
-    let current_dir = current_dir().expect("current dir");
-    let current_dir = current_dir.to_str().expect("current dir").to_string();
-    let gcc_path = include_str!("../gcc_path");
-    let gcc_path = gcc_path.trim();
-    env::set_var("LD_LIBRARY_PATH", gcc_path);
-    LangTester::new()
-        .test_dir("tests/run")
-        .test_file_filter(|path| path.extension().expect("extension").to_str().expect("to_str") == "rs")
-        .test_extract(|source| {
-            let lines =
-                source.lines()
-                    .skip_while(|l| !l.starts_with("//"))
-                    .take_while(|l| l.starts_with("//"))
-                    .map(|l| &l[2..])
-                    .collect::<Vec<_>>()
-                    .join("\n");
-            Some(lines)
-        })
-        .test_cmds(move |path| {
-            // Test command 1: Compile `x.rs` into `tempdir/x`.
-            let mut exe = PathBuf::new();
-            exe.push(&tempdir);
-            exe.push(path.file_stem().expect("file_stem"));
-            let mut compiler = Command::new("rustc");
-            compiler.args(&[
-                &format!("-Zcodegen-backend={}/target/debug/librustc_codegen_gcc.so", current_dir),
-                "--sysroot", &format!("{}/build_sysroot/sysroot/", current_dir),
-                "-Zno-parallel-llvm",
-                "-C", "panic=abort",
-                "-C", "link-arg=-lc",
-                "-o", exe.to_str().expect("to_str"),
-                path.to_str().expect("to_str"),
-            ]);
-            // Test command 2: run `tempdir/x`.
-            let runtime = Command::new(exe);
-            vec![("Compiler", compiler), ("Run-time", runtime)]
-        })
-        .run();
-}

diff --git a/compiler/rustc_codegen_gcc/tests/run/int.rs b/compiler/rustc_codegen_gcc/tests/run/int.rs
index 49376012c40e79e34ca715aabbb6c1e90c271d52..2b90e4ae8d82b9079b571be7d305d8d6f3f9967c 100644 (file)
--- a/compiler/rustc_codegen_gcc/tests/run/int.rs
+++ b/compiler/rustc_codegen_gcc/tests/run/int.rs
@@ -3,151 +3,338 @@
 // Run-time:
 //   status: 0
 
-#![feature(arbitrary_self_types, auto_traits, core_intrinsics, lang_items, start, intrinsics)]
+#![feature(bench_black_box, const_black_box, core_intrinsics, start)]
 
 #![no_std]
 
-mod intrinsics {
-    extern "rust-intrinsic" {
-        pub fn abort() -> !;
-    }
+#[panic_handler]
+fn panic_handler(_: &core::panic::PanicInfo) -> ! {
+    core::intrinsics::abort();
 }
 
 /*
- * Core
+ * Code
  */
 
-mod libc {
-    #[link(name = "c")]
-    extern "C" {
-        pub fn puts(s: *const u8) -> i32;
+#[start]
+fn main(_argc: isize, _argv: *const *const u8) -> isize {
+    use core::hint::black_box;
+
+    macro_rules! check {
+        ($ty:ty, $expr:expr) => {
+            {
+                const EXPECTED: $ty = $expr;
+                assert_eq!($expr, EXPECTED);
+            }
+        };
     }
-}
 
-#[panic_handler]
-fn panic_handler(_: &core::panic::PanicInfo) -> ! {
-    unsafe {
-        core::intrinsics::abort();
+    check!(u32, (2220326408_u32 + black_box(1)) >> (32 - 6));
+
+    /// Generate `check!` tests for integer types at least as wide as 128 bits.
+    macro_rules! check_ops128 {
+        () => {
+            check_ops64!();
+
+            // Shifts.
+            check!(T, VAL1 << black_box(64));
+            check!(T, VAL1 << black_box(81));
+            check!(T, VAL3 << black_box(63));
+            check!(T, VAL3 << black_box(64));
+
+            check!(T, VAL1 >> black_box(64));
+            check!(T, VAL2 >> black_box(64));
+            check!(T, VAL3 >> black_box(64));
+            check!(T, VAL3 >> black_box(81));
+        };
     }
-}
 
-/*
- * Code
- */
+    /// Generate `check!` tests for integer types at least as wide as 64 bits.
+    macro_rules! check_ops64 {
+        () => {
+            check_ops32!();
+
+            // Shifts.
+            check!(T, VAL2 << black_box(33));
+            check!(T, VAL2 << black_box(49));
+            check!(T, VAL2 << black_box(61));
+            check!(T, VAL2 << black_box(63));
+
+            check!(T, VAL3 << black_box(33));
+            check!(T, VAL3 << black_box(49));
+            check!(T, VAL3 << black_box(61));
+
+            check!(T, VAL1 >> black_box(33));
+            check!(T, VAL1 >> black_box(49));
+            check!(T, VAL1 >> black_box(61));
+            check!(T, VAL1 >> black_box(63));
+
+            check!(T, VAL2 >> black_box(33));
+            check!(T, VAL2 >> black_box(49));
+            check!(T, VAL2 >> black_box(61));
+            check!(T, VAL2 >> black_box(63));
+
+            check!(T, VAL3 >> black_box(33));
+            check!(T, VAL3 >> black_box(49));
+            check!(T, VAL3 >> black_box(61));
+            check!(T, VAL3 >> black_box(63));
+        };
+    }
 
-#[start]
-fn main(argc: isize, _argv: *const *const u8) -> isize {
-    let var = 134217856_u128;
-    let var2 = 10475372733397991552_u128;
-    let var3 = 193236519889708027473620326106273939584_u128;
-    let var4 = 123236519889708027473620326106273939584_u128;
-    let var5 = 153236519889708027473620326106273939584_u128;
-    let var6 = 18446744073709551616_i128;
-    let var7 = 170141183460469231731687303715884105728_u128;
-
-    // Shifts.
-    assert_eq!(var << (argc as u128 - 1), var);
-    assert_eq!(var << argc as u128, 268435712);
-    assert_eq!(var << (argc + 32) as u128, 1152922604118474752);
-    assert_eq!(var << (argc + 48) as u128, 75557935783508361347072);
-    assert_eq!(var << (argc + 60) as u128, 309485304969250248077606912);
-    assert_eq!(var << (argc + 62) as u128, 1237941219877000992310427648);
-    assert_eq!(var << (argc + 63) as u128, 2475882439754001984620855296);
-    assert_eq!(var << (argc + 80) as u128, 324518863143436548128224745357312);
-
-    assert_eq!(var2 << argc as u128, 20950745466795983104);
-    assert_eq!(var2 << (argc as u128 - 1), var2);
-    assert_eq!(var2 << (argc + 32) as u128, 89982766606709001335848566784);
-    assert_eq!(var2 << (argc + 48) as u128, 5897110592337281111546171672756224);
-    assert_eq!(var2 << (argc + 60) as u128, 24154564986213503432893119171609493504);
-    assert_eq!(var2 << (argc + 62) as u128, 96618259944854013731572476686437974016);
-    assert_eq!(var2 << (argc + 63) as u128, 193236519889708027463144953372875948032);
-
-    assert_eq!(var3 << argc as u128, 46190672858477591483866044780779667712);
-    assert_eq!(var3 << (argc as u128 - 1), var3);
-    assert_eq!(var3 << (argc + 32) as u128, 21267668304951024224840338247585366016);
-    assert_eq!(var3 << (argc + 48) as u128, 1335125106377253154015353231953100800);
-    assert_eq!(var3 << (argc + 60) as u128, 24154564986213503432893119171609493504);
-    assert_eq!(var3 << (argc + 62) as u128, 96618259944854013731572476686437974016);
-    assert_eq!(var3 << (argc + 63) as u128, 193236519889708027463144953372875948032);
-
-    assert_eq!((2220326408_u32 + argc as u32) >> (32 - 6), 33);
-
-    assert_eq!(var >> (argc as u128 - 1), var);
-    assert_eq!(var >> argc as u128, 67108928);
-    assert_eq!(var >> (argc + 32) as u128, 0);
-    assert_eq!(var >> (argc + 48) as u128, 0);
-    assert_eq!(var >> (argc + 60) as u128, 0);
-    assert_eq!(var >> (argc + 62) as u128, 0);
-    assert_eq!(var >> (argc + 63) as u128, 0);
-
-    assert_eq!(var2 >> argc as u128, 5237686366698995776);
-    assert_eq!(var2 >> (argc as u128 - 1), var2);
-    assert_eq!(var2 >> (argc + 32) as u128, 1219493888);
-    assert_eq!(var2 >> (argc + 48) as u128, 18608);
-    assert_eq!(var2 >> (argc + 60) as u128, 4);
-    assert_eq!(var2 >> (argc + 62) as u128, 1);
-    assert_eq!(var2 >> (argc + 63) as u128, 0);
-
-    assert_eq!(var3 >> (argc as u128 - 1), var3);
-    assert_eq!(var3 >> argc as u128, 96618259944854013736810163053136969792);
-    assert_eq!(var3 >> (argc + 32) as u128, 22495691651677250335181635584);
-    assert_eq!(var3 >> (argc + 48) as u128, 343257013727985387194544);
-    assert_eq!(var3 >> (argc + 60) as u128, 83802981867183932420);
-    assert_eq!(var3 >> (argc + 62) as u128, 20950745466795983105);
-    assert_eq!(var3 >> (argc + 63) as u128, 10475372733397991552);
-    assert_eq!(var3 >> (argc + 80) as u128, 79920751444992);
-
-    assert_eq!(var6 >> argc as u128, 9223372036854775808);
-    assert_eq!((var6 - 1) >> argc as u128, 9223372036854775807);
-    assert_eq!(var7 >> argc as u128, 85070591730234615865843651857942052864);
-
-    // Casts
-    assert_eq!((var >> (argc + 32) as u128) as u64, 0);
-    assert_eq!((var >> argc as u128) as u64, 67108928);
-
-    // Addition.
-    assert_eq!(var + argc as u128, 134217857);
-
-    assert_eq!(var2 + argc as u128, 10475372733397991553);
-    assert_eq!(var2 + (var2 + argc as u128) as u128, 20950745466795983105);
-
-    assert_eq!(var3 + argc as u128, 193236519889708027473620326106273939585);
-
-    // Subtraction
-    assert_eq!(var - argc as u128, 134217855);
-
-    assert_eq!(var2 - argc as u128, 10475372733397991551);
-
-    assert_eq!(var3 - argc as u128, 193236519889708027473620326106273939583);
-
-    // Multiplication
-    assert_eq!(var * (argc + 1) as u128, 268435712);
-    assert_eq!(var * (argc as u128 + var2), 1405982069077538020949770368);
-
-    assert_eq!(var2 * (argc + 1) as u128, 20950745466795983104);
-    assert_eq!(var2 * (argc as u128 + var2), 109733433903618109003204073240861360256);
-
-    assert_eq!(var3 * argc as u128, 193236519889708027473620326106273939584);
-
-    assert_eq!(var4 * (argc + 1) as u128, 246473039779416054947240652212547879168);
-
-    assert_eq!(var5 * (argc + 1) as u128, 306473039779416054947240652212547879168);
-
-    // Division.
-    assert_eq!(var / (argc + 1) as u128, 67108928);
-    assert_eq!(var / (argc + 2) as u128, 44739285);
-
-    assert_eq!(var2 / (argc + 1) as u128, 5237686366698995776);
-    assert_eq!(var2 / (argc + 2) as u128, 3491790911132663850);
-
-    assert_eq!(var3 / (argc + 1) as u128, 96618259944854013736810163053136969792);
-    assert_eq!(var3 / (argc + 2) as u128, 64412173296569342491206775368757979861);
-    assert_eq!(var3 / (argc as u128 + var4), 1);
-    assert_eq!(var3 / (argc as u128 + var2), 18446744073709551615);
-
-    assert_eq!(var4 / (argc + 1) as u128, 61618259944854013736810163053136969792);
-    assert_eq!(var4 / (argc + 2) as u128, 41078839963236009157873442035424646528);
+    /// Generate `check!` tests for integer types at least as wide as 32 bits.
+    macro_rules! check_ops32 {
+        () => {
+            // Shifts.
+            check!(T, VAL2 << black_box(1));
+            check!(T, VAL2 << black_box(0));
+
+            check!(T, VAL3 << black_box(1));
+            check!(T, VAL3 << black_box(0));
+
+            check!(T, VAL1.wrapping_shl(black_box(0)));
+            check!(T, VAL1.wrapping_shl(black_box(1)));
+            check!(T, VAL1.wrapping_shl(black_box(33)));
+            check!(T, VAL1.wrapping_shl(black_box(49)));
+            check!(T, VAL1.wrapping_shl(black_box(61)));
+            check!(T, VAL1.wrapping_shl(black_box(63)));
+            check!(T, VAL1.wrapping_shl(black_box(64)));
+            check!(T, VAL1.wrapping_shl(black_box(81)));
+
+            check!(Option<T>, VAL1.checked_shl(black_box(0)));
+            check!(Option<T>, VAL1.checked_shl(black_box(1)));
+            check!(Option<T>, VAL1.checked_shl(black_box(33)));
+            check!(Option<T>, VAL1.checked_shl(black_box(49)));
+            check!(Option<T>, VAL1.checked_shl(black_box(61)));
+            check!(Option<T>, VAL1.checked_shl(black_box(63)));
+            check!(Option<T>, VAL1.checked_shl(black_box(64)));
+            check!(Option<T>, VAL1.checked_shl(black_box(81)));
+
+            check!(T, VAL1 >> black_box(0));
+            check!(T, VAL1 >> black_box(1));
+
+            check!(T, VAL2 >> black_box(1));
+            check!(T, VAL2 >> black_box(0));
+
+            check!(T, VAL3 >> black_box(0));
+            check!(T, VAL3 >> black_box(1));
+
+            check!(T, VAL1.wrapping_shr(black_box(0)));
+            check!(T, VAL1.wrapping_shr(black_box(1)));
+            check!(T, VAL1.wrapping_shr(black_box(33)));
+            check!(T, VAL1.wrapping_shr(black_box(49)));
+            check!(T, VAL1.wrapping_shr(black_box(61)));
+            check!(T, VAL1.wrapping_shr(black_box(63)));
+            check!(T, VAL1.wrapping_shr(black_box(64)));
+            check!(T, VAL1.wrapping_shr(black_box(81)));
+
+            check!(Option<T>, VAL1.checked_shr(black_box(0)));
+            check!(Option<T>, VAL1.checked_shr(black_box(1)));
+            check!(Option<T>, VAL1.checked_shr(black_box(33)));
+            check!(Option<T>, VAL1.checked_shr(black_box(49)));
+            check!(Option<T>, VAL1.checked_shr(black_box(61)));
+            check!(Option<T>, VAL1.checked_shr(black_box(63)));
+            check!(Option<T>, VAL1.checked_shr(black_box(64)));
+            check!(Option<T>, VAL1.checked_shr(black_box(81)));
+
+            // Casts
+            check!(u64, (VAL1 >> black_box(1)) as u64);
+
+            // Addition.
+            check!(T, VAL1 + black_box(1));
+            check!(T, VAL2 + black_box(1));
+            check!(T, VAL2 + (VAL2 + black_box(1)));
+            check!(T, VAL3 + black_box(1));
+
+            check!(Option<T>, VAL1.checked_add(black_box(1)));
+            check!(Option<T>, VAL2.checked_add(black_box(1)));
+            check!(Option<T>, VAL2.checked_add(VAL2 + black_box(1)));
+            check!(Option<T>, VAL3.checked_add(T::MAX));
+            check!(Option<T>, VAL3.checked_add(T::MIN));
+
+            check!(T, VAL1.wrapping_add(black_box(1)));
+            check!(T, VAL2.wrapping_add(black_box(1)));
+            check!(T, VAL2.wrapping_add(VAL2 + black_box(1)));
+            check!(T, VAL3.wrapping_add(T::MAX));
+            check!(T, VAL3.wrapping_add(T::MIN));
+
+            check!((T, bool), VAL1.overflowing_add(black_box(1)));
+            check!((T, bool), VAL2.overflowing_add(black_box(1)));
+            check!((T, bool), VAL2.overflowing_add(VAL2 + black_box(1)));
+            check!((T, bool), VAL3.overflowing_add(T::MAX));
+            check!((T, bool), VAL3.overflowing_add(T::MIN));
+
+            check!(T, VAL1.saturating_add(black_box(1)));
+            check!(T, VAL2.saturating_add(black_box(1)));
+            check!(T, VAL2.saturating_add(VAL2 + black_box(1)));
+            check!(T, VAL3.saturating_add(T::MAX));
+            check!(T, VAL3.saturating_add(T::MIN));
+
+            // Subtraction
+            check!(T, VAL1 - black_box(1));
+            check!(T, VAL2 - black_box(1));
+            check!(T, VAL3 - black_box(1));
+
+            check!(Option<T>, VAL1.checked_sub(black_box(1)));
+            check!(Option<T>, VAL2.checked_sub(black_box(1)));
+            check!(Option<T>, VAL2.checked_sub(VAL2 + black_box(1)));
+            check!(Option<T>, VAL3.checked_sub(T::MAX));
+            check!(Option<T>, VAL3.checked_sub(T::MIN));
+
+            check!(T, VAL1.wrapping_sub(black_box(1)));
+            check!(T, VAL2.wrapping_sub(black_box(1)));
+            check!(T, VAL2.wrapping_sub(VAL2 + black_box(1)));
+            check!(T, VAL3.wrapping_sub(T::MAX));
+            check!(T, VAL3.wrapping_sub(T::MIN));
+
+            check!((T, bool), VAL1.overflowing_sub(black_box(1)));
+            check!((T, bool), VAL2.overflowing_sub(black_box(1)));
+            check!((T, bool), VAL2.overflowing_sub(VAL2 + black_box(1)));
+            check!((T, bool), VAL3.overflowing_sub(T::MAX));
+            check!((T, bool), VAL3.overflowing_sub(T::MIN));
+
+            check!(T, VAL1.saturating_sub(black_box(1)));
+            check!(T, VAL2.saturating_sub(black_box(1)));
+            check!(T, VAL2.saturating_sub(VAL2 + black_box(1)));
+            check!(T, VAL3.saturating_sub(T::MAX));
+            check!(T, VAL3.saturating_sub(T::MIN));
+
+            // Multiplication
+            check!(T, VAL1 * black_box(2));
+            check!(T, VAL1 * (black_box(1) + VAL2));
+            check!(T, VAL2 * black_box(2));
+            check!(T, VAL2 * (black_box(1) + VAL2));
+            check!(T, VAL3 * black_box(1));
+            check!(T, VAL4 * black_box(2));
+            check!(T, VAL5 * black_box(2));
+
+            check!(Option<T>, VAL1.checked_mul(black_box(2)));
+            check!(Option<T>, VAL1.checked_mul(black_box(1) + VAL2));
+            check!(Option<T>, VAL3.checked_mul(VAL3));
+            check!(Option<T>, VAL4.checked_mul(black_box(2)));
+            check!(Option<T>, VAL5.checked_mul(black_box(2)));
+
+            check!(T, VAL1.wrapping_mul(black_box(2)));
+            check!(T, VAL1.wrapping_mul((black_box(1) + VAL2)));
+            check!(T, VAL3.wrapping_mul(VAL3));
+            check!(T, VAL4.wrapping_mul(black_box(2)));
+            check!(T, VAL5.wrapping_mul(black_box(2)));
+
+            check!((T, bool), VAL1.overflowing_mul(black_box(2)));
+            check!((T, bool), VAL1.overflowing_mul(black_box(1) + VAL2));
+            check!((T, bool), VAL3.overflowing_mul(VAL3));
+            check!((T, bool), VAL4.overflowing_mul(black_box(2)));
+            check!((T, bool), VAL5.overflowing_mul(black_box(2)));
+
+            check!(T, VAL1.saturating_mul(black_box(2)));
+            check!(T, VAL1.saturating_mul(black_box(1) + VAL2));
+            check!(T, VAL3.saturating_mul(VAL3));
+            check!(T, VAL4.saturating_mul(black_box(2)));
+            check!(T, VAL5.saturating_mul(black_box(2)));
+
+            // Division.
+            check!(T, VAL1 / black_box(2));
+            check!(T, VAL1 / black_box(3));
+
+            check!(T, VAL2 / black_box(2));
+            check!(T, VAL2 / black_box(3));
+
+            check!(T, VAL3 / black_box(2));
+            check!(T, VAL3 / black_box(3));
+            check!(T, VAL3 / (black_box(1) + VAL4));
+            check!(T, VAL3 / (black_box(1) + VAL2));
+
+            check!(T, VAL4 / black_box(2));
+            check!(T, VAL4 / black_box(3));
+
+            check!(Option<T>, VAL1.checked_div(black_box(2)));
+            check!(Option<T>, VAL1.checked_div(black_box(1) + VAL2));
+            check!(Option<T>, VAL3.checked_div(VAL3));
+            check!(Option<T>, VAL4.checked_div(black_box(2)));
+            check!(Option<T>, VAL5.checked_div(black_box(2)));
+            check!(Option<T>, (T::MIN).checked_div(black_box(0 as T).wrapping_sub(1)));
+            check!(Option<T>, VAL5.checked_div(black_box(0))); // var5 / 0
+
+            check!(T, VAL1.wrapping_div(black_box(2)));
+            check!(T, VAL1.wrapping_div(black_box(1) + VAL2));
+            check!(T, VAL3.wrapping_div(VAL3));
+            check!(T, VAL4.wrapping_div(black_box(2)));
+            check!(T, VAL5.wrapping_div(black_box(2)));
+            check!(T, (T::MIN).wrapping_div(black_box(0 as T).wrapping_sub(1)));
+
+            check!((T, bool), VAL1.overflowing_div(black_box(2)));
+            check!((T, bool), VAL1.overflowing_div(black_box(1) + VAL2));
+            check!((T, bool), VAL3.overflowing_div(VAL3));
+            check!((T, bool), VAL4.overflowing_div(black_box(2)));
+            check!((T, bool), VAL5.overflowing_div(black_box(2)));
+            check!((T, bool), (T::MIN).overflowing_div(black_box(0 as T).wrapping_sub(1)));
+
+            check!(T, VAL1.saturating_div(black_box(2)));
+            check!(T, VAL1.saturating_div((black_box(1) + VAL2)));
+            check!(T, VAL3.saturating_div(VAL3));
+            check!(T, VAL4.saturating_div(black_box(2)));
+            check!(T, VAL5.saturating_div(black_box(2)));
+            check!(T, (T::MIN).saturating_div((0 as T).wrapping_sub(black_box(1))));
+        };
+    }
+
+    {
+        type T = u32;
+        const VAL1: T = 14162_u32;
+        const VAL2: T = 14556_u32;
+        const VAL3: T = 323656954_u32;
+        const VAL4: T = 2023651954_u32;
+        const VAL5: T = 1323651954_u32;
+        check_ops32!();
+    }
+
+    {
+        type T = i32;
+        const VAL1: T = 13456_i32;
+        const VAL2: T = 10475_i32;
+        const VAL3: T = 923653954_i32;
+        const VAL4: T = 993198738_i32;
+        const VAL5: T = 1023653954_i32;
+        check_ops32!();
+    }
+
+    {
+        type T = u64;
+        const VAL1: T = 134217856_u64;
+        const VAL2: T = 104753732_u64;
+        const VAL3: T = 12323651988970863954_u64;
+        const VAL4: T = 7323651988970863954_u64;
+        const VAL5: T = 8323651988970863954_u64;
+        check_ops64!();
+    }
+
+    {
+        type T = i64;
+        const VAL1: T = 134217856_i64;
+        const VAL2: T = 104753732_i64;
+        const VAL3: T = 6323651988970863954_i64;
+        const VAL4: T = 2323651988970863954_i64;
+        const VAL5: T = 3323651988970863954_i64;
+        check_ops64!();
+    }
+
+    {
+        type T = u128;
+        const VAL1: T = 134217856_u128;
+        const VAL2: T = 10475372733397991552_u128;
+        const VAL3: T = 193236519889708027473620326106273939584_u128;
+        const VAL4: T = 123236519889708027473620326106273939584_u128;
+        const VAL5: T = 153236519889708027473620326106273939584_u128;
+        check_ops128!();
+    }
+    {
+        type T = i128;
+        const VAL1: T = 134217856_i128;
+        const VAL2: T = 10475372733397991552_i128;
+        const VAL3: T = 83236519889708027473620326106273939584_i128;
+        const VAL4: T = 63236519889708027473620326106273939584_i128;
+        const VAL5: T = 73236519889708027473620326106273939584_i128;
+        check_ops128!();
+    }
 
     0
 }

diff --git a/compiler/rustc_codegen_gcc/tests/run/int_overflow.rs b/compiler/rustc_codegen_gcc/tests/run/int_overflow.rs
index 6477b83982804646fbb7bc9c597e9dcd8a09a3d4..ea2c5add962ae3d871cc0a1a298d9e7b8f54da98 100644 (file)
--- a/compiler/rustc_codegen_gcc/tests/run/int_overflow.rs
+++ b/compiler/rustc_codegen_gcc/tests/run/int_overflow.rs
@@ -1,7 +1,7 @@
 // Compiler:
 //
 // Run-time:
-//   stdout: Panicking
+//   stdout: Success
 //   status: signal
 
 #![allow(unused_attributes)]
@@ -64,7 +64,9 @@ mod intrinsics {
 #[no_mangle]
 pub fn panic(_msg: &str) -> ! {
     unsafe {
-        libc::puts("Panicking\0" as *const str as *const u8);
+        // Panicking is expected iff overflow checking is enabled.
+        #[cfg(debug_assertions)]
+        libc::puts("Success\0" as *const str as *const u8);
         libc::fflush(libc::stdout);
         intrinsics::abort();
     }
@@ -124,6 +126,15 @@ fn add(self, rhs: Self) -> Self {
 #[start]
 fn main(mut argc: isize, _argv: *const *const u8) -> isize {
     let int = 9223372036854775807isize;
-    let int = int + argc;
+    let int = int + argc;  // overflow
+
+    // If overflow checking is disabled, we should reach here.
+    #[cfg(not(debug_assertions))]
+    unsafe {
+        libc::puts("Success\0" as *const str as *const u8);
+        libc::fflush(libc::stdout);
+        intrinsics::abort();
+    }
+
     int
 }

diff --git a/compiler/rustc_codegen_gcc/tools/generate_intrinsics.py b/compiler/rustc_codegen_gcc/tools/generate_intrinsics.py
new file mode 100644 (file)
index 0000000..849c6e9
--- /dev/null
+++ b/compiler/rustc_codegen_gcc/tools/generate_intrinsics.py
@@ -0,0 +1,238 @@
+import json
+import os
+import re
+import sys
+import subprocess
+from os import walk
+
+
+def run_command(command, cwd=None):
+    p = subprocess.Popen(command, cwd=cwd)
+    if p.wait() != 0:
+        print("command `{}` failed...".format(" ".join(command)))
+        sys.exit(1)
+
+
+def clone_repository(repo_name, path, repo_url, sub_path=None):
+    if os.path.exists(path):
+        while True:
+            choice = input("There is already a `{}` folder, do you want to update it? [y/N]".format(path))
+            if choice == "" or choice.lower() == "n":
+                print("Skipping repository update.")
+                return
+            elif choice.lower() == "y":
+                print("Updating repository...")
+                run_command(["git", "pull", "origin"], cwd=path)
+                return
+            else:
+                print("Didn't understand answer...")
+    print("Cloning {} repository...".format(repo_name))
+    if sub_path is None:
+        run_command(["git", "clone", repo_url, "--depth", "1", path])
+    else:
+        run_command(["git", "clone", repo_url, "--filter=tree:0", "--no-checkout", path])
+        run_command(["git", "sparse-checkout", "init"], cwd=path)
+        run_command(["git", "sparse-checkout", "set", "add", sub_path], cwd=path)
+        run_command(["git", "checkout"], cwd=path)
+
+
+def append_intrinsic(array, intrinsic_name, translation):
+    array.append((intrinsic_name, translation))
+
+
+def extract_instrinsics(intrinsics, file):
+    print("Extracting intrinsics from `{}`...".format(file))
+    with open(file, "r", encoding="utf8") as f:
+        content = f.read()
+
+    lines = content.splitlines()
+    pos = 0
+    current_arch = None
+    while pos < len(lines):
+        line = lines[pos].strip()
+        if line.startswith("let TargetPrefix ="):
+            current_arch = line.split('"')[1].strip()
+            if len(current_arch) == 0:
+                current_arch = None
+        elif current_arch is None:
+            pass
+        elif line == "}":
+            current_arch = None
+        elif line.startswith("def "):
+            content = ""
+            while not content.endswith(";") and not content.endswith("}") and pos < len(lines):
+                line = lines[pos].split(" // ")[0].strip()
+                content += line
+                pos += 1
+            entries = re.findall('GCCBuiltin<"(\\w+)">', content)
+            if len(entries) > 0:
+                intrinsic = content.split("def ")[1].strip().split(":")[0].strip()
+                intrinsic = intrinsic.split("_")
+                if len(intrinsic) < 2 or intrinsic[0] != "int":
+                    continue
+                intrinsic[0] = "llvm"
+                intrinsic = ".".join(intrinsic)
+                if current_arch not in intrinsics:
+                    intrinsics[current_arch] = []
+                for entry in entries:
+                    append_intrinsic(intrinsics[current_arch], intrinsic, entry)
+            continue
+        pos += 1
+        continue
+    print("Done!")
+
+
+def extract_instrinsics_from_llvm(llvm_path, intrinsics):
+    files = []
+    intrinsics_path = os.path.join(llvm_path, "llvm/include/llvm/IR")
+    for (dirpath, dirnames, filenames) in walk(intrinsics_path):
+        files.extend([os.path.join(intrinsics_path, f) for f in filenames if f.endswith(".td")])
+
+    for file in files:
+        extract_instrinsics(intrinsics, file)
+
+
+def append_translation(json_data, p, array):
+    it = json_data["index"][p]
+    content = it["docs"].split('`')
+    if len(content) != 5:
+        return
+    append_intrinsic(array, content[1], content[3])
+
+
+def extract_instrinsics_from_llvmint(llvmint, intrinsics):
+    archs = [
+        "AMDGPU",
+        "aarch64",
+        "arm",
+        "cuda",
+        "hexagon",
+        "mips",
+        "nvvm",
+        "ppc",
+        "ptx",
+        "x86",
+        "xcore",
+    ]
+
+    json_file = os.path.join(llvmint, "target/doc/llvmint.json")
+    # We need to regenerate the documentation!
+    run_command(
+        ["cargo", "rustdoc", "--", "-Zunstable-options", "--output-format", "json"],
+        cwd=llvmint,
+    )
+    with open(json_file, "r", encoding="utf8") as f:
+        json_data = json.loads(f.read())
+    for p in json_data["paths"]:
+        it = json_data["paths"][p]
+        if it["crate_id"] != 0:
+            # This is from an external crate.
+            continue
+        if it["kind"] != "function":
+            # We're only looking for functions.
+            continue
+        # if len(it["path"]) == 2:
+        #   # This is a "general" intrinsic, not bound to a specific arch.
+        #   append_translation(json_data, p, general)
+        #   continue
+        if len(it["path"]) != 3 or it["path"][1] not in archs:
+            continue
+        arch = it["path"][1]
+        if arch not in intrinsics:
+            intrinsics[arch] = []
+        append_translation(json_data, p, intrinsics[arch])
+
+
+def fill_intrinsics(intrinsics, from_intrinsics, all_intrinsics):
+    for arch in from_intrinsics:
+        if arch not in intrinsics:
+            intrinsics[arch] = []
+        for entry in from_intrinsics[arch]:
+            if entry[0] in all_intrinsics:
+                if all_intrinsics[entry[0]] == entry[1]:
+                    # This is a "full" duplicate, both the LLVM instruction and the GCC
+                    # translation are the same.
+                    continue
+                intrinsics[arch].append((entry[0], entry[1], True))
+            else:
+                intrinsics[arch].append((entry[0], entry[1], False))
+                all_intrinsics[entry[0]] = entry[1]
+
+
+def update_intrinsics(llvm_path, llvmint, llvmint2):
+    intrinsics_llvm = {}
+    intrinsics_llvmint = {}
+    all_intrinsics = {}
+
+    extract_instrinsics_from_llvm(llvm_path, intrinsics_llvm)
+    extract_instrinsics_from_llvmint(llvmint, intrinsics_llvmint)
+    extract_instrinsics_from_llvmint(llvmint2, intrinsics_llvmint)
+
+    intrinsics = {}
+    # We give priority to translations from LLVM over the ones from llvmint.
+    fill_intrinsics(intrinsics, intrinsics_llvm, all_intrinsics)
+    fill_intrinsics(intrinsics, intrinsics_llvmint, all_intrinsics)
+
+    archs = [arch for arch in intrinsics]
+    archs.sort()
+
+    output_file = os.path.join(
+        os.path.dirname(os.path.abspath(__file__)),
+        "../src/intrinsic/archs.rs",
+    )
+    print("Updating content of `{}`...".format(output_file))
+    with open(output_file, "w", encoding="utf8") as out:
+        out.write("// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py`\n")
+        out.write("// DO NOT EDIT IT!\n")
+        out.write("match name {\n")
+        for arch in archs:
+            if len(intrinsics[arch]) == 0:
+                continue
+            intrinsics[arch].sort(key=lambda x: (x[0], x[2]))
+            out.write('    // {}\n'.format(arch))
+            for entry in intrinsics[arch]:
+                if entry[2] == True: # if it is a duplicate
+                    out.write('    // [DUPLICATE]: "{}" => "{}",\n'.format(entry[0], entry[1]))
+                else:
+                    out.write('    "{}" => "{}",\n'.format(entry[0], entry[1]))
+        out.write('    _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n')
+        out.write("}\n")
+    print("Done!")
+
+
+def main():
+    llvm_path = os.path.join(
+        os.path.dirname(os.path.abspath(__file__)),
+        "llvm-project",
+    )
+    llvmint_path = os.path.join(
+        os.path.dirname(os.path.abspath(__file__)),
+        "llvmint",
+    )
+    llvmint2_path = os.path.join(
+        os.path.dirname(os.path.abspath(__file__)),
+        "llvmint-2",
+    )
+
+    # First, we clone the LLVM repository if it's not already here.
+    clone_repository(
+        "llvm-project",
+        llvm_path,
+        "https://github.com/llvm/llvm-project",
+        sub_path="llvm/include/llvm/IR",
+    )
+    clone_repository(
+        "llvmint",
+        llvmint_path,
+        "https://github.com/GuillaumeGomez/llvmint",
+    )
+    clone_repository(
+        "llvmint2",
+        llvmint2_path,
+        "https://github.com/antoyo/llvmint",
+    )
+    update_intrinsics(llvm_path, llvmint_path, llvmint2_path)
+
+
+if __name__ == "__main__":
+    sys.exit(main())