]> git.lizzy.rs Git - plan9front.git/commitdiff
igfx: fix cdclk and dpll settings for dual channel lvds on sandybridge
authorqwx <devnull@localhost>
Tue, 22 Aug 2017 21:25:39 +0000 (00:25 +0300)
committerqwx <devnull@localhost>
Tue, 22 Aug 2017 21:25:39 +0000 (00:25 +0300)
sys/src/cmd/aux/vga/igfx.c

index 40d9c2107544290ea44ebf1722a1762f6c9f59fb..cc595c1320402538fe4c9f833abfe556566f6740 100644 (file)
@@ -456,7 +456,7 @@ snarf(Vga* vga, Ctlr* ctlr)
 
        case TypeSNB:
                igfx->npipe = 2;        /* A,B */
-               igfx->cdclk = 300;      /* MHz */
+               igfx->cdclk = 400;      /* MHz */
                goto IVBcommon;
 
        case TypeIVB:
@@ -843,6 +843,10 @@ initdpll(Igfx *igfx, int x, int freq, int port)
        dpll->ctrl.v &= ~(3<<24);
        if(port == PortLCD){
                p2 = 14;
+               if(freq > 112*MHz){
+                       p2 >>= 1;
+                       dpll->ctrl.v |= (1<<24);
+               }
                if(genpll(freq, cref, p2, &m1, &m2, &n, &p1) < 0)
                        return -1;
        } else {