Autogenerate most ARM platform intrinsics.

diff --git a/src/etc/platform-intrinsics/arm.json b/src/etc/platform-intrinsics/arm.json
new file mode 100644 (file)
index 0000000..0a48a50
--- /dev/null
+++ b/src/etc/platform-intrinsics/arm.json
@@ -0,0 +1,396 @@
+{
+    "platform": "arm",
+    "intrinsic_prefix": "arm_v",
+    "llvm_prefix": "llvm.neon.v",
+    "number_info": {
+        "signed": {
+            "kind": "s",
+            "data_type": { "pattern": "s{bitwidth}" }
+        },
+        "unsigned": {
+            "kind": "u",
+            "data_type": { "pattern": "u{bitwidth}" }
+        },
+        "float": {
+            "kind": "f",
+            "data_type": { "pattern": "f{bitwidth}" }
+        }
+    },
+    "widths": {
+        "64": "",
+        "128": "q"
+    },
+    "intrinsics": [
+        {
+            "intrinsic": "hadd{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "hadd{0.kind}.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "rhadd{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "rhadd{0.kind}.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "qadd{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "qadd{0.kind}.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "raddhn_{1.data_type}",
+            "width": [64],
+            "llvm": "raddhn.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0w", "0w"]
+        },
+        {
+            "intrinsic": "fma{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "!llvm.fma.{0.llvm_name}",
+            "ret": "f32",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "qdmulh{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "sqdmulh.{0.llvm_name}",
+            "ret": "s(16-32)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "qrdmulh{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "sqrdmulh.{0.llvm_name}",
+            "ret": "s(16-32)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "mull_{1.data_type}",
+            "width": [128],
+            "llvm": "mull{0.kind}.{0.llvm_name}",
+            "ret": "i(16-64)",
+            "args": ["0n", "0n"]
+        },
+        {
+            "intrinsic": "qdmull{0.width}_{1.data_type}",
+            "width": [128],
+            "llvm": "sqdmull.{0.llvm_name}",
+            "ret": "s(16-32)",
+            "args": ["0n", "0n"]
+        },
+        {
+            "intrinsic": "hsub{0.width}_{1.data_type}",
+            "width": [64, 128],
+            "llvm": "hsub{0.kind}.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "qsub{0.width}_{1.data_type}",
+            "width": [64, 128],
+            "llvm": "qsub{0.kind}.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "rsubhn_{1.data_type}",
+            "width": [64],
+            "llvm": "rsubhn.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0w", "0w"]
+        },
+        {
+            "intrinsic": "abd{0.width}_{1.data_type}",
+            "width": [64, 128],
+            "llvm": "abd{0.kind}.{0.llvm_name}",
+            "ret": ["i(8-32)","f32"],
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "max{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "max{0.kind}.{0.llvm_name}",
+            "ret": ["i(8-32)","f32"],
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "min{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "min{0.kind}.{0.llvm_name}",
+            "ret": ["i(8-32)","f32"],
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "shl{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "shl{0.kind}.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0", "0s"]
+        },
+        {
+            "intrinsic": "qshl{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "qshl{0.kind}.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0", "0s"]
+        },
+        {
+            "intrinsic": "rshl{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "rshl{0.kind}.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0", "0s"]
+        },
+        {
+            "intrinsic": "qrshl{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "qrshl{0.kind}.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0", "0s"]
+        },
+        {
+            "intrinsic": "qshrun_n_{1.data_type}",
+            "width": [64],
+            "llvm": "sqshrun.{0.llvm_name}",
+            "ret": "s(8-32)",
+            "args": ["0w", "U32"]
+        },
+        {
+            "intrinsic": "qrshrun_n_{1.data_type}",
+            "width": [64],
+            "llvm": "sqrshrun.{0.llvm_name}",
+            "ret": "s(8-32)",
+            "args": ["0w", "U32"]
+        },
+        {
+            "intrinsic": "qshrn_n_{1.data_type}",
+            "width": [64],
+            "llvm": "qshrn{0.kind}.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0w", "U32"]
+        },
+        {
+            "intrinsic": "rshrn_n_{1.data_type}",
+            "width": [64],
+            "llvm": "rshrn.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0w", "U32"]
+        },
+        {
+            "intrinsic": "qrshrn_n_{1.data_type}",
+            "width": [64],
+            "llvm": "qrshrn{0.kind}.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0w", "U32"]
+        },
+        {
+            "intrinsic": "sri{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "vsri.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "sli{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "vsli.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "vqmovn_{1.data_type}",
+            "width": [64],
+            "llvm": "qxtn{0.kind}.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0w"]
+        },
+        {
+            "intrinsic": "abs{0.width}_{0.data_type}",
+            "width": [64,128],
+            "llvm": "abs.{0.llvm_name}",
+            "ret": "s(8-32)",
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "abs{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "!llvm.fabs.{0.llvm_name}",
+            "ret": "f32",
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "qabs{0.width}_{0.data_type}",
+            "width": [64,128],
+            "llvm": "sqabs.{0.llvm_name}",
+            "ret": "s(8-32)",
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "qneg{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "sqneg.{0.llvm_name}",
+            "ret": "s(8-32)",
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "clz{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "!llvm.ctlz.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "cls{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "cls.{0.llvm_name}",
+            "ret": "i(8-32)",
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "cnt{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "!llvm.ctpop.{0.llvm_name}",
+            "ret": "i8",
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "recpe{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "recpe.{0.llvm_name}",
+            "ret": ["u32","f32"],
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "recps{0.width}_{0.data_type}",
+            "width": [64,128],
+            "llvm": "frecps.{0.llvm_name}",
+            "ret": "f32",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "sqrt{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "!llvm.sqrt.{0.llvm_name}",
+            "ret": "f32",
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "rsqrte{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "rsqrte.{0.llvm_name}",
+            "ret": ["u32","f32"],
+            "args": ["0"]
+        },
+        {
+            "intrinsic": "rsqrts{0.width}_{0.data_type}",
+            "width": [64,128],
+            "llvm": "rsqrts.{0.llvm_name}",
+            "ret": "f32",
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "bsl{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "bsl.{0.llvm_name}",
+            "ret": "i(8-64)",
+            "args": ["0u", "0"]
+        },
+        {
+            "intrinsic": "padd{0.width}_{0.data_type}",
+            "width": [64],
+            "llvm": "padd.{0.llvm_name}",
+            "ret": ["i(8-32)","f32"],
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "paddl{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "paddl{0.kind}.{0.llvm_name}.{1.llvm_name}",
+            "ret": "i(16-64)",
+            "args": ["0dn"]
+        },
+        {
+            "intrinsic": "padal{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "padal{0.kind}.{0.llvm_name}.{1.llvm_name}",
+            "ret": "i(16-64)",
+            "args": ["0", "0dn"]
+        },
+        {
+            "intrinsic": "pmax{0.width}_{0.data_type}",
+            "width": [64],
+            "llvm": "pmax{0.kind}.{0.llvm_name}",
+            "ret": ["i(8-32)","f32"],
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "pmin{0.width}_{0.data_type}",
+            "width": [64, 128],
+            "llvm": "pmin{0.kind}.{0.llvm_name}",
+            "ret": ["i(8-32)","f32"],
+            "args": ["0", "0"]
+        },
+        {
+            "intrinsic": "qtbl1_{0.data_type}",
+            "width": [64],
+            "llvm": "tbl1",
+            "ret": "i8",
+            "args": ["0x128", "0u"]
+        },
+        {
+            "intrinsic": "qtbx1_{0.data_type}",
+            "width": [64],
+            "llvm": "tbx1",
+            "ret": "i8",
+            "args": ["0", "0", "0u"]
+        },
+        {
+            "intrinsic": "qtbl2_{0.data_type}",
+            "width": [64],
+            "llvm": "tbl2",
+            "ret": "i8",
+            "args": ["(0,0)f", "0u"]
+        },
+        {
+            "intrinsic": "qtbx2_{0.data_type}",
+            "width": [64],
+            "llvm": "tbx2",
+            "ret": "i8",
+            "args": ["(0,0)f", "0u"]
+        },
+        {
+            "intrinsic": "qtbl3_{0.data_type}",
+            "width": [64],
+            "llvm": "tbl3",
+            "ret": "i8",
+            "args": ["(0,0,0)f", "0u"]
+        },
+        {
+            "intrinsic": "qtbx3_{0.data_type}",
+            "width": [64],
+            "llvm": "tbx3",
+            "ret": "i8",
+            "args": ["0", "(0,0,0)f", "0u"]
+        },
+        {
+            "intrinsic": "qtbl4_{0.data_type}",
+            "width": [64],
+            "llvm": "tbl4",
+            "ret": "i8",
+            "args": ["(0,0,0,0)f", "0u"]
+        },
+        {
+            "intrinsic": "qtbx4_{0.data_type}",
+            "width": [64],
+            "llvm": "tbx4",
+            "ret": "i8",
+            "args": ["0", "(0,0,0,0)f", "0u"]
+        }
+    ]
+}

diff --git a/src/librustc_platform_intrinsics/arm.rs b/src/librustc_platform_intrinsics/arm.rs
index b8a02773ec05ab0bf772510e525fa538b862cf9c..7398dcf79835e67537ad9eae9e71aabfe6da8f95 100644 (file)
--- a/src/librustc_platform_intrinsics/arm.rs
+++ b/src/librustc_platform_intrinsics/arm.rs
@@ -8,340 +8,2076 @@
 // option. This file may not be copied, modified, or distributed
 // except according to those terms.
 
-use {Intrinsic, i, f, v};
+// DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py
+// ignore-tidy-linelength
+
+use {Intrinsic, i, u, f, v, agg};
+use IntrinsicDef::Named;
 use rustc::middle::ty;
 
-macro_rules! p {
-    ($name: expr, ($($inputs: tt),*) -> $output: tt) => {
-        plain!(concat!("llvm.arm.neon.", $name), ($($inputs),*) -> $output)
-    }
-}
 pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option<Intrinsic> {
     if !name.starts_with("arm_v") { return None }
     Some(match &name["arm_v".len()..] {
-        "sqrtq_f32" => plain!("llvm.sqrt.v4f32", (f32x4) -> f32x4),
-        "sqrtq_f64" => plain!("llvm.sqrt.v2f64", (f64x2) -> f64x2),
-
-        "hadd_s8" => p!("vhadds.v8i8", (i8x8, i8x8) -> i8x8),
-        "haddq_s8" => p!("vhadds.v16i8", (i8x16, i8x16) -> i8x16),
-        "hadd_s16" => p!("vhadds.v4i16", (i16x4, i16x4) -> i16x4),
-        "haddq_s16" => p!("vhadds.v8i16", (i16x8, i16x8) -> i16x8),
-        "hadd_s32" => p!("vhadds.v2i32", (i32x2, i32x2) -> i32x2),
-        "haddq_s32" => p!("vhadds.v4i32", (i32x4, i32x4) -> i32x4),
-        "hadd_u8" => p!("vhaddu.v8i8", (i8x8, i8x8) -> i8x8),
-        "haddq_u8" => p!("vhaddu.v16i8", (i8x16, i8x16) -> i8x16),
-        "hadd_u16" => p!("vhaddu.v4i16", (i16x4, i16x4) -> i16x4),
-        "haddq_u16" => p!("vhaddu.v8i16", (i16x8, i16x8) -> i16x8),
-        "hadd_u32" => p!("vhaddu.v2i32", (i32x2, i32x2) -> i32x2),
-        "haddq_u32" => p!("vhaddu.v4i32", (i32x4, i32x4) -> i32x4),
-        "rhadd_s8" => p!("vrhadds.v8i8", (i8x8, i8x8) -> i8x8),
-        "rhaddq_s8" => p!("vrhadds.v16i8", (i8x16, i8x16) -> i8x16),
-        "rhadd_s16" => p!("vrhadds.v4i16", (i16x4, i16x4) -> i16x4),
-        "rhaddq_s16" => p!("vrhadds.v8i16", (i16x8, i16x8) -> i16x8),
-        "rhadd_s32" => p!("vrhadds.v2i32", (i32x2, i32x2) -> i32x2),
-        "rhaddq_s32" => p!("vrhadds.v4i32", (i32x4, i32x4) -> i32x4),
-        "rhadd_u8" => p!("vrhaddu.v8i8", (i8x8, i8x8) -> i8x8),
-        "rhaddq_u8" => p!("vrhaddu.v16i8", (i8x16, i8x16) -> i8x16),
-        "rhadd_u16" => p!("vrhaddu.v4i16", (i16x4, i16x4) -> i16x4),
-        "rhaddq_u16" => p!("vrhaddu.v8i16", (i16x8, i16x8) -> i16x8),
-        "rhadd_u32" => p!("vrhaddu.v2i32", (i32x2, i32x2) -> i32x2),
-        "rhaddq_u32" => p!("vrhaddu.v4i32", (i32x4, i32x4) -> i32x4),
-        "qadd_s8" => p!("vqadds.v8i8", (i8x8, i8x8) -> i8x8),
-        "qaddq_s8" => p!("vqadds.v16i8", (i8x16, i8x16) -> i8x16),
-        "qadd_s16" => p!("vqadds.v4i16", (i16x4, i16x4) -> i16x4),
-        "qaddq_s16" => p!("vqadds.v8i16", (i16x8, i16x8) -> i16x8),
-        "qadd_s32" => p!("vqadds.v2i32", (i32x2, i32x2) -> i32x2),
-        "qaddq_s32" => p!("vqadds.v4i32", (i32x4, i32x4) -> i32x4),
-        "qadd_s64" => p!("vqaddu.v1i64", (i64x1, i64x1) -> i64x1),
-        "qaddq_s64" => p!("vqaddu.v2i64", (i64x2, i64x2) -> i64x2),
-        "qadd_u8" => p!("vqaddu.v8i8", (i8x8, i8x8) -> i8x8),
-        "qaddq_u8" => p!("vqaddu.v16i8", (i8x16, i8x16) -> i8x16),
-        "qadd_u16" => p!("vqaddu.v4i16", (i16x4, i16x4) -> i16x4),
-        "qaddq_u16" => p!("vqaddu.v8i16", (i16x8, i16x8) -> i16x8),
-        "qadd_u32" => p!("vqaddu.v2i32", (i32x2, i32x2) -> i32x2),
-        "qaddq_u32" => p!("vqaddu.v4i32", (i32x4, i32x4) -> i32x4),
-        "qadd_u64" => p!("vqaddu.v1i64", (i64x1, i64x1) -> i64x1),
-        "qaddq_u64" => p!("vqaddu.v2i64", (i64x2, i64x2) -> i64x2),
-        "raddhn_s16" => p!("vraddhn.v8i8", (i16x8, i16x8) -> i8x8),
-        "raddhn_s32" => p!("vraddhn.v4i16", (i32x4, i32x4) -> i16x4),
-        "raddhn_s64" => p!("vraddhn.v2i32", (i64x2, i64x2) -> i32x2),
-        "fma_f32" => plain!("llvm.fma.v2f32", (f32x2, f32x2, f32x2) -> f32x2),
-        "fmaq_f32" => plain!("llvm.fma.v4f32", (f32x4, f32x4, f32x4) -> f32x4),
-        "qdmulh_s16" => p!("vqdmulh.v4i16", (i16x4, i16x4) -> i16x4),
-        "qdmulhq_s16" => p!("vqdmulh.v8i16", (i16x8, i16x8) -> i16x8),
-        "qdmulh_s32" => p!("vqdmulh.v2i32", (i32x2, i32x2) -> i32x4),
-        "qdmulhq_s32" => p!("vqdmulh.v4i32", (i32x4, i32x4) -> i32x4),
-        "qrdmulh_s16" => p!("vqrdmulh.v4i16", (i16x4, i16x4) -> i16x4),
-        "qrdmulhqr_s16" => p!("vqrdmulh.v8i16", (i16x8, i16x8) -> i16x8),
-        "qrdmulh_s32" => p!("vqrdmulh.v2i32", (i32x2, i32x2) -> i32x4),
-        "qrdmulhqr_s32" => p!("vqrdmulh.v4i32", (i32x4, i32x4) -> i32x4),
-        "mull_s8" => p!("vmulls.v8i16", (i8x8, i8x8) -> i16x8),
-        "mull_s16" => p!("vmulls.v4i32", (i16x4, i16x4) -> i32x4),
-        "mull_s32" => p!("vmulls.v2i64", (i32x2, i32x2) -> i64x2),
-        "mull_u8" => p!("vmullu.v8i16", (i8x8, i8x8) -> i16x8),
-        "mull_u16" => p!("vmullu.v4i32", (i16x4, i16x4) -> i32x4),
-        "mull_u32" => p!("vmullu.v2i64", (i32x2, i32x2) -> i64x2),
-        "qdmull_s16" => p!("vqdmull.v4i32", (i16x4, i16x4) -> i32x4),
-        "qdmull_s32" => p!("vqdmull.v2i64", (i32x2, i32x2) -> i64x2),
-        "hsub_s8" => p!("vhsubs.v8i8", (i8x8, i8x8) -> i8x8),
-        "hsubq_s8" => p!("vhsubs.v16i8", (i8x16, i8x16) -> i8x16),
-        "hsub_s16" => p!("vhsubs.v4i16", (i16x4, i16x4) -> i16x4),
-        "hsubq_s16" => p!("vhsubs.v8i16", (i16x8, i16x8) -> i16x8),
-        "hsub_s32" => p!("vhsubs.v2i32", (i32x2, i32x2) -> i32x2),
-        "hsubq_s32" => p!("vhsubs.v4i32", (i32x4, i32x4) -> i32x4),
-        "hsub_u8" => p!("vhsubu.v8i8", (i8x8, i8x8) -> i8x8),
-        "hsubq_u8" => p!("vhsubu.v16i8", (i8x16, i8x16) -> i8x16),
-        "hsub_u16" => p!("vhsubu.v4i16", (i16x4, i16x4) -> i16x4),
-        "hsubq_u16" => p!("vhsubu.v8i16", (i16x8, i16x8) -> i16x8),
-        "hsub_u32" => p!("vhsubu.v2i32", (i32x2, i32x2) -> i32x2),
-        "hsubq_u32" => p!("vhsubu.v4i32", (i32x4, i32x4) -> i32x4),
-        "qsub_s8" => p!("vqsubs.v8i8", (i8x8, i8x8) -> i8x8),
-        "qsubq_s8" => p!("vqsubs.v16i8", (i8x16, i8x16) -> i8x16),
-        "qsub_s16" => p!("vqsubs.v4i16", (i16x4, i16x4) -> i16x4),
-        "qsubq_s16" => p!("vqsubs.v8i16", (i16x8, i16x8) -> i16x8),
-        "qsub_s32" => p!("vqsubs.v2i32", (i32x2, i32x2) -> i32x2),
-        "qsubq_s32" => p!("vqsubs.v4i32", (i32x4, i32x4) -> i32x4),
-        "qsub_s64" => p!("vqsubu.v1i64", (i64x1, i64x1) -> i64x1),
-        "qsubq_s64" => p!("vqsubu.v2i64", (i64x2, i64x2) -> i64x2),
-        "qsub_u8" => p!("vqsubu.v8i8", (i8x8, i8x8) -> i8x8),
-        "qsubq_u8" => p!("vqsubu.v16i8", (i8x16, i8x16) -> i8x16),
-        "qsub_u16" => p!("vqsubu.v4i16", (i16x4, i16x4) -> i16x4),
-        "qsubq_u16" => p!("vqsubu.v8i16", (i16x8, i16x8) -> i16x8),
-        "qsub_u32" => p!("vqsubu.v2i32", (i32x2, i32x2) -> i32x2),
-        "qsubq_u32" => p!("vqsubu.v4i32", (i32x4, i32x4) -> i32x4),
-        "qsub_u64" => p!("vqsubu.v1i64", (i64x1, i64x1) -> i64x1),
-        "qsubq_u64" => p!("vqsubu.v2i64", (i64x2, i64x2) -> i64x2),
-        "abd_s8" => p!("vabds.v8i8", (i8x8, i8x8) -> i8x8),
-        "abdq_s8" => p!("vabds.v16i8", (i8x16, i8x16) -> i8x16),
-        "abd_s16" => p!("vabds.v4i16", (i16x4, i16x4) -> i16x4),
-        "abdq_s16" => p!("vabds.v8i16", (i16x8, i16x8) -> i16x8),
-        "abd_s32" => p!("vabds.v2i32", (i32x2, i32x2) -> i32x2),
-        "abdq_s32" => p!("vabds.v4i32", (i32x4, i32x4) -> i32x4),
-        "abd_u8" => p!("vabdu.v8i8", (i8x8, i8x8) -> i8x8),
-        "abdq_u8" => p!("vabdu.v16i8", (i8x16, i8x16) -> i8x16),
-        "abd_u16" => p!("vabdu.v4i16", (i16x4, i16x4) -> i16x4),
-        "abdq_u16" => p!("vabdu.v8i16", (i16x8, i16x8) -> i16x8),
-        "abd_u32" => p!("vabdu.v2i32", (i32x2, i32x2) -> i32x2),
-        "abdq_u32" => p!("vabdu.v4i32", (i32x4, i32x4) -> i32x4),
-        "abd_f32" => p!("vabds.v2f32", (f32x2, f32x2) -> f32x2),
-        "abdq_f32" => p!("vabds.v4f32", (f32x4, f32x4) -> f32x4),
-        "max_s8" => p!("vmaxs.v8i8", (i8x8, i8x8) -> i8x8),
-        "maxq_s8" => p!("vmaxs.v16i8", (i8x16, i8x16) -> i8x16),
-        "max_s16" => p!("vmaxs.v4i16", (i16x4, i16x4) -> i16x4),
-        "maxq_s16" => p!("vmaxs.v8i16", (i16x8, i16x8) -> i16x8),
-        "max_s32" => p!("vmaxs.v2i32", (i32x2, i32x2) -> i32x2),
-        "maxq_s32" => p!("vmaxs.v4i32", (i32x4, i32x4) -> i32x4),
-        "max_u8" => p!("vmaxu.v8i8", (i8x8, i8x8) -> i8x8),
-        "maxq_u8" => p!("vmaxu.v16i8", (i8x16, i8x16) -> i8x16),
-        "max_u16" => p!("vmaxu.v4i16", (i16x4, i16x4) -> i16x4),
-        "maxq_u16" => p!("vmaxu.v8i16", (i16x8, i16x8) -> i16x8),
-        "max_u32" => p!("vmaxu.v2i32", (i32x2, i32x2) -> i32x2),
-        "maxq_u32" => p!("vmaxu.v4i32", (i32x4, i32x4) -> i32x4),
-        "max_f32" => p!("vmaxs.v2f32", (f32x2, f32x2) -> f32x2),
-        "maxq_f32" => p!("vmaxs.v4f32", (f32x4, f32x4) -> f32x4),
-        "min_s8" => p!("vmins.v8i8", (i8x8, i8x8) -> i8x8),
-        "minq_s8" => p!("vmins.v16i8", (i8x16, i8x16) -> i8x16),
-        "min_s16" => p!("vmins.v4i16", (i16x4, i16x4) -> i16x4),
-        "minq_s16" => p!("vmins.v8i16", (i16x8, i16x8) -> i16x8),
-        "min_s32" => p!("vmins.v2i32", (i32x2, i32x2) -> i32x2),
-        "minq_s32" => p!("vmins.v4i32", (i32x4, i32x4) -> i32x4),
-        "min_u8" => p!("vminu.v8i8", (i8x8, i8x8) -> i8x8),
-        "minq_u8" => p!("vminu.v16i8", (i8x16, i8x16) -> i8x16),
-        "min_u16" => p!("vminu.v4i16", (i16x4, i16x4) -> i16x4),
-        "minq_u16" => p!("vminu.v8i16", (i16x8, i16x8) -> i16x8),
-        "min_u32" => p!("vminu.v2i32", (i32x2, i32x2) -> i32x2),
-        "minq_u32" => p!("vminu.v4i32", (i32x4, i32x4) -> i32x4),
-        "min_f32" => p!("vmins.v2f32", (f32x2, f32x2) -> f32x2),
-        "minq_f32" => p!("vmins.v4f32", (f32x4, f32x4) -> f32x4),
-        "shl_s8" => p!("vshifts.v8i8", (i8x8, i8x8) -> i8x8),
-        "shlq_s8" => p!("vshifts.v16i8", (i8x16, i8x16) -> i8x16),
-        "shl_s16" => p!("vshifts.v4i16", (i16x4, i16x4) -> i16x4),
-        "shlq_s16" => p!("vshifts.v8i16", (i16x8, i16x8) -> i16x8),
-        "shl_s32" => p!("vshifts.v2i32", (i32x2, i32x2) -> i32x2),
-        "shlq_s32" => p!("vshifts.v4i32", (i32x4, i32x4) -> i32x4),
-        "shl_s64" => p!("vshiftu.v1i64", (i64x1, i64x1) -> i64x1),
-        "shlq_s64" => p!("vshiftu.v2i64", (i64x2, i64x2) -> i64x2),
-        "shl_u8" => p!("vshiftu.v8i8", (i8x8, i8x8) -> i8x8),
-        "shlq_u8" => p!("vshiftu.v16i8", (i8x16, i8x16) -> i8x16),
-        "shl_u16" => p!("vshiftu.v4i16", (i16x4, i16x4) -> i16x4),
-        "shlq_u16" => p!("vshiftu.v8i16", (i16x8, i16x8) -> i16x8),
-        "shl_u32" => p!("vshiftu.v2i32", (i32x2, i32x2) -> i32x2),
-        "shlq_u32" => p!("vshiftu.v4i32", (i32x4, i32x4) -> i32x4),
-        "shl_u64" => p!("vshiftu.v1i64", (i64x1, i64x1) -> i64x1),
-        "shlq_u64" => p!("vshiftu.v2i64", (i64x2, i64x2) -> i64x2),
-        "qshl_s8" => p!("vqshifts.v8i8", (i8x8, i8x8) -> i8x8),
-        "qshlq_s8" => p!("vqshifts.v16i8", (i8x16, i8x16) -> i8x16),
-        "qshl_s16" => p!("vqshifts.v4i16", (i16x4, i16x4) -> i16x4),
-        "qshlq_s16" => p!("vqshifts.v8i16", (i16x8, i16x8) -> i16x8),
-        "qshl_s32" => p!("vqshifts.v2i32", (i32x2, i32x2) -> i32x2),
-        "qshlq_s32" => p!("vqshifts.v4i32", (i32x4, i32x4) -> i32x4),
-        "qshl_s64" => p!("vqshiftu.v1i64", (i64x1, i64x1) -> i64x1),
-        "qshlq_s64" => p!("vqshiftu.v2i64", (i64x2, i64x2) -> i64x2),
-        "qshl_u8" => p!("vqshiftu.v8i8", (i8x8, i8x8) -> i8x8),
-        "qshlq_u8" => p!("vqshiftu.v16i8", (i8x16, i8x16) -> i8x16),
-        "qshl_u16" => p!("vqshiftu.v4i16", (i16x4, i16x4) -> i16x4),
-        "qshlq_u16" => p!("vqshiftu.v8i16", (i16x8, i16x8) -> i16x8),
-        "qshl_u32" => p!("vqshiftu.v2i32", (i32x2, i32x2) -> i32x2),
-        "qshlq_u32" => p!("vqshiftu.v4i32", (i32x4, i32x4) -> i32x4),
-        "qshl_u64" => p!("vqshiftu.v1i64", (i64x1, i64x1) -> i64x1),
-        "qshlq_u64" => p!("vqshiftu.v2i64", (i64x2, i64x2) -> i64x2),
-        "rshl_s8" => p!("vrshifts.v8i8", (i8x8, i8x8) -> i8x8),
-        "rshlr_s8" => p!("vrshifts.v16i8", (i8x16, i8x16) -> i8x16),
-        "rshl_s16" => p!("vrshifts.v4i16", (i16x4, i16x4) -> i16x4),
-        "rshlr_s16" => p!("vrshifts.v8i16", (i16x8, i16x8) -> i16x8),
-        "rshl_s32" => p!("vrshifts.v2i32", (i32x2, i32x2) -> i32x2),
-        "rshlr_s32" => p!("vrshifts.v4i32", (i32x4, i32x4) -> i32x4),
-        "rshl_s64" => p!("vrshiftu.v1i64", (i64x1, i64x1) -> i64x1),
-        "rshlr_s64" => p!("vrshiftu.v2i64", (i64x2, i64x2) -> i64x2),
-        "rshl_u8" => p!("vrshiftu.v8i8", (i8x8, i8x8) -> i8x8),
-        "rshlr_u8" => p!("vrshiftu.v16i8", (i8x16, i8x16) -> i8x16),
-        "rshl_u16" => p!("vrshiftu.v4i16", (i16x4, i16x4) -> i16x4),
-        "rshlr_u16" => p!("vrshiftu.v8i16", (i16x8, i16x8) -> i16x8),
-        "rshl_u32" => p!("vrshiftu.v2i32", (i32x2, i32x2) -> i32x2),
-        "rshlr_u32" => p!("vrshiftu.v4i32", (i32x4, i32x4) -> i32x4),
-        "rshl_u64" => p!("vrshiftu.v1i64", (i64x1, i64x1) -> i64x1),
-        "rshlr_u64" => p!("vrshiftu.v2i64", (i64x2, i64x2) -> i64x2),
-        "qrshl_s8" => p!("vqrshifts.v8i8", (i8x8, i8x8) -> i8x8),
-        "qrshlqr_s8" => p!("vqrshifts.v16i8", (i8x16, i8x16) -> i8x16),
-        "qrshl_s16" => p!("vqrshifts.v4i16", (i16x4, i16x4) -> i16x4),
-        "qrshlqr_s16" => p!("vqrshifts.v8i16", (i16x8, i16x8) -> i16x8),
-        "qrshl_s32" => p!("vqrshifts.v2i32", (i32x2, i32x2) -> i32x2),
-        "qrshlqr_s32" => p!("vqrshifts.v4i32", (i32x4, i32x4) -> i32x4),
-        "qrshl_s64" => p!("vqrshiftu.v1i64", (i64x1, i64x1) -> i64x1),
-        "qrshlqr_s64" => p!("vqrshiftu.v2i64", (i64x2, i64x2) -> i64x2),
-        "qrshl_u8" => p!("vqrshiftu.v8i8", (i8x8, i8x8) -> i8x8),
-        "qrshlqr_u8" => p!("vqrshiftu.v16i8", (i8x16, i8x16) -> i8x16),
-        "qrshl_u16" => p!("vqrshiftu.v4i16", (i16x4, i16x4) -> i16x4),
-        "qrshlqr_u16" => p!("vqrshiftu.v8i16", (i16x8, i16x8) -> i16x8),
-        "qrshl_u32" => p!("vqrshiftu.v2i32", (i32x2, i32x2) -> i32x2),
-        "qrshlqr_u32" => p!("vqrshiftu.v4i32", (i32x4, i32x4) -> i32x4),
-        "qrshl_u64" => p!("vqrshiftu.v1i64", (i64x1, i64x1) -> i64x1),
-        "qrshlqr_u64" => p!("vqrshiftu.v2i64", (i64x2, i64x2) -> i64x2),
-        "qmovn_s16" => p!("vqmovns.v8i8", (i16x8) -> i8x8),
-        "qmovn_s32" => p!("vqmovns.v4i16", (i32x4) -> i16x4),
-        "qmovn_s64" => p!("vqmovns.v2i32", (i64x2) -> i32x2),
-        "qmovn_u16" => p!("vqmovnu.v8i8", (i16x8) -> i8x8),
-        "qmovn_u32" => p!("vqmovnu.v4i16", (i32x4) -> i16x4),
-        "qmovn_u64" => p!("vqmovnu.v2i32", (i64x2) -> i32x2),
-        "qmovun_s16" => p!("vqmovnsu.v8i8", (i16x8) -> i8x8),
-        "qmovun_s32" => p!("vqmovnsu.v4i16", (i32x4) -> i16x4),
-        "qmovun_s64" => p!("vqmovnsu.v2i32", (i64x2) -> i32x2),
-        "abs_s8" => p!("vabs.v8i8", (i8x8, i8x8) -> i8x8),
-        "absq_s8" => p!("vabs.v16i8", (i8x16, i8x16) -> i8x16),
-        "abs_s16" => p!("vabs.v4i16", (i16x4, i16x4) -> i16x4),
-        "absq_s16" => p!("vabs.v8i16", (i16x8, i16x8) -> i16x8),
-        "abs_s32" => p!("vabs.v2i32", (i32x2, i32x2) -> i32x2),
-        "absq_s32" => p!("vabs.v4i32", (i32x4, i32x4) -> i32x4),
-        "abs_f32" => p!("vabs.v2f32", (f32x2, f32x2) -> f32x2),
-        "absq_f32" => p!("vabs.v4f32", (f32x4, f32x4) -> f32x4),
-        "qabs_s8" => p!("vqabs.v8i8", (i8x8, i8x8) -> i8x8),
-        "qabsq_s8" => p!("vqabs.v16i8", (i8x16, i8x16) -> i8x16),
-        "qabs_s16" => p!("vqabs.v4i16", (i16x4, i16x4) -> i16x4),
-        "qabsq_s16" => p!("vqabs.v8i16", (i16x8, i16x8) -> i16x8),
-        "qabs_s32" => p!("vqabs.v2i32", (i32x2, i32x2) -> i32x2),
-        "qabsq_s32" => p!("vqabs.v4i32", (i32x4, i32x4) -> i32x4),
-        "neg_s8" => p!("vneg.v8i8", (i8x8) -> i8x8),
-        "negq_s8" => p!("vneg.v16i8", (i8x16) -> i8x16),
-        "neg_s16" => p!("vneg.v4i16", (i16x4) -> i16x4),
-        "negq_s16" => p!("vneg.v8i16", (i16x8) -> i16x8),
-        "neg_s32" => p!("vneg.v2i32", (i32x2) -> i32x2),
-        "negq_s32" => p!("vneg.v4i32", (i32x4) -> i32x4),
-        "neg_f32" => p!("vneg.v2f32", (f32x2) -> f32x2),
-        "negq_f32" => p!("vneg.v4f32", (f32x4) -> f32x4),
-        "qneg_s8" => p!("vqneg.v8i8", (i8x8) -> i8x8),
-        "qnegq_s8" => p!("vqneg.v16i8", (i8x16) -> i8x16),
-        "qneg_s16" => p!("vqneg.v4i16", (i16x4) -> i16x4),
-        "qnegq_s16" => p!("vqneg.v8i16", (i16x8) -> i16x8),
-        "qneg_s32" => p!("vqneg.v2i32", (i32x2) -> i32x2),
-        "qnegq_s32" => p!("vqneg.v4i32", (i32x4) -> i32x4),
-        "cls_s8" => p!("vcls.v8i8", (i8x8) -> i8x8),
-        "clsq_s8" => p!("vcls.v16i8", (i8x16) -> i8x16),
-        "cls_s16" => p!("vcls.v4i16", (i16x4) -> i16x4),
-        "clsq_s16" => p!("vcls.v8i16", (i16x8) -> i16x8),
-        "cls_s32" => p!("vcls.v2i32", (i32x2) -> i32x2),
-        "clsq_s32" => p!("vcls.v4i32", (i32x4) -> i32x4),
-        "clz_s8" => p!("vclz.v8i8", (i8x8) -> i8x8),
-        "clzq_s8" => p!("vclz.v16i8", (i8x16) -> i8x16),
-        "clz_s16" => p!("vclz.v4i16", (i16x4) -> i16x4),
-        "clzq_s16" => p!("vclz.v8i16", (i16x8) -> i16x8),
-        "clz_s32" => p!("vclz.v2i32", (i32x2) -> i32x2),
-        "clzq_s32" => p!("vclz.v4i32", (i32x4) -> i32x4),
-        "cnt_s8" => p!("vcnt.v8i8", (i8x8) -> i8x8),
-        "cntq_s8" => p!("vcnt.v16i8", (i8x16) -> i8x16),
-        "recpe_u32" => p!("vrecpe.v2i32", (i32x2) -> i32x2),
-        "recpeq_u32" => p!("vrecpe.v4i32", (i32x4) -> i32x4),
-        "recpe_f32" => p!("vrecpe.v2f32", (f32x2) -> f32x2),
-        "recpeq_f32" => p!("vrecpe.v4f32", (f32x4) -> f32x4),
-        "recps_f32" => p!("vrecps.v2f32", (f32x2, f32x2) -> f32x2),
-        "recpsq_f32" => p!("vrecps.v4f32", (f32x4, f32x4) -> f32x4),
-        "rsqrte_u32" => p!("vrsqrte.v2i32", (i32x2) -> i32x2),
-        "rsqrteq_u32" => p!("vrsqrte.v4i32", (i32x4) -> i32x4),
-        "rsqrte_f32" => p!("vrsqrte.v2f32", (f32x2) -> f32x2),
-        "rsqrteq_f32" => p!("vrsqrte.v4f32", (f32x4) -> f32x4),
-        "rsqrts_f32" => p!("vrsqrts.v2f32", (f32x2, f32x2) -> f32x2),
-        "rsqrtsq_f32" => p!("vrsqrts.v4f32", (f32x4, f32x4) -> f32x4),
-        "bsl_s8" => p!("vsl.v8i8", (i8x8, i8x8, i8x8) -> i8x8),
-        "bslq_s8" => p!("vsl.v16i8", (i8x16, i8x16, i8x16) -> i8x16),
-        "padd_s8" => p!("vpadd.v8i8", (i8x8, i8x8) -> i8x8),
-        "padd_s16" => p!("vpadd.v4i16", (i16x4, i16x4) -> i16x4),
-        "padd_s32" => p!("vpadd.v2i32", (i32x2, i32x2) -> i32x2),
-        "padd_u8" => p!("vpadd.v8i8", (i8x8, i8x8) -> i8x8),
-        "padd_u16" => p!("vpadd.v4i16", (i16x4, i16x4) -> i16x4),
-        "padd_u32" => p!("vpadd.v2i32", (i32x2, i32x2) -> i32x2),
-        "padd_f32" => p!("vpadd.v2f32", (f32x2, f32x2) -> f32x2),
-        "paddl_s8" => p!("vpaddls.v4i16.v8i8", (i8x8) -> i16x4),
-        "paddlq_s8" => p!("vpaddls.v8i16.v16i8", (i8x16) -> i16x8),
-        "paddl_s16" => p!("vpaddls.v2i32.v4i16", (i16x4) -> i32x2),
-        "paddlq_s16" => p!("vpaddls.v4i32.v8i16", (i16x8) -> i32x4),
-        "paddl_s32" => p!("vpaddls.v1i64.v2i32", (i32x2) -> i64x1),
-        "paddlq_s32" => p!("vpaddls.v2i64.v4i32", (i32x4) -> i64x2),
-        "paddl_u8" => p!("vpaddlu.v4i16.v8i8", (i8x8) -> i16x4),
-        "paddlq_u8" => p!("vpaddlu.v8i16.v16i8", (i8x16) -> i16x8),
-        "paddl_u16" => p!("vpaddlu.v2i32.v4i16", (i16x4) -> i32x2),
-        "paddlq_u16" => p!("vpaddlu.v4i32.v8i16", (i16x8) -> i32x4),
-        "paddl_u32" => p!("vpaddlu.v1i64.v2i32", (i32x2) -> i64x1),
-        "paddlq_u32" => p!("vpaddlu.v2i64.v4i32", (i32x4) -> i64x2),
-        "padal_s8" => p!("vpadals.v4i16.v8i8", (i16x4, i8x8) -> i16x4),
-        "padalq_s8" => p!("vpadals.v8i16.v16i8", (i16x8, i8x16) -> i16x8),
-        "padal_s16" => p!("vpadals.v2i32.v4i16", (i32x2, i16x4) -> i32x2),
-        "padalq_s16" => p!("vpadals.v4i32.v8i16", (i32x4, i16x8) -> i32x4),
-        "padal_s32" => p!("vpadals.v1i64.v2i32", (i64x1, i32x2) -> i64x1),
-        "padalq_s32" => p!("vpadals.v2i64.v4i32", (i64x2, i32x4) -> i64x2),
-        "padal_u8" => p!("vpadalu.v4i16.v8i8", (i16x4, i8x8) -> i16x4),
-        "padalq_u8" => p!("vpadalu.v8i16.v16i8", (i16x8, i8x16) -> i16x8),
-        "padal_u16" => p!("vpadalu.v2i32.v4i16", (i32x2, i16x4) -> i32x2),
-        "padalq_u16" => p!("vpadalu.v4i32.v8i16", (i32x4, i16x8) -> i32x4),
-        "padal_u32" => p!("vpadalu.v1i64.v2i32", (i64x1, i32x2) -> i64x1),
-        "padalq_u32" => p!("vpadalu.v2i64.v4i32", (i64x2, i32x4) -> i64x2),
-        "pmax_s16" => p!("vpmaxs.v4i16", (i16x4, i16x4) -> i16x4),
-        "pmax_s32" => p!("vpmaxs.v2i32", (i32x2, i32x2) -> i32x2),
-        "pmax_s8" => p!("vpmaxs.v8i8", (i8x8, i8x8) -> i8x8),
-        "pmax_u16" => p!("vpmaxu.v4i16", (i16x4, i16x4) -> i16x4),
-        "pmax_u32" => p!("vpmaxu.v2i32", (i32x2, i32x2) -> i32x2),
-        "pmax_u8" => p!("vpmaxu.v8i8", (i8x8, i8x8) -> i8x8),
-        "pmin_s16" => p!("vpmins.v4i16", (i16x4, i16x4) -> i16x4),
-        "pmin_s32" => p!("vpmins.v2i32", (i32x2, i32x2) -> i32x2),
-        "pmin_s8" => p!("vpmins.v8i8", (i8x8, i8x8) -> i8x8),
-        "pmin_u16" => p!("vpminu.v4i16", (i16x4, i16x4) -> i16x4),
-        "pmin_u32" => p!("vpminu.v2i32", (i32x2, i32x2) -> i32x2),
-        "pmin_u8" => p!("vpminu.v8i8", (i8x8, i8x8) -> i8x8),
-        "tbl1_s8" => p!("vtbl1", (i8x8, i8x8) -> i8x8),
-        "tbl1_u8" => p!("vtbl1", (i8x8, i8x8) -> i8x8),
-        // these aren't exactly the C intrinsics (they take one argument)
-        "tbl2_s8" => p!("vtbl2", (i8x8, i8x8, i8x8) -> i8x8),
-        "tbl2_u8" => p!("vtbl2", (i8x8, i8x8, i8x8) -> i8x8),
-        "tbl3_s8" => p!("vtbl3", (i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbl3_u8" => p!("vtbl3", (i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbl4_s8" => p!("vtbl4", (i8x8, i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbl4_u8" => p!("vtbl4", (i8x8, i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbx1_s8" => p!("vtbx1", (i8x8, i8x8, i8x8) -> i8x8),
-        "tbx1_u8" => p!("vtbx1", (i8x8, i8x8, i8x8) -> i8x8),
-        "tbx2_s8" => p!("vtbx2", (i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbx2_u8" => p!("vtbx2", (i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbx3_s8" => p!("vtbx3", (i8x8, i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbx3_u8" => p!("vtbx3", (i8x8, i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbx4_s8" => p!("vtbx4", (i8x8, i8x8, i8x8, i8x8, i8x8, i8x8) -> i8x8),
-        "tbx4_u8" => p!("vtbx4", (i8x8, i8x8, i8x8, i8x8, i8x8, i8x8) -> i8x8),
+        "hadd_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vhadds.v8i8")
+        },
+        "hadd_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vhaddu.v8i8")
+        },
+        "hadd_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vhadds.v4i16")
+        },
+        "hadd_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vhaddu.v4i16")
+        },
+        "hadd_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vhadds.v2i32")
+        },
+        "hadd_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vhaddu.v2i32")
+        },
+        "haddq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vhadds.v16i8")
+        },
+        "haddq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vhaddu.v16i8")
+        },
+        "haddq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vhadds.v8i16")
+        },
+        "haddq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vhaddu.v8i16")
+        },
+        "haddq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vhadds.v4i32")
+        },
+        "haddq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vhaddu.v4i32")
+        },
+        "rhadd_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vrhadds.v8i8")
+        },
+        "rhadd_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vrhaddu.v8i8")
+        },
+        "rhadd_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vrhadds.v4i16")
+        },
+        "rhadd_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vrhaddu.v4i16")
+        },
+        "rhadd_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vrhadds.v2i32")
+        },
+        "rhadd_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vrhaddu.v2i32")
+        },
+        "rhaddq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vrhadds.v16i8")
+        },
+        "rhaddq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vrhaddu.v16i8")
+        },
+        "rhaddq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vrhadds.v8i16")
+        },
+        "rhaddq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vrhaddu.v8i16")
+        },
+        "rhaddq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vrhadds.v4i32")
+        },
+        "rhaddq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vrhaddu.v4i32")
+        },
+        "qadd_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vqadds.v8i8")
+        },
+        "qadd_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vqaddu.v8i8")
+        },
+        "qadd_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vqadds.v4i16")
+        },
+        "qadd_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vqaddu.v4i16")
+        },
+        "qadd_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vqadds.v2i32")
+        },
+        "qadd_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vqaddu.v2i32")
+        },
+        "qadd_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vqadds.v1i64")
+        },
+        "qadd_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(u(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vqaddu.v1i64")
+        },
+        "qaddq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vqadds.v16i8")
+        },
+        "qaddq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vqaddu.v16i8")
+        },
+        "qaddq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vqadds.v8i16")
+        },
+        "qaddq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vqaddu.v8i16")
+        },
+        "qaddq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vqadds.v4i32")
+        },
+        "qaddq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vqaddu.v4i32")
+        },
+        "qaddq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vqadds.v2i64")
+        },
+        "qaddq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(u(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vqaddu.v2i64")
+        },
+        "raddhn_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vraddhn.v8i8")
+        },
+        "raddhn_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vraddhn.v8i8")
+        },
+        "raddhn_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vraddhn.v4i16")
+        },
+        "raddhn_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vraddhn.v4i16")
+        },
+        "raddhn_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vraddhn.v2i32")
+        },
+        "raddhn_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(u(64), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vraddhn.v2i32")
+        },
+        "fma_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.fma.v2f32")
+        },
+        "fmaq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4), v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.fma.v4f32")
+        },
+        "qdmulh_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vsqdmulh.v4i16")
+        },
+        "qdmulh_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vsqdmulh.v2i32")
+        },
+        "qdmulhq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vsqdmulh.v8i16")
+        },
+        "qdmulhq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vsqdmulh.v4i32")
+        },
+        "qrdmulh_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vsqrdmulh.v4i16")
+        },
+        "qrdmulh_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vsqrdmulh.v2i32")
+        },
+        "qrdmulhq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vsqrdmulh.v8i16")
+        },
+        "qrdmulhq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vsqrdmulh.v4i32")
+        },
+        "mull_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vmulls.v8i16")
+        },
+        "mull_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vmullu.v8i16")
+        },
+        "mull_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vmulls.v4i32")
+        },
+        "mull_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vmullu.v4i32")
+        },
+        "mull_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vmulls.v2i64")
+        },
+        "mull_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vmullu.v2i64")
+        },
+        "qdmullq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vsqdmull.v8i16")
+        },
+        "qdmullq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vsqdmull.v4i32")
+        },
+        "hsub_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vhsubs.v8i8")
+        },
+        "hsub_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vhsubu.v8i8")
+        },
+        "hsub_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vhsubs.v4i16")
+        },
+        "hsub_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vhsubu.v4i16")
+        },
+        "hsub_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vhsubs.v2i32")
+        },
+        "hsub_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vhsubu.v2i32")
+        },
+        "hsubq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vhsubs.v16i8")
+        },
+        "hsubq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vhsubu.v16i8")
+        },
+        "hsubq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vhsubs.v8i16")
+        },
+        "hsubq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vhsubu.v8i16")
+        },
+        "hsubq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vhsubs.v4i32")
+        },
+        "hsubq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vhsubu.v4i32")
+        },
+        "qsub_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vqsubs.v8i8")
+        },
+        "qsub_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vqsubu.v8i8")
+        },
+        "qsub_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vqsubs.v4i16")
+        },
+        "qsub_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vqsubu.v4i16")
+        },
+        "qsub_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vqsubs.v2i32")
+        },
+        "qsub_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vqsubu.v2i32")
+        },
+        "qsub_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vqsubs.v1i64")
+        },
+        "qsub_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(u(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vqsubu.v1i64")
+        },
+        "qsubq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vqsubs.v16i8")
+        },
+        "qsubq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vqsubu.v16i8")
+        },
+        "qsubq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vqsubs.v8i16")
+        },
+        "qsubq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vqsubu.v8i16")
+        },
+        "qsubq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vqsubs.v4i32")
+        },
+        "qsubq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vqsubu.v4i32")
+        },
+        "qsubq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vqsubs.v2i64")
+        },
+        "qsubq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(u(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vqsubu.v2i64")
+        },
+        "rsubhn_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vrsubhn.v8i8")
+        },
+        "rsubhn_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vrsubhn.v8i8")
+        },
+        "rsubhn_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vrsubhn.v4i16")
+        },
+        "rsubhn_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vrsubhn.v4i16")
+        },
+        "rsubhn_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vrsubhn.v2i32")
+        },
+        "rsubhn_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(u(64), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vrsubhn.v2i32")
+        },
+        "abd_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vabds.v8i8")
+        },
+        "abd_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vabdu.v8i8")
+        },
+        "abd_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vabds.v4i16")
+        },
+        "abd_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vabdu.v4i16")
+        },
+        "abd_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vabds.v2i32")
+        },
+        "abd_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vabdu.v2i32")
+        },
+        "abd_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vabdf.v2f32")
+        },
+        "abdq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vabds.v16i8")
+        },
+        "abdq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vabdu.v16i8")
+        },
+        "abdq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vabds.v8i16")
+        },
+        "abdq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vabdu.v8i16")
+        },
+        "abdq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vabds.v4i32")
+        },
+        "abdq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vabdu.v4i32")
+        },
+        "abdq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4), v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.neon.vabdf.v4f32")
+        },
+        "max_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vmaxs.v8i8")
+        },
+        "max_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vmaxu.v8i8")
+        },
+        "max_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vmaxs.v4i16")
+        },
+        "max_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vmaxu.v4i16")
+        },
+        "max_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vmaxs.v2i32")
+        },
+        "max_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vmaxu.v2i32")
+        },
+        "max_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vmaxf.v2f32")
+        },
+        "maxq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vmaxs.v16i8")
+        },
+        "maxq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vmaxu.v16i8")
+        },
+        "maxq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vmaxs.v8i16")
+        },
+        "maxq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vmaxu.v8i16")
+        },
+        "maxq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vmaxs.v4i32")
+        },
+        "maxq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vmaxu.v4i32")
+        },
+        "maxq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4), v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.neon.vmaxf.v4f32")
+        },
+        "min_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vmins.v8i8")
+        },
+        "min_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vminu.v8i8")
+        },
+        "min_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vmins.v4i16")
+        },
+        "min_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vminu.v4i16")
+        },
+        "min_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vmins.v2i32")
+        },
+        "min_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vminu.v2i32")
+        },
+        "min_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vminf.v2f32")
+        },
+        "minq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vmins.v16i8")
+        },
+        "minq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vminu.v16i8")
+        },
+        "minq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vmins.v8i16")
+        },
+        "minq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vminu.v8i16")
+        },
+        "minq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vmins.v4i32")
+        },
+        "minq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vminu.v4i32")
+        },
+        "minq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4), v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.neon.vminf.v4f32")
+        },
+        "shl_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vshls.v8i8")
+        },
+        "shl_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(i(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vshlu.v8i8")
+        },
+        "shl_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vshls.v4i16")
+        },
+        "shl_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(i(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vshlu.v4i16")
+        },
+        "shl_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vshls.v2i32")
+        },
+        "shl_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(i(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vshlu.v2i32")
+        },
+        "shl_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vshls.v1i64")
+        },
+        "shl_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(i(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vshlu.v1i64")
+        },
+        "shlq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vshls.v16i8")
+        },
+        "shlq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(i(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vshlu.v16i8")
+        },
+        "shlq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vshls.v8i16")
+        },
+        "shlq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(i(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vshlu.v8i16")
+        },
+        "shlq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vshls.v4i32")
+        },
+        "shlq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(i(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vshlu.v4i32")
+        },
+        "shlq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vshls.v2i64")
+        },
+        "shlq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(i(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vshlu.v2i64")
+        },
+        "qshl_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vqshls.v8i8")
+        },
+        "qshl_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(i(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vqshlu.v8i8")
+        },
+        "qshl_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vqshls.v4i16")
+        },
+        "qshl_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(i(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vqshlu.v4i16")
+        },
+        "qshl_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vqshls.v2i32")
+        },
+        "qshl_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(i(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vqshlu.v2i32")
+        },
+        "qshl_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vqshls.v1i64")
+        },
+        "qshl_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(i(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vqshlu.v1i64")
+        },
+        "qshlq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vqshls.v16i8")
+        },
+        "qshlq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(i(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vqshlu.v16i8")
+        },
+        "qshlq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vqshls.v8i16")
+        },
+        "qshlq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(i(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vqshlu.v8i16")
+        },
+        "qshlq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vqshls.v4i32")
+        },
+        "qshlq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(i(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vqshlu.v4i32")
+        },
+        "qshlq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vqshls.v2i64")
+        },
+        "qshlq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(i(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vqshlu.v2i64")
+        },
+        "rshl_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vrshls.v8i8")
+        },
+        "rshl_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(i(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vrshlu.v8i8")
+        },
+        "rshl_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vrshls.v4i16")
+        },
+        "rshl_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(i(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vrshlu.v4i16")
+        },
+        "rshl_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vrshls.v2i32")
+        },
+        "rshl_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(i(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vrshlu.v2i32")
+        },
+        "rshl_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vrshls.v1i64")
+        },
+        "rshl_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(i(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vrshlu.v1i64")
+        },
+        "rshlq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vrshls.v16i8")
+        },
+        "rshlq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(i(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vrshlu.v16i8")
+        },
+        "rshlq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vrshls.v8i16")
+        },
+        "rshlq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(i(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vrshlu.v8i16")
+        },
+        "rshlq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vrshls.v4i32")
+        },
+        "rshlq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(i(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vrshlu.v4i32")
+        },
+        "rshlq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vrshls.v2i64")
+        },
+        "rshlq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(i(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vrshlu.v2i64")
+        },
+        "qrshl_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vqrshls.v8i8")
+        },
+        "qrshl_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(i(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vqrshlu.v8i8")
+        },
+        "qrshl_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vqrshls.v4i16")
+        },
+        "qrshl_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(i(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vqrshlu.v4i16")
+        },
+        "qrshl_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vqrshls.v2i32")
+        },
+        "qrshl_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(i(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vqrshlu.v2i32")
+        },
+        "qrshl_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vqrshls.v1i64")
+        },
+        "qrshl_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(i(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vqrshlu.v1i64")
+        },
+        "qrshlq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vqrshls.v16i8")
+        },
+        "qrshlq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(i(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vqrshlu.v16i8")
+        },
+        "qrshlq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vqrshls.v8i16")
+        },
+        "qrshlq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(i(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vqrshlu.v8i16")
+        },
+        "qrshlq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vqrshls.v4i32")
+        },
+        "qrshlq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(i(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vqrshlu.v4i32")
+        },
+        "qrshlq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vqrshls.v2i64")
+        },
+        "qrshlq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(i(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vqrshlu.v2i64")
+        },
+        "qshrun_n_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), u(32)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vsqshrun.v8i8")
+        },
+        "qshrun_n_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), u(32)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vsqshrun.v4i16")
+        },
+        "qshrun_n_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), u(32)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vsqshrun.v2i32")
+        },
+        "qrshrun_n_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), u(32)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vsqrshrun.v8i8")
+        },
+        "qrshrun_n_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), u(32)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vsqrshrun.v4i16")
+        },
+        "qrshrun_n_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), u(32)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vsqrshrun.v2i32")
+        },
+        "qshrn_n_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), u(32)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vqshrns.v8i8")
+        },
+        "qshrn_n_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), u(32)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vqshrnu.v8i8")
+        },
+        "qshrn_n_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), u(32)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vqshrns.v4i16")
+        },
+        "qshrn_n_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), u(32)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vqshrnu.v4i16")
+        },
+        "qshrn_n_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), u(32)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vqshrns.v2i32")
+        },
+        "qshrn_n_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), u(32)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vqshrnu.v2i32")
+        },
+        "rshrn_n_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), u(32)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vrshrn.v8i8")
+        },
+        "rshrn_n_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), u(32)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vrshrn.v8i8")
+        },
+        "rshrn_n_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), u(32)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vrshrn.v4i16")
+        },
+        "rshrn_n_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), u(32)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vrshrn.v4i16")
+        },
+        "rshrn_n_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), u(32)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vrshrn.v2i32")
+        },
+        "rshrn_n_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), u(32)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vrshrn.v2i32")
+        },
+        "qrshrn_n_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), u(32)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vqrshrns.v8i8")
+        },
+        "qrshrn_n_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), u(32)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vqrshrnu.v8i8")
+        },
+        "qrshrn_n_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), u(32)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vqrshrns.v4i16")
+        },
+        "qrshrn_n_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), u(32)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vqrshrnu.v4i16")
+        },
+        "qrshrn_n_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), u(32)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vqrshrns.v2i32")
+        },
+        "qrshrn_n_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), u(32)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vqrshrnu.v2i32")
+        },
+        "sri_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vvsri.v8i8")
+        },
+        "sri_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vvsri.v8i8")
+        },
+        "sri_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vvsri.v4i16")
+        },
+        "sri_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vvsri.v4i16")
+        },
+        "sri_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vvsri.v2i32")
+        },
+        "sri_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vvsri.v2i32")
+        },
+        "sri_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vvsri.v1i64")
+        },
+        "sri_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(u(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vvsri.v1i64")
+        },
+        "sriq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vvsri.v16i8")
+        },
+        "sriq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vvsri.v16i8")
+        },
+        "sriq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vvsri.v8i16")
+        },
+        "sriq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vvsri.v8i16")
+        },
+        "sriq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vvsri.v4i32")
+        },
+        "sriq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vvsri.v4i32")
+        },
+        "sriq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vvsri.v2i64")
+        },
+        "sriq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(u(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vvsri.v2i64")
+        },
+        "sli_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vvsli.v8i8")
+        },
+        "sli_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vvsli.v8i8")
+        },
+        "sli_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vvsli.v4i16")
+        },
+        "sli_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vvsli.v4i16")
+        },
+        "sli_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vvsli.v2i32")
+        },
+        "sli_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vvsli.v2i32")
+        },
+        "sli_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vvsli.v1i64")
+        },
+        "sli_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(u(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vvsli.v1i64")
+        },
+        "sliq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vvsli.v16i8")
+        },
+        "sliq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vvsli.v16i8")
+        },
+        "sliq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vvsli.v8i16")
+        },
+        "sliq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vvsli.v8i16")
+        },
+        "sliq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vvsli.v4i32")
+        },
+        "sliq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vvsli.v4i32")
+        },
+        "sliq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vvsli.v2i64")
+        },
+        "sliq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(u(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vvsli.v2i64")
+        },
+        "vqmovn_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vqxtns.v8i8")
+        },
+        "vqmovn_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vqxtnu.v8i8")
+        },
+        "vqmovn_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vqxtns.v4i16")
+        },
+        "vqmovn_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vqxtnu.v4i16")
+        },
+        "vqmovn_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vqxtns.v2i32")
+        },
+        "vqmovn_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vqxtnu.v2i32")
+        },
+        "abs_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vabs.v8i8")
+        },
+        "abs_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vabs.v4i16")
+        },
+        "abs_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vabs.v2i32")
+        },
+        "absq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vabs.v16i8")
+        },
+        "absq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vabs.v8i16")
+        },
+        "absq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vabs.v4i32")
+        },
+        "abs_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.fabs.v2f32")
+        },
+        "absq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.fabs.v4f32")
+        },
+        "qabs_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vsqabs.v8i8")
+        },
+        "qabs_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vsqabs.v4i16")
+        },
+        "qabs_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vsqabs.v2i32")
+        },
+        "qabsq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vsqabs.v16i8")
+        },
+        "qabsq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vsqabs.v8i16")
+        },
+        "qabsq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vsqabs.v4i32")
+        },
+        "qneg_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vsqneg.v8i8")
+        },
+        "qneg_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vsqneg.v4i16")
+        },
+        "qneg_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vsqneg.v2i32")
+        },
+        "qnegq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vsqneg.v16i8")
+        },
+        "qnegq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vsqneg.v8i16")
+        },
+        "qnegq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vsqneg.v4i32")
+        },
+        "clz_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.ctlz.v8i8")
+        },
+        "clz_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.ctlz.v8i8")
+        },
+        "clz_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.ctlz.v4i16")
+        },
+        "clz_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.ctlz.v4i16")
+        },
+        "clz_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.ctlz.v2i32")
+        },
+        "clz_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.ctlz.v2i32")
+        },
+        "clzq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.ctlz.v16i8")
+        },
+        "clzq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.ctlz.v16i8")
+        },
+        "clzq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.ctlz.v8i16")
+        },
+        "clzq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.ctlz.v8i16")
+        },
+        "clzq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.ctlz.v4i32")
+        },
+        "clzq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.ctlz.v4i32")
+        },
+        "cls_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vcls.v8i8")
+        },
+        "cls_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vcls.v8i8")
+        },
+        "cls_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vcls.v4i16")
+        },
+        "cls_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vcls.v4i16")
+        },
+        "cls_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vcls.v2i32")
+        },
+        "cls_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vcls.v2i32")
+        },
+        "clsq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vcls.v16i8")
+        },
+        "clsq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vcls.v16i8")
+        },
+        "clsq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vcls.v8i16")
+        },
+        "clsq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vcls.v8i16")
+        },
+        "clsq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vcls.v4i32")
+        },
+        "clsq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vcls.v4i32")
+        },
+        "cnt_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.ctpop.v8i8")
+        },
+        "cnt_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.ctpop.v8i8")
+        },
+        "cntq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.ctpop.v16i8")
+        },
+        "cntq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.ctpop.v16i8")
+        },
+        "recpe_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vrecpe.v2i32")
+        },
+        "recpe_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vrecpe.v2f32")
+        },
+        "recpeq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vrecpe.v4i32")
+        },
+        "recpeq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.neon.vrecpe.v4f32")
+        },
+        "recps_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vfrecps.v2f32")
+        },
+        "recpsq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4), v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.neon.vfrecps.v4f32")
+        },
+        "sqrt_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.sqrt.v2f32")
+        },
+        "sqrtq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.sqrt.v4f32")
+        },
+        "rsqrte_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vrsqrte.v2i32")
+        },
+        "rsqrte_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vrsqrte.v2f32")
+        },
+        "rsqrteq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vrsqrte.v4i32")
+        },
+        "rsqrteq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.neon.vrsqrte.v4f32")
+        },
+        "rsqrts_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vrsqrts.v2f32")
+        },
+        "rsqrtsq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4), v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.neon.vrsqrts.v4f32")
+        },
+        "bsl_s8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vbsl.v8i8")
+        },
+        "bsl_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vbsl.v8i8")
+        },
+        "bsl_s16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vbsl.v4i16")
+        },
+        "bsl_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vbsl.v4i16")
+        },
+        "bsl_s32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vbsl.v2i32")
+        },
+        "bsl_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vbsl.v2i32")
+        },
+        "bsl_s64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(i(64), 1)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vbsl.v1i64")
+        },
+        "bsl_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(u(64), 1)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vbsl.v1i64")
+        },
+        "bslq_s8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vbsl.v16i8")
+        },
+        "bslq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vbsl.v16i8")
+        },
+        "bslq_s16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vbsl.v8i16")
+        },
+        "bslq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vbsl.v8i16")
+        },
+        "bslq_s32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vbsl.v4i32")
+        },
+        "bslq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vbsl.v4i32")
+        },
+        "bslq_s64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(i(64), 2)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vbsl.v2i64")
+        },
+        "bslq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(u(64), 2)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vbsl.v2i64")
+        },
+        "padd_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vpadd.v8i8")
+        },
+        "padd_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vpadd.v8i8")
+        },
+        "padd_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vpadd.v4i16")
+        },
+        "padd_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vpadd.v4i16")
+        },
+        "padd_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vpadd.v2i32")
+        },
+        "padd_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vpadd.v2i32")
+        },
+        "padd_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vpadd.v2f32")
+        },
+        "paddl_s16" => Intrinsic {
+            inputs: vec![v(i(8), 8)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vpaddls.v4i16.v8i8")
+        },
+        "paddl_u16" => Intrinsic {
+            inputs: vec![v(u(8), 8)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vpaddlu.v4i16.v8i8")
+        },
+        "paddl_s32" => Intrinsic {
+            inputs: vec![v(i(16), 4)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vpaddls.v2i32.v4i16")
+        },
+        "paddl_u32" => Intrinsic {
+            inputs: vec![v(u(16), 4)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vpaddlu.v2i32.v4i16")
+        },
+        "paddl_s64" => Intrinsic {
+            inputs: vec![v(i(32), 2)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vpaddls.v1i64.v2i32")
+        },
+        "paddl_u64" => Intrinsic {
+            inputs: vec![v(u(32), 2)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vpaddlu.v1i64.v2i32")
+        },
+        "paddlq_s16" => Intrinsic {
+            inputs: vec![v(i(8), 16)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vpaddls.v8i16.v16i8")
+        },
+        "paddlq_u16" => Intrinsic {
+            inputs: vec![v(u(8), 16)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vpaddlu.v8i16.v16i8")
+        },
+        "paddlq_s32" => Intrinsic {
+            inputs: vec![v(i(16), 8)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vpaddls.v4i32.v8i16")
+        },
+        "paddlq_u32" => Intrinsic {
+            inputs: vec![v(u(16), 8)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vpaddlu.v4i32.v8i16")
+        },
+        "paddlq_s64" => Intrinsic {
+            inputs: vec![v(i(32), 4)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vpaddls.v2i64.v4i32")
+        },
+        "paddlq_u64" => Intrinsic {
+            inputs: vec![v(u(32), 4)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vpaddlu.v2i64.v4i32")
+        },
+        "padal_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(8), 8)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vpadals.v4i16.v4i16")
+        },
+        "padal_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(8), 8)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vpadalu.v4i16.v4i16")
+        },
+        "padal_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(16), 4)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vpadals.v2i32.v2i32")
+        },
+        "padal_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(16), 4)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vpadalu.v2i32.v2i32")
+        },
+        "padal_s64" => Intrinsic {
+            inputs: vec![v(i(64), 1), v(i(32), 2)],
+            output: v(i(64), 1),
+            definition: Named("llvm.neon.vpadals.v1i64.v1i64")
+        },
+        "padal_u64" => Intrinsic {
+            inputs: vec![v(u(64), 1), v(u(32), 2)],
+            output: v(u(64), 1),
+            definition: Named("llvm.neon.vpadalu.v1i64.v1i64")
+        },
+        "padalq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(8), 16)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vpadals.v8i16.v8i16")
+        },
+        "padalq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(8), 16)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vpadalu.v8i16.v8i16")
+        },
+        "padalq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(16), 8)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vpadals.v4i32.v4i32")
+        },
+        "padalq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(16), 8)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vpadalu.v4i32.v4i32")
+        },
+        "padalq_s64" => Intrinsic {
+            inputs: vec![v(i(64), 2), v(i(32), 4)],
+            output: v(i(64), 2),
+            definition: Named("llvm.neon.vpadals.v2i64.v2i64")
+        },
+        "padalq_u64" => Intrinsic {
+            inputs: vec![v(u(64), 2), v(u(32), 4)],
+            output: v(u(64), 2),
+            definition: Named("llvm.neon.vpadalu.v2i64.v2i64")
+        },
+        "pmax_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vpmaxs.v8i8")
+        },
+        "pmax_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vpmaxu.v8i8")
+        },
+        "pmax_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vpmaxs.v4i16")
+        },
+        "pmax_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vpmaxu.v4i16")
+        },
+        "pmax_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vpmaxs.v2i32")
+        },
+        "pmax_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vpmaxu.v2i32")
+        },
+        "pmax_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vpmaxf.v2f32")
+        },
+        "pmin_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vpmins.v8i8")
+        },
+        "pmin_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vpminu.v8i8")
+        },
+        "pmin_s16" => Intrinsic {
+            inputs: vec![v(i(16), 4), v(i(16), 4)],
+            output: v(i(16), 4),
+            definition: Named("llvm.neon.vpmins.v4i16")
+        },
+        "pmin_u16" => Intrinsic {
+            inputs: vec![v(u(16), 4), v(u(16), 4)],
+            output: v(u(16), 4),
+            definition: Named("llvm.neon.vpminu.v4i16")
+        },
+        "pmin_s32" => Intrinsic {
+            inputs: vec![v(i(32), 2), v(i(32), 2)],
+            output: v(i(32), 2),
+            definition: Named("llvm.neon.vpmins.v2i32")
+        },
+        "pmin_u32" => Intrinsic {
+            inputs: vec![v(u(32), 2), v(u(32), 2)],
+            output: v(u(32), 2),
+            definition: Named("llvm.neon.vpminu.v2i32")
+        },
+        "pmin_f32" => Intrinsic {
+            inputs: vec![v(f(32), 2), v(f(32), 2)],
+            output: v(f(32), 2),
+            definition: Named("llvm.neon.vpminf.v2f32")
+        },
+        "pminq_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(i(8), 16)],
+            output: v(i(8), 16),
+            definition: Named("llvm.neon.vpmins.v16i8")
+        },
+        "pminq_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 16)],
+            output: v(u(8), 16),
+            definition: Named("llvm.neon.vpminu.v16i8")
+        },
+        "pminq_s16" => Intrinsic {
+            inputs: vec![v(i(16), 8), v(i(16), 8)],
+            output: v(i(16), 8),
+            definition: Named("llvm.neon.vpmins.v8i16")
+        },
+        "pminq_u16" => Intrinsic {
+            inputs: vec![v(u(16), 8), v(u(16), 8)],
+            output: v(u(16), 8),
+            definition: Named("llvm.neon.vpminu.v8i16")
+        },
+        "pminq_s32" => Intrinsic {
+            inputs: vec![v(i(32), 4), v(i(32), 4)],
+            output: v(i(32), 4),
+            definition: Named("llvm.neon.vpmins.v4i32")
+        },
+        "pminq_u32" => Intrinsic {
+            inputs: vec![v(u(32), 4), v(u(32), 4)],
+            output: v(u(32), 4),
+            definition: Named("llvm.neon.vpminu.v4i32")
+        },
+        "pminq_f32" => Intrinsic {
+            inputs: vec![v(f(32), 4), v(f(32), 4)],
+            output: v(f(32), 4),
+            definition: Named("llvm.neon.vpminf.v4f32")
+        },
+        "qtbl1_s8" => Intrinsic {
+            inputs: vec![v(i(8), 16), v(u(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vtbl1")
+        },
+        "qtbl1_u8" => Intrinsic {
+            inputs: vec![v(u(8), 16), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vtbl1")
+        },
+        "qtbx1_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), v(i(8), 8), v(u(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vtbx1")
+        },
+        "qtbx1_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), v(u(8), 8), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vtbx1")
+        },
+        "qtbl2_s8" => Intrinsic {
+            inputs: vec![agg(true, vec![v(i(8), 8), v(i(8), 8)]), v(u(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vtbl2")
+        },
+        "qtbl2_u8" => Intrinsic {
+            inputs: vec![agg(true, vec![v(u(8), 8), v(u(8), 8)]), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vtbl2")
+        },
+        "qtbx2_s8" => Intrinsic {
+            inputs: vec![agg(true, vec![v(i(8), 8), v(i(8), 8)]), v(u(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vtbx2")
+        },
+        "qtbx2_u8" => Intrinsic {
+            inputs: vec![agg(true, vec![v(u(8), 8), v(u(8), 8)]), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vtbx2")
+        },
+        "qtbl3_s8" => Intrinsic {
+            inputs: vec![agg(true, vec![v(i(8), 8), v(i(8), 8), v(i(8), 8)]), v(u(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vtbl3")
+        },
+        "qtbl3_u8" => Intrinsic {
+            inputs: vec![agg(true, vec![v(u(8), 8), v(u(8), 8), v(u(8), 8)]), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vtbl3")
+        },
+        "qtbx3_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), agg(true, vec![v(i(8), 8), v(i(8), 8), v(i(8), 8)]), v(u(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vtbx3")
+        },
+        "qtbx3_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), agg(true, vec![v(u(8), 8), v(u(8), 8), v(u(8), 8)]), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vtbx3")
+        },
+        "qtbl4_s8" => Intrinsic {
+            inputs: vec![agg(true, vec![v(i(8), 8), v(i(8), 8), v(i(8), 8), v(i(8), 8)]), v(u(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vtbl4")
+        },
+        "qtbl4_u8" => Intrinsic {
+            inputs: vec![agg(true, vec![v(u(8), 8), v(u(8), 8), v(u(8), 8), v(u(8), 8)]), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vtbl4")
+        },
+        "qtbx4_s8" => Intrinsic {
+            inputs: vec![v(i(8), 8), agg(true, vec![v(i(8), 8), v(i(8), 8), v(i(8), 8), v(i(8), 8)]), v(u(8), 8)],
+            output: v(i(8), 8),
+            definition: Named("llvm.neon.vtbx4")
+        },
+        "qtbx4_u8" => Intrinsic {
+            inputs: vec![v(u(8), 8), agg(true, vec![v(u(8), 8), v(u(8), 8), v(u(8), 8), v(u(8), 8)]), v(u(8), 8)],
+            output: v(u(8), 8),
+            definition: Named("llvm.neon.vtbx4")
+        },
         _ => return None,
     })
 }