]> git.lizzy.rs Git - micro.git/commit
add system verilog syntax file
authorZachary Yedidia <zyedidia@gmail.com>
Mon, 30 Dec 2019 19:05:06 +0000 (14:05 -0500)
committerZachary Yedidia <zyedidia@gmail.com>
Mon, 30 Dec 2019 19:05:06 +0000 (14:05 -0500)
commitf8743775730d89ab5de097b352719872edfe8025
tree89073033841dad91276c8acc18deb1083df79f99
parentce868faeced6385855cf89c561a1abe39184e762
add system verilog syntax file
runtime/syntax/verilog.yaml [new file with mode: 0644]