truetypefs: fall back to width if advance is zero

[plan9front.git] / sys / src / 9 / zynq / timer.c

diff --git a/sys/src/9/zynq/timer.c b/sys/src/9/zynq/timer.c
index 42211446c1dcbccb34b6e8fc311206770a6ef579..4edd2962d18fad339629980f156c1069aa75baa2 100644 (file)
--- a/sys/src/9/zynq/timer.c
+++ b/sys/src/9/zynq/timer.c
@@ -23,13 +23,19 @@ enum {
 uvlong timerhz;
 
 void
-delay(int)
+microdelay(int n)
 {
+       ulong now;
+
+       now = µs();
+       while(µs() - now < n);
 }
 
 void
-microdelay(int)
+delay(int n)
 {
+       while(--n >= 0)
+               microdelay(1000);
 }
 
 uvlong
@@ -49,8 +55,7 @@ fastticks(uvlong *hz)
 ulong
 µs(void)
 {
-       NOPE
-       return 0;
+       return fastticks2us(fastticks(nil));
 }
 
 void
@@ -80,12 +85,39 @@ timerirq(Ureg *u, void *)
 void
 timerinit(void)
 {
-       int mhz;
-       
-       mhz = PS_CLK * (slcr[ARM_PLL_CTRL] >> 12 & 0x7f) / (slcr[ARM_CLK_CTRL] >> 8 & 0x3f);
-       timerhz = mhz * 500000;
+       m->cpumhz = PS_CLK * (slcr[ARM_PLL_CTRL] >> 12 & 0x7f) / (slcr[ARM_CLK_CTRL] >> 8 & 0x3f);
+       m->cpuhz = m->cpumhz * 1000000;
+       timerhz = m->cpuhz / 2;
        mpcore[GTIMERCTL] = TIMERDIV - 1 << 8 | 3;
        mpcore[LTIMERCTL] = LTIMERDIV - 1 << 8 | 4;
        intrenable(TIMERIRQ, timerirq, nil, EDGE, "clock");
+
+       /* enable and reset cycle counter register */
+       m->cyclefreq = m->cpuhz;
+       setpmcnten((1<<31));
+       coherence();
+       setpmcr(7);
+}
+
+/*
+ * synchronize all cpu's cycle counter registers
+ */
+void
+synccycles(void)
+{
+       static Ref r1, r2;
+       int s;
+
+       s = splhi();
+       r2.ref = 0;
+       incref(&r1);
+       while(r1.ref != conf.nmach)
+               ;
        setpmcr(7);
+       m->cycleshi = MACHP(0)->cycleshi;
+       incref(&r2);
+       while(r2.ref != conf.nmach)
+               ;
+       r1.ref = 0;
+       splx(s);
 }