int i;
va_list arg;
- if(!(DEBUG & DbgPROBE))
+ if(!(DEBUG & DbgPROBE)){
+ USED(cmdport);
+ USED(ctlport);
+ USED(fmt);
return;
+ }
p = buf;
e = buf + sizeof buf;
atapktio0(Drive *drive, SDreq *r)
{
uchar *cmd;
- int as, cmdport, ctlport, len, rv;
+ int as, len, cmdport, ctlport, rv;
Ctlr *ctlr;
rv = SDok;
return SDnostatus;
ilock(ctlr);
- if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen)){
+ if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen))
drive->pktdma = Dma;
- len = 0; /* bytecount should be 0 for dma */
- }else{
+ else
drive->pktdma = 0;
- if(drive->secsize)
- len = 16*drive->secsize;
- else
- len = 0x8000;
- }
+ len = drive->secsize > 0 ? 16*drive->secsize : 0x8000;
outb(cmdport+Features, drive->pktdma);
outb(cmdport+Count, 0);
outb(cmdport+Sector, 0);
atadmastart(ctlr, drive->write);
iunlock(ctlr);
- if(iowait(drive, 30*1000, 0) <= 0){
- ilock(ctlr);
+ while(iowait(drive, 30*1000, 1) == 0)
+ ;
+
+ ilock(ctlr);
+ if(!ctlr->done){
+ rv = SDcheck;
ataabort(drive, 0);
- } else
- ilock(ctlr);
+ }
if(drive->error){
if(drive->pktdma)
atadmastop(ctlr);
}
iunlock(ctlr);
- if(drive->status & Chk){
+ if(rv != SDcheck && drive->status & Chk){
rv = SDcheck;
if(drive->pktdma){
print("atapktio: disabling dma\n");
drive->dmactl = 0;
- rv = SDretry;
}
}
return rv;
SDunit *unit;
unit = r->unit;
- if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil){
- r->status = SDtimeout;
- return SDtimeout;
- }
+ if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
+ return r->status = SDtimeout;
drive = ctlr->drive[unit->subno];
qlock(drive);
for(;;){
case (0x4D69<<16)|0x105A: /* Promise Ultra/133 TX2 */
case (0x3373<<16)|0x105A: /* Promise 20378 RAID */
case (0x3149<<16)|0x1106: /* VIA VT8237 SATA/RAID */
+ case (0x0415<<16)|0x1106: /* VIA VT6415 PATA IDE */
case (0x3112<<16)|0x1095: /* SiL 3112 SATA/RAID */
maxio = 15;
span = 8*1024;
*/
break;
case (0x7441<<16)|0x1022: /* AMD 768 */
- case (0x7800<<16)|0x1022:
/*
* Set:
* 0x41 prefetch, postwrite;
case (0x7111<<16)|0x8086: /* 82371[AE]B (PIIX4[E]) */
maxdma = 0x20000;
break;
+ case (0x1c00<<16)|0x8086: /* SERIES6 SATA */
+ case (0x1c01<<16)|0x8086: /* SERIES6 SATA */
+ case (0x1c08<<16)|0x8086: /* SERIES6 SATA */
+ case (0x1c09<<16)|0x8086: /* SERIES6 SATA */
case (0x2411<<16)|0x8086: /* 82801AA (ICH) */
case (0x2421<<16)|0x8086: /* 82801AB (ICH0) */
case (0x244A<<16)|0x8086: /* 82801BA (ICH2, Mobile) */
case (0x27C5<<16)|0x8086: /* 82801GBM SATA AHCI (ICH7) */
case (0x2850<<16)|0x8086: /* 82801HBM/HEM PATA */
case (0x2820<<16)|0x8086: /* 82801HB/HR/HH/HO SATA IDE */
+ case (0x2825<<16)|0x8086: /* 82801IIH Intel Q35 IDE */
case (0x2828<<16)|0x8086: /* 82801HBM SATA (ICH8-M) */
case (0x2829<<16)|0x8086: /* 82801HBM SATA AHCI (ICH8-M) */
case (0x2920<<16)|0x8086: /* 82801(IB)/IR/IH/IO SATA (ICH9) port 0-3 */
map |= 2;
irqack = ichirqack;
break;
+ case (0x811a<<16)|0x8086: /* Intel SCH (Poulsbo) */
+ map = 1;
+ irqack = ichirqack;
+ break;
}
for(channel = 0; channel < 2; channel++){
if((map & 1<<channel) == 0)
ctlr->maxdma = maxdma;
ctlr->span = span;
ctlr->irqack = irqack;
- if(pi & 0x80)
+ if((pi & 0x80) && (p->mem[4].bar & 0x01))
ctlr->bmiba = (p->mem[4].bar & ~0x01) + channel*8;
if(head != nil)
tail->next = sdev;
atadmaclr(ctlr);
if(ctlr->pcidev != nil)
pcisetbme(ctlr->pcidev);
- ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 4, 0, 64*1024);
+ /* Intel SCH requires 8 byte alignment, though datasheet says 4 m( */
+ ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 8, 0, 64*1024);
}
snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
intrenable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
if(drive->pkt == 0 && (drive->feat & Dlba) == 0)
p = seprint(p, e, " %d %d %d", drive->c, drive->h, drive->s);
p = seprint(p, e, "\n");
+ p = seprint(p, e, "alignment %d %d\n",
+ drive->secsize<<drive->physshift, drive->physalign);
}
p = seprint(p, e, "missirq %ud\n", drive->missirq);
p = seprint(p, e, "sloop %ud\n", drive->spurloop);