merge

[plan9front.git] / sys / src / 9 / pc / ethervt6102.c

diff --git a/sys/src/9/pc/ethervt6102.c b/sys/src/9/pc/ethervt6102.c
index b76d3be8baad0961aa5aa19cae61157565291c5b..9ea47f1aee7d3140a288af1f5e98d42c26956a63 100644 (file)
--- a/sys/src/9/pc/ethervt6102.c
+++ b/sys/src/9/pc/ethervt6102.c
@@ -15,6 +15,7 @@
 #include "dat.h"
 #include "fns.h"
 #include "io.h"
+#include "../port/pci.h"
 #include "../port/error.h"
 #include "../port/netif.h"
 #include "../port/etherif.h"
@@ -947,7 +948,7 @@ vt6102pci(void)
 {
        Pcidev *p;
        Ctlr *ctlr;
-       int cls, port;
+       int port;
 
        p = nil;
        while(p = pcimatch(p, 0, 0)){
@@ -962,7 +963,7 @@ vt6102pci(void)
                        break;
                }
 
-               port = p->mem[0].bar & ~0x01;
+               port = p->mem[0].bar & ~3;
                if(ioalloc(port, p->mem[0].size, 0, "vt6102") < 0){
                        print("vt6102: port 0x%uX in use\n", port);
                        continue;
@@ -977,9 +978,7 @@ vt6102pci(void)
                ctlr->pcidev = p;
                pcienable(p);
                ctlr->id = (p->did<<16)|p->vid;
-               if((cls = pcicfgr8(p, PciCLS)) == 0 || cls == 0xFF)
-                       cls = 0x10;
-               ctlr->cls = cls*4;
+               ctlr->cls = p->cls*4;
                ctlr->tft = Ctft64;
 
                if(vt6102reset(ctlr)){