#include "dat.h"
#include "fns.h"
#include "io.h"
+#include "../port/pci.h"
#include "../port/error.h"
#include "../port/netif.h"
#include "../port/etherif.h"
typedef struct Ctlr Ctlr;
struct Ctlr {
- int port;
+ uvlong port;
Pcidev* pcidev;
Ctlr* next;
int active;
* 3rd arg of 1 selects gigabit only; 2 10/100 only.
*/
ga620command(ctlr, 0x0B, 0x00, 0x00);
- print("#l%d: ga620: port %8.8uX: firmware is up\n",
+ print("#l%d: ga620: port %8.8lluX: firmware is up\n",
edev->ctlrno, ctlr->port);
break;
case 0x04: /* statistics updated */
if(!(rbd->flags & Ferror) && len != 0){
bp = rbd->opaque;
bp->wp = bp->rp+len;
- etheriq(edev, bp, 1);
+ etheriq(edev, bp);
}
else
freeb(rbd->opaque);
static int
ga620reset(Ctlr* ctlr)
{
- int cls, csr, i, r;
+ int csr, i, r;
if(ga620detach(ctlr) < 0)
return -1;
csr = csr32r(ctlr, Ps) & (PCI32|PCI66);
csr |= PCIwcmd|PCIrcmd|PCImrm;
if(ctlr->pcidev->pcr & 0x0010){
- cls = pcicfgr8(ctlr->pcidev, PciCLS) * 4;
- if(cls != 32)
- pcicfgw8(ctlr->pcidev, PciCLS, 32/4);
+ if(ctlr->pcidev->cls != 32/4){
+ ctlr->pcidev->cls = 32/4;
+ pcicfgw8(ctlr->pcidev, PciCLS, ctlr->pcidev->cls);
+ }
csr |= PCIwm32;
}
csr32w(ctlr, Ps, csr);
while(p = pcimatch(p, 0, 0)){
if(p->ccrb != 0x02 || p->ccru != 0)
continue;
+ if(p->mem[0].bar & 1)
+ continue;
switch(p->did<<16 | p->vid){
default:
break;
}
- mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
- if(mem == 0){
- print("ga620: can't map %8.8luX\n", p->mem[0].bar);
+ mem = vmap(p->mem[0].bar & ~0xF, p->mem[0].size);
+ if(mem == nil){
+ print("ga620: can't map %llux\n", p->mem[0].bar & ~0xF);
continue;
}
print("ga620: can't allocate memory\n");
continue;
}
- ctlr->port = p->mem[0].bar & ~0x0F;
+ ctlr->port = p->mem[0].bar & ~0xF;
ctlr->pcidev = p;
+ pcienable(p);
+
ctlr->id = p->did<<16 | p->vid;
ctlr->nic = mem;
free(ctlr);
continue;
}
+ pcisetbme(p);
if(ctlrhead != nil)
ctlrtail->next = ctlr;