#include "dat.h"
#include "fns.h"
#include "io.h"
+#include "../port/pci.h"
#include "../port/error.h"
#include "../port/netif.h"
-
-#include "etherif.h"
-#include "ethermii.h"
+#include "../port/etherif.h"
+#include "../port/ethermii.h"
enum { /* Registers */
Cr = 0x00, /* Command */
typedef struct Ctlr Ctlr;
typedef struct Ctlr {
- int port;
+ uvlong port;
Pcidev* pcidev;
Ctlr* next;
int active;
bp = desc->bp;
desc->bp = nil;
bp->wp += cmdsts & SizeMASK;
- etheriq(edev, bp, 1);
+ etheriq(edev, bp);
}
else if(0 && !(cmdsts & Ok)){
iprint("dp83820: rx %8.8uX:", cmdsts);
while(p = pcimatch(p, 0, 0)){
if(p->ccrb != Pcibcnet || p->ccru != Pciscether)
continue;
+ if(p->mem[1].bar & 1)
+ continue;
switch((p->did<<16)|p->vid){
default:
break;
}
- mem = vmap(p->mem[1].bar & ~0x0F, p->mem[1].size);
- if(mem == 0){
- print("DP83820: can't map %8.8luX\n", p->mem[1].bar);
+ mem = vmap(p->mem[1].bar & ~0xF, p->mem[1].size);
+ if(mem == nil){
+ print("DP83820: can't map %llux\n", p->mem[1].bar & ~0xF);
continue;
}
print("DP83820: can't allocate memory\n");
continue;
}
- ctlr->port = p->mem[1].bar & ~0x0F;
+ ctlr->port = p->mem[1].bar & ~0xF;
ctlr->pcidev = p;
+ pcienable(p);
ctlr->id = (p->did<<16)|p->vid;
ctlr->nic = mem;
edev->attach = dp83820attach;
edev->transmit = dp83820transmit;
- edev->interrupt = dp83820interrupt;
edev->ifstat = dp83820ifstat;
edev->arg = edev;
edev->multicast = dp83820multicast;
edev->shutdown = dp83820shutdown;
+ intrenable(edev->irq, dp83820interrupt, edev, edev->tbdf, edev->name);
+
return 0;
}