]> git.lizzy.rs Git - plan9front.git/blobdiff - sys/src/9/pc/ether8169.c
kernel: cleanup makefile for $CONF.$O target
[plan9front.git] / sys / src / 9 / pc / ether8169.c
index 0fe6bc578d3312491ac9fcc89d557258a0aff72a..bf6cf8ef48f5f90a37fa33f150a810653c6658b3 100644 (file)
@@ -16,8 +16,7 @@
 #include "../port/error.h"
 #include "../port/netif.h"
 #include "../port/etherif.h"
-
-#include "ethermii.h"
+#include "../port/ethermii.h"
 
 enum {                                 /* registers */
        Idr0            = 0x00,         /* MAC address */
@@ -725,7 +724,15 @@ rtl8169init(Ether* edev)
 
        csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
        ctlr->tcr = csr32r(ctlr, Tcr);
-       ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
+       switch(ctlr->macv){
+       case Macv42:
+       case Macv45:
+               ctlr->rcr = Rxfth256|Mrxdmaunlimited|Ab|Am|Apm;
+               break;
+       default:
+               ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
+               break;
+       }
        ctlr->mchash = 0;
        csr32w(ctlr, Mar0,   0);
        csr32w(ctlr, Mar0+4, 0);
@@ -970,7 +977,7 @@ rtl8169receive(Ether* edev)
                                bp->flag |= Bipck;
                                break;
                        }
-                       etheriq(edev, bp, 1);
+                       etheriq(edev, bp);
                }else{
                        if(!(control & Res))
                                ctlr->frag++;
@@ -1111,25 +1118,17 @@ rtl8169pci(void)
                ctlr->pciv = i;
                ctlr->pcie = pcie;
 
+               pcienable(p);
                if(vetmacv(ctlr, &macv) == -1){
+                       pcidisable(p);
                        iofree(port);
                        free(ctlr);
                        print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
                        continue;
                }
 
-               if(pcigetpms(p) > 0){
-                       pcisetpms(p, 0);
-
-                       for(i = 0; i < 6; i++)
-                               pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
-                       pcicfgw8(p, PciINTL, p->intl);
-                       pcicfgw8(p, PciLTR, p->ltr);
-                       pcicfgw8(p, PciCLS, p->cls);
-                       pcicfgw16(p, PciPCR, p->pcr);
-               }
-
                if(rtl8169reset(ctlr)){
+                       pcidisable(p);
                        iofree(port);
                        free(ctlr);
                        print("rtl8169: reset failed\n");