kernel: avoid palloc lock during mmurelease()

[plan9front.git] / sys / src / 9 / omap / mmu.c

diff --git a/sys/src/9/omap/mmu.c b/sys/src/9/omap/mmu.c
old mode 100755 (executable)
new mode 100644 (file)
index 05b4dc3..12383c9
--- a/sys/src/9/omap/mmu.c
+++ b/sys/src/9/omap/mmu.c
@@ -138,7 +138,7 @@ mmul2empty(Proc* proc, int clear)
        l2 = &proc->mmul2;
        for(page = *l2; page != nil; page = page->next){
                if(clear)
-                       memset(UINT2PTR(page->va), 0, BY2PG);
+                       memset((void*)page->va, 0, BY2PG);
                l1[page->daddr] = Fault;
                l2 = &page->next;
        }
@@ -234,20 +234,12 @@ flushmmu(void)
 void
 mmurelease(Proc* proc)
 {
-       Page *page, *next;
-
        /* write back dirty and invalidate l1 caches */
        cacheuwbinv();
 
        mmul2empty(proc, 0);
-       for(page = proc->mmul2cache; page != nil; page = next){
-               next = page->next;
-               if(--page->ref)
-                       panic("mmurelease: page->ref %d", page->ref);
-               pagechainhead(page);
-       }
-       if(proc->mmul2cache && palloc.r.p)
-               wakeup(&palloc.r);
+
+       freepages(proc->mmul2cache, nil, 0);
        proc->mmul2cache = nil;
 
        mmul1empty();
@@ -282,7 +274,7 @@ putmmu(uintptr va, uintptr pa, Page* page)
                else{
                        pg = up->mmul2cache;
                        up->mmul2cache = pg->next;
-                       memset(UINT2PTR(pg->va), 0, BY2PG);
+                       memset((void*)pg->va, 0, BY2PG);
                }
                pg->daddr = x;
                pg->next = up->mmul2;
@@ -302,7 +294,7 @@ putmmu(uintptr va, uintptr pa, Page* page)
                                m->mmul1hi = x;
                }
        }
-       pte = UINT2PTR(KADDR(PPN(*l1)));
+       pte = KADDR(PPN(*l1));
        //print("pte %#p index %ld was %#ux\n", pte, L2X(va), *(pte+L2X(va)));
 
        /* protection bits are
@@ -330,10 +322,9 @@ putmmu(uintptr va, uintptr pa, Page* page)
         *  rather than direct mapped.
         */
        cachedwbinv();
-       if(page->cachectl[0] == PG_TXTFLUSH){
-               /* pio() sets PG_TXTFLUSH whenever a text pg has been written */
+       if(page->txtflush){
                cacheiinv();
-               page->cachectl[0] = PG_NOFLUSH;
+               page->txtflush = 0;
        }
        //print("putmmu %#p %#p %#p\n", va, pa, PPN(pa)|x);
 }
@@ -350,7 +341,7 @@ mmuuncache(void* v, usize size)
         * Uncache a Section, must already be
         * valid in the MMU.
         */
-       va = PTR2UINT(v);
+       va = (uintptr)v;
        assert(!(va & (1*MiB-1)) && size == 1*MiB);
 
        x = L1X(va);
@@ -434,13 +425,13 @@ vmap(uintptr pa, usize size)
         * will fail.
         */
        if(pa+size < 4*MiB)
-               return UINT2PTR(kseg0|pa);
+               return (void*)(kseg0|pa);
 
        osize = size;
        o = pa & (BY2PG-1);
        pa -= o;
        size += o;
-       size = ROUNDUP(size, BY2PG);
+       size = PGROUND(size);
 
        va = kseg0|pa;
        pae = mmukmap(va, pa, size);
@@ -448,7 +439,7 @@ vmap(uintptr pa, usize size)
                panic("vmap(%#p, %ld) called from %#p: mmukmap fails %#p",
                        pa+o, osize, getcallerpc(&pa), pae);
 
-       return UINT2PTR(va+o);
+       return (void*)(va+o);
 }
 
 /* from 386 */