* rather than direct mapped.
*/
cachedwbinv();
- if(page->cachectl[0] == PG_TXTFLUSH){
- /* pio() sets PG_TXTFLUSH whenever a text pg has been written */
+ if(page->txtflush){
cacheiinv();
- page->cachectl[0] = PG_NOFLUSH;
+ page->txtflush = 0;
}
checkmmu(va, PPN(pa));
}
*pte++ = (pa+n)|Dom0|L1AP(Krw)|Section;
mmuinvalidateaddr(va+n);
}
- cachedwbse(pte0, pte - pte0);
+ cachedwbse(pte0, (uintptr)pte - (uintptr)pte0);
return va + o;
}