merge

[plan9front.git] / sys / src / 9 / bcm / irq.c

diff --git a/sys/src/9/bcm/irq.c b/sys/src/9/bcm/irq.c
index f93dcd38c82e46d84b1b4b82726d980f610b46b1..e960d8c5c4214ad04df5260f2eb1bd7cd89a9681 100644 (file)
--- a/sys/src/9/bcm/irq.c
+++ b/sys/src/9/bcm/irq.c
@@ -83,6 +83,7 @@ irq(Ureg* ureg)
        Vctl *v;
        int clockintr;
 
+       m->intr++;
        clockintr = 0;
        for(v = vctl[m->machno]; v != nil; v = v->next)
                if((*v->reg & v->mask) != 0){
@@ -103,18 +104,17 @@ fiq(Ureg *ureg)
 {
        Vctl *v;
 
+       m->intr++;
        v = vfiq;
-       if(v == nil)
+       if(v == nil || m->machno)
                panic("cpu%d: unexpected item in bagging area", m->machno);
-       m->intr++;
-       ureg->pc -= 4;
        coherence();
        v->f(ureg, v->a);
        coherence();
 }
 
 void
-irqenable(int irq, void (*f)(Ureg*, void*), void* a)
+intrenable(int irq, void (*f)(Ureg*, void*), void* a, int, char*)
 {
        Vctl *v;
        Intregs *ip;
@@ -149,6 +149,7 @@ irqenable(int irq, void (*f)(Ureg*, void*), void* a)
        if(irq == IRQfiq){
                assert((ip->FIQctl & Fiqenable) == 0);
                assert((*enable & v->mask) == 0);
+               assert(cpu == 0);
                vfiq = v;
                ip->FIQctl = Fiqenable | irq;
        }else{
@@ -164,3 +165,8 @@ irqenable(int irq, void (*f)(Ureg*, void*), void* a)
        }
        unlock(&vctllock);
 }
+
+void
+intrdisable(int, void (*)(Ureg*, void*), void*, int, char*)
+{
+}