MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
BARRIERS
+ /*
+ * turn SMP off
+ */
+ MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
+ BIC $CpACsmp, R1
+ MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
+ BARRIERS
+
/*
* clear mach and page tables
*/
MOVW $PADDR(MACHADDR), R1
MOVW $PADDR(KTZERO), R2
+ MOVW $0, R0
_ramZ:
MOVW R0, (R1)
ADD $4, R1
CMP R1, R2
- BNE _ramZ
-
- /*
- * turn SMP on
- * invalidate tlb
- */
- MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
- ORR $CpACsmp, R1 /* turn SMP on */
- MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
- BARRIERS
- MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
- BARRIERS
+ BNE _ramZ
/*
* start stack at top of mach (physical addr)
* set up page tables for kernel
*/
MOVW $PADDR(MACHADDR+MACHSIZE-4), R13
+
MOVW $PADDR(L1), R0
BL mmuinit(SB)
+ BL mmuinvalidate(SB)
/*
* set up domain access control and page table base
BARRIERS
/*
- * enable caches, mmu, and high vectors
+ * turn SMP on
*/
+ MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
+ ORR $CpACsmp, R1
+ MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
+ BARRIERS
+ /*
+ * enable caches, mmu, and high vectors
+ */
MRC CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
ORR $(CpChv|CpCdcache|CpCicache|CpCmmu), R0
MCR CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
reset:
/*
* load physical base for SB addressing while mmu is off
- * keep a handy zero in R0 until first function call
*/
MOVW $setR12(SB), R12
SUB $KZERO, R12
ADD $PHYSDRAM, R12
- MOVW $0, R0
/*
* SVC mode, interrupts disabled
BARRIERS
/*
- * turn SMP on
- * invalidate tlb
+ * turn SMP off
*/
MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
- ORR $CpACsmp, R1 /* turn SMP on */
+ BIC $CpACsmp, R1
MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
BARRIERS
- MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
- BARRIERS
/*
* find Mach for this cpu
AND $(MAXMACH-1), R2 /* mask out non-cpu-id bits */
SLL $2, R2 /* convert to word index */
MOVW $machaddr(SB), R0
+ BIC $KSEGM, R0
+ ORR $PHYSDRAM, R0
ADD R2, R0 /* R0 = &machaddr[cpuid] */
MOVW (R0), R0 /* R0 = machaddr[cpuid] */
CMP $0, R0
*/
ADD $(MACHSIZE-4), R(MACH), R13
+ BL mmuinvalidate(SB)
+
/*
* set up domain access control and page table base
*/
BL cacheiinv(SB)
BARRIERS
+ /*
+ * turn SMP on
+ */
+ MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
+ ORR $CpACsmp, R1
+ MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
+ BARRIERS
+
/*
* enable caches, mmu, and high vectors
*/