.I 5e
simulates the execution of an ARM binary in a Plan 9 environment.
Unlike its predecessor
-.IR 5i (1)
+.IR vi (1)
it supports, among others, the syscalls
-.IR rfork (2)
+rfork (see
+.IR fork (2))
and
.IR exec (2),
which allows for the execution of threaded programs (e.g.,
.BR /rc/bin .
.PP
Unlike
-.IR 5i (1),
+.IR vi (1),
.IR 5e (1)
does not provide built-in debugging facilities.
It
causes failing processes to call
.IR abort (2)
instead of
-.IR sysfatal (2).
+.I sysfatal.
See below.
.SH SOURCE
.B /sys/src/cmd/5e
.SH SEE ALSO
-.IR 5i (1)
+.IR vi (1)
.SH BUGS
The host is required to be little endian and is assumed to have a floating point implementation conforming to IEEE 754.
.B LDREX
and
.B STREX
-instructions can lead to deadlock, while a real processor will exhibit undefined behavior in these cases.
+instructions can lead to deadlock, while the
+.I ARM Architecture Reference Manual
+indicates a real processor will exhibit undefined behavior in these cases.
Accesses spanning segment boundaries will be treated as page faults.
Many syscalls such as
.I text
argument should behave more like it would if it had been entered as an argument to
.IR rc (1).
+.SH HISTORY
+.I 5e
+first appeared in 9front (June, 2011).