Merge branch 'python-highlight-zero' of https://github.com/a11ce/micro into a11ce...

[micro.git] / runtime / syntax / verilog.yaml

diff --git a/runtime/syntax/verilog.yaml b/runtime/syntax/verilog.yaml
index 97c4184708b043a6f13791927f2ce208cd83747c..d6de7530984fe22ed82a3941cc86621e107e21a6 100644 (file)
--- a/runtime/syntax/verilog.yaml
+++ b/runtime/syntax/verilog.yaml
@@ -1,7 +1,7 @@
 filetype: verilog
 
 detect:
-    filename: "\\.(vh|sv|svh)$"
+    filename: "\\.(v|vh|sv|svh)$"
 
 rules:
     - preproc: "\\b(module|package|program|endmodule|endpackage|endprogram)\\b"