Rollup merge of #63230 - tmandry:disallow-possibly-uninitialized, r=Centril

[rust.git] / config.toml.example

diff --git a/config.toml.example b/config.toml.example
index c14adf8ce33c7f276332bc9d0b8685c7fdf219b8..6816eaeaa9486e66e99465094a1c4dce76e2a5ab 100644 (file)
--- a/config.toml.example
+++ b/config.toml.example
@@ -57,14 +57,13 @@
 # support. You'll need to write a target specification at least, and most
 # likely, teach rustc about the C ABI of the target. Get in touch with the
 # Rust team and file an issue if you need assistance in porting!
-#targets = "X86;ARM;AArch64;Mips;PowerPC;SystemZ;MSP430;Sparc;NVPTX;Hexagon"
+#targets = "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86"
 
 # LLVM experimental targets to build support for. These targets are specified in
 # the same format as above, but since these targets are experimental, they are
 # not built by default and the experimental Rust compilation targets that depend
-# on them will not work unless the user opts in to building them. By default the
-# `WebAssembly` and `RISCV` targets are enabled when compiling LLVM from scratch.
-#experimental-targets = "WebAssembly;RISCV"
+# on them will not work unless the user opts in to building them.
+#experimental-targets = ""
 
 # Cap the number of parallel linker invocations when compiling LLVM.
 # This can be useful when building LLVM with debug info, which significantly