- // MIR for `g` before Inline
+ // MIR for `g` after Inline
  
  fn g(_1: i32) -> u32 {
      debug i => _1;                       // in scope 0 at $DIR/inline-diverging.rs:12:10: 12:11
      let mut _0: u32;                     // return place in scope 0 at $DIR/inline-diverging.rs:12:21: 12:24
      let mut _2: bool;                    // in scope 0 at $DIR/inline-diverging.rs:13:8: 13:13
      let mut _3: i32;                     // in scope 0 at $DIR/inline-diverging.rs:13:8: 13:9
      let mut _4: i32;                     // in scope 0 at $DIR/inline-diverging.rs:14:9: 14:10
      let mut _5: !;                       // in scope 0 at $DIR/inline-diverging.rs:15:12: 17:6
      let _6: !;                           // in scope 0 at $DIR/inline-diverging.rs:16:9: 16:16
+     scope 1 (inlined panic) {            // at $DIR/inline-diverging.rs:16:9: 16:16
+         let mut _7: !;                   // in scope 1 at $SRC_DIR/std/src/panic.rs:LL:COL
+     }
  
      bb0: {
          StorageLive(_2);                 // scope 0 at $DIR/inline-diverging.rs:13:8: 13:13
          StorageLive(_3);                 // scope 0 at $DIR/inline-diverging.rs:13:8: 13:9
          _3 = _1;                         // scope 0 at $DIR/inline-diverging.rs:13:8: 13:9
          _2 = Gt(move _3, const 0_i32);   // scope 0 at $DIR/inline-diverging.rs:13:8: 13:13
          StorageDead(_3);                 // scope 0 at $DIR/inline-diverging.rs:13:12: 13:13
          switchInt(move _2) -> [false: bb2, otherwise: bb1]; // scope 0 at $DIR/inline-diverging.rs:13:8: 13:13
      }
  
      bb1: {
          StorageLive(_4);                 // scope 0 at $DIR/inline-diverging.rs:14:9: 14:10
          _4 = _1;                         // scope 0 at $DIR/inline-diverging.rs:14:9: 14:10
          _0 = move _4 as u32 (Misc);      // scope 0 at $DIR/inline-diverging.rs:14:9: 14:17
          StorageDead(_4);                 // scope 0 at $DIR/inline-diverging.rs:14:16: 14:17
          StorageDead(_2);                 // scope 0 at $DIR/inline-diverging.rs:17:5: 17:6
          return;                          // scope 0 at $DIR/inline-diverging.rs:18:2: 18:2
      }
  
      bb2: {
          StorageLive(_6);                 // scope 0 at $DIR/inline-diverging.rs:16:9: 16:16
-         _6 = panic();                    // scope 0 at $DIR/inline-diverging.rs:16:9: 16:16
+         StorageLive(_7);                 // scope 1 at $SRC_DIR/std/src/panic.rs:LL:COL
+         _7 = begin_panic::<&str>(const "explicit panic"); // scope 1 at $SRC_DIR/std/src/panic.rs:LL:COL
                                           // mir::Constant
-                                          // + span: $DIR/inline-diverging.rs:16:9: 16:14
-                                          // + literal: Const { ty: fn() -> ! {panic}, val: Value(<ZST>) }
+                                          // + span: $SRC_DIR/std/src/panic.rs:LL:COL
+                                          // + literal: Const { ty: fn(&str) -> ! {begin_panic::<&str>}, val: Value(<ZST>) }
+                                          // mir::Constant
+                                          // + span: $SRC_DIR/std/src/panic.rs:LL:COL
+                                          // + literal: Const { ty: &str, val: Value(Slice(..)) }
+     }
+ 
+     bb3 (cleanup): {
+         resume;                          // scope 0 at $DIR/inline-diverging.rs:12:1: 18:2
      }
  }