tests/mir-opt/inline/inline_instruction_set.default.Inline.diff

   1 - // MIR for `default` before Inline
   2 + // MIR for `default` after Inline
   3
   4   fn default() -> () {
   5       let mut _0: ();                      // return place in scope 0 at $DIR/inline_instruction_set.rs:+0:18: +0:18
   6       let _1: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
   7       let _2: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
   8       let _3: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
   9       let _4: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
  10 +     scope 1 (inlined instruction_set_default) { // at $DIR/inline_instruction_set.rs:59:5: 59:30
  11 +     }
  12 +     scope 2 (inlined inline_always_and_using_inline_asm) { // at $DIR/inline_instruction_set.rs:60:5: 60:41
  13 +         scope 3 {
  14 +         }
  15 +     }
  16
  17       bb0: {
  18           StorageLive(_1);                 // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
  19           _1 = instruction_set_a32() -> bb1; // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
  20                                            // mir::Constant
  21                                            // + span: $DIR/inline_instruction_set.rs:57:5: 57:24
  22                                            // + literal: Const { ty: fn() {instruction_set_a32}, val: Value(<ZST>) }
  23       }
  24
  25       bb1: {
  26           StorageDead(_1);                 // scope 0 at $DIR/inline_instruction_set.rs:+1:26: +1:27
  27           StorageLive(_2);                 // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
  28           _2 = instruction_set_t32() -> bb2; // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
  29                                            // mir::Constant
  30                                            // + span: $DIR/inline_instruction_set.rs:58:5: 58:24
  31                                            // + literal: Const { ty: fn() {instruction_set_t32}, val: Value(<ZST>) }
  32       }
  33
  34       bb2: {
  35           StorageDead(_2);                 // scope 0 at $DIR/inline_instruction_set.rs:+2:26: +2:27
  36           StorageLive(_3);                 // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
  37 -         _3 = instruction_set_default() -> bb3; // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
  38 -                                          // mir::Constant
  39 -                                          // + span: $DIR/inline_instruction_set.rs:59:5: 59:28
  40 -                                          // + literal: Const { ty: fn() {instruction_set_default}, val: Value(<ZST>) }
  41 -     }
  42 -
  43 -     bb3: {
  44           StorageDead(_3);                 // scope 0 at $DIR/inline_instruction_set.rs:+3:30: +3:31
  45           StorageLive(_4);                 // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
  46 -         _4 = inline_always_and_using_inline_asm() -> bb4; // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
  47 -                                          // mir::Constant
  48 -                                          // + span: $DIR/inline_instruction_set.rs:60:5: 60:39
  49 -                                          // + literal: Const { ty: fn() {inline_always_and_using_inline_asm}, val: Value(<ZST>) }
  50 +         asm!("/* do nothing */", options((empty))) -> bb3; // scope 3 at $DIR/inline_instruction_set.rs:43:14: 43:38
  51       }
  52
  53 -     bb4: {
  54 +     bb3: {
  55           StorageDead(_4);                 // scope 0 at $DIR/inline_instruction_set.rs:+4:41: +4:42
  56           _0 = const ();                   // scope 0 at $DIR/inline_instruction_set.rs:+0:18: +5:2
  57           return;                          // scope 0 at $DIR/inline_instruction_set.rs:+5:2: +5:2
  58       }
  59   }
  60