sys/src/libmach/6.c

   1 /*
   2  * amd64 definition
   3  */
   4 #include <u.h>
   5 #include <libc.h>
   6 #include <bio.h>
   7 #include "/amd64/include/ureg.h"
   8 #include <mach.h>
   9
  10 #define REGOFF(x)       offsetof(struct Ureg, x)
  11
  12 #define REGSIZE         sizeof(struct Ureg)
  13 #define FP_CTLS(x)      (REGSIZE+2*(x))
  14 #define FP_CTL(x)       (REGSIZE+4*(x))
  15 #define FP_REG(x)       (FP_CTL(8)+16*(x))
  16 #define XM_REG(x)       (FP_CTL(8)+8*16+16*(x))
  17
  18 #define FPREGSIZE       512     /* TO DO? currently only 0x1A0 used */
  19
  20 Reglist amd64reglist[] = {
  21         {"AX",          REGOFF(ax),     RINT, 'Y'},
  22         {"BX",          REGOFF(bx),     RINT, 'Y'},
  23         {"CX",          REGOFF(cx),     RINT, 'Y'},
  24         {"DX",          REGOFF(dx),     RINT, 'Y'},
  25         {"SI",          REGOFF(si),     RINT, 'Y'},
  26         {"DI",          REGOFF(di),     RINT, 'Y'},
  27         {"BP",          REGOFF(bp),     RINT, 'Y'},
  28         {"R8",          REGOFF(r8),     RINT, 'Y'},
  29         {"R9",          REGOFF(r9),     RINT, 'Y'},
  30         {"R10",         REGOFF(r10),    RINT, 'Y'},
  31         {"R11",         REGOFF(r11),    RINT, 'Y'},
  32         {"R12",         REGOFF(r12),    RINT, 'Y'},
  33         {"R13",         REGOFF(r13),    RINT, 'Y'},
  34         {"R14",         REGOFF(r14),    RINT, 'Y'},
  35         {"R15",         REGOFF(r15),    RINT, 'Y'},
  36         {"DS",          REGOFF(ds),     RINT, 'x'},
  37         {"ES",          REGOFF(es),     RINT, 'x'},
  38         {"FS",          REGOFF(fs),     RINT, 'x'},
  39         {"GS",          REGOFF(gs),     RINT, 'x'},
  40         {"TYPE",        REGOFF(type),   RINT, 'Y'},
  41         {"TRAP",        REGOFF(type),   RINT, 'Y'},     /* alias for acid */
  42         {"ERROR",       REGOFF(error),  RINT, 'Y'},
  43         {"IP",          REGOFF(pc),     RINT, 'Y'},
  44         {"PC",          REGOFF(pc),     RINT, 'Y'},     /* alias for acid */
  45         {"CS",          REGOFF(cs),     RINT, 'Y'},
  46         {"FLAGS",       REGOFF(flags),  RINT, 'Y'},
  47         {"SP",          REGOFF(sp),     RINT, 'Y'},
  48         {"SS",          REGOFF(ss),     RINT, 'Y'},
  49
  50         {"FCW",         FP_CTLS(0),     RFLT, 'x'},
  51         {"FSW",         FP_CTLS(1),     RFLT, 'x'},
  52         {"FTW",         FP_CTLS(2),     RFLT, 'b'},
  53         {"FOP",         FP_CTLS(3),     RFLT, 'x'},
  54         {"RIP",         FP_CTL(2),      RFLT, 'Y'},
  55         {"RDP",         FP_CTL(4),      RFLT, 'Y'},
  56         {"MXCSR",       FP_CTL(6),      RFLT, 'X'},
  57         {"MXCSRMASK",   FP_CTL(7),      RFLT, 'X'},
  58         {"M0",          FP_REG(0),      RFLT, 'F'},     /* assumes double */
  59         {"M1",          FP_REG(1),      RFLT, 'F'},
  60         {"M2",          FP_REG(2),      RFLT, 'F'},
  61         {"M3",          FP_REG(3),      RFLT, 'F'},
  62         {"M4",          FP_REG(4),      RFLT, 'F'},
  63         {"M5",          FP_REG(5),      RFLT, 'F'},
  64         {"M6",          FP_REG(6),      RFLT, 'F'},
  65         {"M7",          FP_REG(7),      RFLT, 'F'},
  66         {"X0",          XM_REG(0),      RFLT, 'F'},     /* assumes double */
  67         {"X1",          XM_REG(1),      RFLT, 'F'},
  68         {"X2",          XM_REG(2),      RFLT, 'F'},
  69         {"X3",          XM_REG(3),      RFLT, 'F'},
  70         {"X4",          XM_REG(4),      RFLT, 'F'},
  71         {"X5",          XM_REG(5),      RFLT, 'F'},
  72         {"X6",          XM_REG(6),      RFLT, 'F'},
  73         {"X7",          XM_REG(7),      RFLT, 'F'},
  74         {"X8",          XM_REG(8),      RFLT, 'F'},
  75         {"X9",          XM_REG(9),      RFLT, 'F'},
  76         {"X10",         XM_REG(10),     RFLT, 'F'},
  77         {"X11",         XM_REG(11),     RFLT, 'F'},
  78         {"X12",         XM_REG(12),     RFLT, 'F'},
  79         {"X13",         XM_REG(13),     RFLT, 'F'},
  80         {"X14",         XM_REG(14),     RFLT, 'F'},
  81         {"X15",         XM_REG(15),     RFLT, 'F'},
  82         {"X16",         XM_REG(16),     RFLT, 'F'},
  83 /*
  84         {"F0",          FP_REG(7),      RFLT, '3'},
  85         {"F1",          FP_REG(6),      RFLT, '3'},
  86         {"F2",          FP_REG(5),      RFLT, '3'},
  87         {"F3",          FP_REG(4),      RFLT, '3'},
  88         {"F4",          FP_REG(3),      RFLT, '3'},
  89         {"F5",          FP_REG(2),      RFLT, '3'},
  90         {"F6",          FP_REG(1),      RFLT, '3'},
  91         {"F7",          FP_REG(0),      RFLT, '3'},
  92 */
  93         {  0 }
  94 };
  95
  96 Mach mamd64=
  97 {
  98         "amd64",
  99         MAMD64,                 /* machine type */
 100         amd64reglist,           /* register list */
 101         REGSIZE,                /* size of registers in bytes */
 102         FPREGSIZE,              /* size of fp registers in bytes */
 103         "PC",                   /* name of PC */
 104         "SP",                   /* name of SP */
 105         0,                      /* link register */
 106         "setSB",                /* static base register name (bogus anyways) */
 107         0,                      /* static base register value */
 108         0x200000,               /* page size (for segment alignment) */
 109         0xffffffff80110000ull,  /* kernel base */
 110         0xffff800000000000ull,  /* kernel text mask */
 111         0x00007ffffffff000ull,  /* user stack top */
 112         1,                      /* quantization of pc */
 113         8,                      /* szaddr */
 114         8,                      /* szreg */
 115         4,                      /* szfloat */
 116         8,                      /* szdouble */
 117 };