6 issue at most one per unit per cycle
7 eight entry instruction queue
8 can fill queue from cache in one clock cycle
9 loads from requested address to end of cache block
12 includes ins. cache access cycles
18 IQ[3210] → fpu buffer/decode [≥1 cycle] → execute 1 → execute 2 → writeback
20 IQ0/decode → buffer [if exec busy] → execute [hold for dependency] →
21 circulate in load/store
24 IQ[3210] → decode/execute → writeback
27 address calculation must complete before stored value enters write buffer