98 [0] {cmp, "cmp", Iarith},
99 [4] {tw, "tw", Iarith},
100 [8] {subfc, "subfc", Iarith},
101 [10] {addc, "addc", Iarith},
102 [11] {mulhwu, "mulhwu", Iarith},
103 [19] {mfcr, "mfcr", Iarith},
104 [20] {lwarx, "lwarx", Iload},
105 [23] {lwzx, "lwzx", Iload},
106 [24] {slw, "slw", Ilog},
107 [26] {cntlzw, "cntlzw", Ilog},
108 [28] {and, "and", Ilog},
109 [32] {cmpl, "cmpl", Iarith},
110 [40] {subf, "subf", Iarith},
111 [54] {dcbst, "dcbst", Icontrol},
112 [55] {lwzx, "lwzux", Iload},
113 [60] {andc, "andc", Ilog},
114 [75] {mulhw, "mulhw", Iarith},
115 [83] {0, "mfmsr", Icontrol},
116 [86] {dcbf, "dcbf", Icontrol},
117 [87] {lbzx, "lbzx", Iload},
118 [104] {neg, "neg", Iarith},
119 [115] {0, "mfpmr", Iarith},
120 [119] {lbzx, "lbzux", Iload},
121 [124] {nor, "nor", Iarith},
122 [136] {subfe, "subfe", Iarith},
123 [138] {adde, "adde", Iarith},
124 [144] {mtcrf, "mtcrf", Ireg},
125 [146] {0, "mtmsr", Icontrol},
126 [150] {stwcx, "stwcx.", Istore},
127 [151] {stwx, "stwx", Istore},
128 [178] {0, "mtpmr", Icontrol},
129 [183] {stwx, "stwux", Istore},
130 [200] {subfze, "subfze", Iarith},
131 [202] {addze, "addze", Iarith},
132 [210] {0, "mtsr", Ireg},
133 [215] {stbx, "stbx", Istore},
134 [232] {subfme, "subfme", Iarith},
135 [234] {addme, "addme", Iarith},
136 [235] {mullw, "mullw", Iarith},
137 [242] {0, "mtsrin", Ireg},
138 [246] {dcbtst, "dcbtst", Icontrol},
139 [247] {stbx, "stbux", Istore},
140 [266] {add, "add", Iarith},
141 [275] {0, "mftb", Icontrol},
142 [278] {dcbt, "dcbt", Icontrol},
143 [279] {lhzx, "lhzx", Iload},
144 [284] {eqv, "eqv", Ilog},
145 [306] {0, "tlbie", Icontrol},
146 [307] {0, "mftbu", Icontrol},
147 [310] {0, "eciwx", Icontrol},
148 [311] {lhzx, "lhzux", Iload},
149 [316] {xor, "xor", Ilog},
150 [339] {mspr, "mfspr", Ireg},
151 [343] {lhax, "lhax", Iload},
152 [375] {lhax, "lhaux", Iload},
153 [403] {0, "mttb", Icontrol},
154 [407] {sthx, "sthx", Istore},
155 [412] {orc, "orc", Ilog},
156 [434] {0, "slbia", Iarith},
157 [435] {0, "mttbu", Icontrol},
158 [438] {0, "ecowx", Icontrol},
159 [439] {sthx, "sthux", Istore},
160 [444] {or, "or", Ilog},
161 [459] {divwu, "divwu", Iarith},
162 [467] {mspr, "mtspr", Ireg},
163 [470] {0, "dcbi", Icontrol},
164 [476] {nand, "nand", Ilog},
165 [491] {divw, "divw", Iarith},
166 [498] {0, "slbia", Icontrol},
167 [512] {mcrxr, "mcrxr", Ireg},
168 [533] {lswx, "lswx", Iload},
169 [534] {lwbrx, "lwbrx", Iload},
170 [535] {lfsx, "lfsx", Ifloat},
171 [536] {srw, "srw", Ilog},
172 [567] {lfsx, "lfsux", Ifloat},
173 [595] {0, "mfsr", Iarith},
174 [597] {lswi, "lswi", Iarith},
175 [598] {sync, "sync", Iarith},
176 [599] {lfdx, "lfdx", Ifloat},
177 [631] {lfdx, "lfdux", Ifloat},
178 [659] {0, "mfsrin", Ireg},
179 [661] {stswx, "stswx", Istore},
180 [662] {stwbrx, "stwbrx", Istore},
181 [663] {stfsx, "stfsx", Istore},
182 [695] {stfsx, "stfsux", Istore},
183 [725] {stswi, "stswi", Istore},
184 [727] {stfdx, "stfdx", Istore},
185 [759] {stfdx, "stfdux", Istore},
186 [790] {lhbrx, "lhbrx", Iload},
187 [792] {sraw, "sraw", Ilog},
188 [824] {srawi, "srawi", Ilog},
189 [854] {0, "eieio", Icontrol},
190 [918] {sthbrx, "sthbrx", Istore},
191 [922] {extsh, "extsh", Iarith},
192 [954] {extsb, "extsb", Iarith},
193 [982] {icbi, "icbi", Icontrol},
194 [983] {unimp, "stfiwx", Istore},
195 [1014] {dcbz, "dcbz", Icontrol},
198 Inset ops31 = {op31, nelem(op31)};
209 switch((rb<<5) | ra) {
211 undef(ir); /* was mq */
214 d = ®.xer; n = "xer";
218 d = ®.tbl; n = "tbl";
222 d = ®.tbu; n = "tbu";
225 d = ®.dec; n = "dec";
228 d = ®.lr; n = "lr";
231 d = ®.ctr; n = "ctr";
234 d = 0; sprint(n = buf, "spr%d", rd);
237 if(getxo(ir) == 339) {
239 itrace("%s\tr%d,%s", ci->name, rd, n);
244 itrace("%s\t%s,r%d", ci->name, n, rd);
264 reg.cr = (reg.cr & ~mkCR(d, 0xF)) | mkCR(d, c);
276 itrace("%s\tr%d,r%d,$0x%lux", ci->name, rd, ra, imm);
278 itrace("li\tr%d,$0x%lux", rd, imm);
294 itrace("%s\tr%d,r%d,$0x%lux", ci->name, rd, ra, imm);
296 itrace("lis\tr%d,$0x%lux", rd, imm);
310 reg.r[ra] = reg.r[rs] & reg.r[rb];
312 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
323 reg.r[ra] = reg.r[rs] & ~reg.r[rb];
325 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
337 reg.r[ra] = reg.r[rs] & imm;
339 itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
350 reg.r[ra] = reg.r[rs] & (imm<<16);
352 itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
379 reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, c);
381 itrace("%s\tcrf%d,r%d,0x%lux [cr=#%x]", ci->name, rd, ra, imm, c);
407 reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, c);
409 itrace("%s\tcrf%d,r%d,r%d [cr=#%x]", ci->name, rd, ra, rb, c);
434 reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, c);
436 itrace("%s\tcrf%d,r%d,0x%lux [cr=#%x]", ci->name, rd, ra, imm, c);
462 reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, c);
464 itrace("%s\tcrf%d,r%d,r%d [cr=#%x]", ci->name, rd, ra, rb, c);
475 for(n=0; n<32 && (reg.r[rs] & (1L<<(31-n))) == 0; n++)
479 itrace("%s%s\tr%d,r%d", ci->name, ir&1?".":"", ra, rs);
490 reg.r[ra] = ~(reg.r[rs] ^ reg.r[rb]);
492 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
505 reg.r[ra] = (schar)reg.r[rs];
507 itrace("%s%s\tr%d,r%d", ci->name, ir&1?".":"", ra, rs);
520 reg.r[ra] = (short)reg.r[rs];
522 itrace("%s%s\tr%d,r%d", ci->name, ir&1?".":"", ra, rs);
534 r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)reg.r[rb];
538 reg.xer |= XER_SO | XER_OV; /* TO DO: rubbish */
540 reg.r[rd] = (ulong)r;
544 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
555 r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)reg.r[rb];
563 reg.xer |= XER_SO | XER_OV;
565 reg.r[rd] = (ulong)r;
569 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
580 r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)reg.r[rb] + ((reg.xer&XER_CA)!=0);
588 reg.xer |= XER_SO | XER_OV;
590 reg.r[rd] = (ulong)r;
594 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
606 r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)imm;
611 reg.r[rd] = (ulong)r;
613 itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
625 r = (uvlong)(ulong)reg.r[ra] + (uvlong)(ulong)imm;
630 reg.r[rd] = (ulong)r;
633 itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
646 r = (uvlong)(ulong)reg.r[ra] + (uvlong)0xFFFFFFFFU + ((reg.xer&XER_CA)!=0);
654 reg.xer |= XER_SO | XER_OV;
656 reg.r[rd] = (ulong)r;
660 itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
673 r = (uvlong)(ulong)reg.r[ra] + ((reg.xer&XER_CA)!=0);
681 reg.xer |= XER_SO | XER_OV;
683 reg.r[rd] = (ulong)r;
687 itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
696 if(reg.r[rb] != 0 && ((ulong)reg.r[ra] != 0x80000000 || reg.r[rb] != -1))
697 reg.r[rd] = reg.r[ra]/reg.r[rb];
699 reg.xer |= XER_SO | XER_OV;
703 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
713 reg.r[rd] = (ulong)reg.r[ra]/(ulong)reg.r[rb];
715 reg.xer |= XER_SO | XER_OV;
719 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
728 if(rd & 3 || ra != 0 || rb != 0 || ir & Rc)
731 reg.cr = (reg.cr & ~mkCR(rd, 0xF)) | mkCR(rd, reg.xer>>28);
732 reg.xer &= ~(0xF<<28);
741 if(ir & ((1<<20)|(1<<11)|Rc))
746 for(i = 0x80; i; i >>= 1) {
751 reg.cr = (reg.cr & ~m) | (reg.r[rs] & m);
760 if(ra != 0 || rb != 0 || ir & Rc)
771 reg.r[rd] = ((vlong)(long)reg.r[ra]*(long)reg.r[rb])>>32;
775 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
776 /* BUG: doesn't set OV */
785 reg.r[rd] = ((uvlong)(ulong)reg.r[ra]*(ulong)reg.r[rb])>>32;
787 setcr(0, reg.r[rd]); /* not sure whether CR setting is signed or unsigned */
789 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
790 /* BUG: doesn't set OV */
799 reg.r[rd] = (uvlong)(ulong)reg.r[ra]*(ulong)reg.r[rb];
803 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&Rc?".":"", rd, ra, rb);
804 /* BUG: doesn't set OV */
814 reg.r[rd] = (uvlong)(ulong)reg.r[ra]*(ulong)imm;
816 itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
825 reg.r[ra] = ~(reg.r[rs] & reg.r[rb]);
829 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
842 if((ulong)reg.r[ra] == 0x80000000) {
844 reg.xer |= XER_SO | XER_OV;
845 reg.r[rd] = reg.r[ra];
847 reg.r[rd] = -reg.r[ra];
858 reg.r[ra] = ~(reg.r[rs] | reg.r[rb]);
862 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
871 reg.r[ra] = reg.r[rs] | reg.r[rb];
876 itrace("mr%s\tr%d,r%d", ir&1?".":"", ra, rs);
878 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
888 reg.r[ra] = reg.r[rs] | ~reg.r[rb];
892 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
902 reg.r[ra] = reg.r[rs] | imm;
904 itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
914 reg.r[ra] = reg.r[rs] | (imm<<16);
916 itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
920 mkmask(int mb, int me)
926 return mkmask(0, me) | mkmask(mb, 31);
928 for(i=mb; i<=me; i++)
929 v |= 1L << (31-i); /* don't need a loop, but i'm lazy */
934 rotl(ulong v, int sh)
938 return (v<<sh) | (v>>(32-sh));
949 m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
950 reg.r[ra] = (reg.r[ra] & ~m) | (rotl(reg.r[rs], sh) & m);
952 itrace("%s\tr%d,r%d,%d,#%lux", ci->name, ra, rs, sh, m);
965 m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
966 reg.r[ra] = rotl(reg.r[rs], sh) & m;
968 itrace("%s%s\tr%d,r%d,%d,#%lux", ci->name, ir&Rc?".":"", ra, rs, sh, m);
980 sh = reg.r[rb] & 0x1F;
981 m = mkmask((ir>>6)&0x1F, (ir>>1)&0x1F);
982 reg.r[ra] = rotl(reg.r[rs], sh) & m;
984 itrace("%s\tr%d,r%d,r%d,#%lux", ci->name, ra, rs, rb, m);
997 if((v & 0x20) == 0) {
999 reg.r[ra] = (ulong)reg.r[rs] << v;
1003 setcr(0, reg.r[ra]);
1005 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
1016 if((v & 0x20) == 0) {
1018 if(reg.r[rs]&SIGNBIT && v)
1019 reg.r[ra] = reg.r[rs]>>v | ~((1<<(32-v))-1);
1021 reg.r[ra] = reg.r[rs]>>v;
1023 reg.r[ra] = reg.r[rs]&SIGNBIT? ~0: 0;
1025 setcr(0, reg.r[ra]);
1027 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
1038 if((v & 0x20) == 0) {
1040 if(reg.r[rs]&SIGNBIT && v)
1041 reg.r[ra] = reg.r[rs]>>v | ~((1<<(32-v))-1);
1043 reg.r[ra] = reg.r[rs]>>v;
1045 reg.r[ra] = reg.r[rs]&SIGNBIT? ~0: 0;
1047 setcr(0, reg.r[ra]);
1049 itrace("%s%s\tr%d,r%d,$%d", ci->name, ir&1?".":"", ra, rs, v);
1061 reg.r[ra] = (ulong)reg.r[rs] >> (v&0x1F);
1065 setcr(0, reg.r[ra]);
1067 itrace("%s%s\tr%d,r%d,r%d", ci->name, ir&1?".":"", ra, rs, rb);
1077 r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)(ulong)reg.r[rb] + 1;
1081 reg.xer |= XER_SO | XER_OV;
1083 reg.r[rd] = (ulong)r;
1085 setcr(0, reg.r[rd]);
1087 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
1098 r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)(ulong)reg.r[rb] + 1;
1106 reg.xer |= XER_SO | XER_OV;
1108 reg.r[rd] = (ulong)r;
1110 setcr(0, reg.r[rd]);
1112 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
1123 r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)(ulong)reg.r[rb] + ((reg.xer&XER_CA)!=0);
1131 reg.xer |= XER_SO | XER_OV;
1133 reg.r[rd] = (ulong)r;
1135 setcr(0, reg.r[rd]);
1137 itrace("%s%s%s\tr%d,r%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra, rb);
1149 r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)(ulong)imm + 1;
1154 reg.r[rd] = (ulong)r;
1156 itrace("%s\tr%d,r%d,$%ld", ci->name, rd, ra, imm);
1169 r = (uvlong)((ulong)~reg.r[ra]) + (uvlong)0xFFFFFFFFU + ((reg.xer&XER_CA)!=0);
1177 reg.xer |= XER_SO | XER_OV;
1179 reg.r[rd] = (ulong)r;
1181 setcr(0, reg.r[rd]);
1183 itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
1196 r = (uvlong)((ulong)~reg.r[ra]) + ((reg.xer&XER_CA)!=0);
1204 reg.xer |= XER_SO | XER_OV;
1206 reg.r[rd] = (ulong)r;
1208 setcr(0, reg.r[rd]);
1210 itrace("%s%s%s\tr%d,r%d", ci->name, ir&OE?"o":"", ir&1?".":"", rd, ra);
1219 reg.r[ra] = reg.r[rs] ^ reg.r[rb];
1221 itrace("%s\tr%d,r%d,r%d", ci->name, ra, rs, rb);
1231 reg.r[ra] = reg.r[rs] ^ imm;
1233 itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
1243 reg.r[ra] = reg.r[rs] ^ (imm<<16);
1245 itrace("%s\tr%d,r%d,$0x%lx", ci->name, ra, rs, imm);
1257 upd = (ir&(1L<<26))!=0;
1267 itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
1269 reg.r[rd] = getmem_w(ea);
1276 int rb, ra, rd, upd;
1280 upd = getxo(ir)==55;
1286 itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
1291 itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
1294 reg.r[rd] = getmem_w(ea);
1312 upd = (ir&(1L<<26))!=0;
1322 itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
1324 reg.r[rd] = getmem_b(ea);
1331 int rb, ra, rd, upd;
1335 upd = getxo(ir)==119;
1341 itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
1346 itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
1349 reg.r[rd] = getmem_b(ea);
1361 upd = (ir&(1L<<26))!=0;
1371 itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
1372 ci->name, rd, imm, ra, ea, reg.r[rd], reg.r[rd]);
1373 putmem_w(ea, reg.r[rd]);
1381 int ra, rd, upd, rb;
1385 upd = getxo(ir)==183;
1391 itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
1392 ci->name, rd, ra, rb, ea, reg.r[rd], reg.r[rd]);
1397 itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
1398 ci->name, rd, rb, ea, reg.r[rd], reg.r[rd]);
1400 putmem_w(ea, reg.r[rd]);
1417 itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
1418 ci->name, rd, ra, rb, ea, reg.r[rd], reg.r[rd]);
1421 itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
1422 ci->name, rd, rb, ea, reg.r[rd], reg.r[rd]);
1424 putmem_w(ea, reg.r[rd]); /* assume a reservation exists; store succeeded */
1438 upd = (ir&(1L<<26))!=0;
1447 v = reg.r[rd] & 0xFF;
1449 itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
1450 ci->name, rd, imm, ra, ea, v, v);
1458 int ra, rd, upd, rb, v;
1462 upd = getxo(ir)==247;
1463 v = reg.r[rd] & 0xFF;
1469 itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
1470 ci->name, rd, ra, rb, ea, v, v);
1475 itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
1476 ci->name, rd, rb, ea, v, v);
1486 int imm, ra, rd, upd;
1490 upd = (ir&(1L<<26))!=0;
1500 itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
1502 reg.r[rd] = getmem_h(ea);
1509 int rb, ra, rd, upd;
1513 upd = getxo(ir)==311;
1519 itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
1524 itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
1527 reg.r[rd] = getmem_h(ea);
1534 int imm, ra, rd, upd;
1538 upd = (ir&(1L<<26))!=0;
1548 itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
1550 reg.r[rd] = (short)getmem_h(ea);
1557 int rb, ra, rd, upd;
1561 upd = getxo(ir)==311;
1567 itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
1572 itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
1575 reg.r[rd] = (short)getmem_h(ea);
1590 itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
1593 itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
1597 reg.r[rd] = ((v&0xFF)<<8)|(v&0xFF);
1604 int imm, ra, rd, upd, v;
1608 upd = (ir&(1L<<26))!=0;
1617 v = reg.r[rd] & 0xFFFF;
1619 itrace("%s\tr%d,%ld(r%d) #%lux=#%lux (%ld)",
1620 ci->name, rd, imm, ra, ea, v, v);
1629 int ra, rd, upd, rb, v;
1633 upd = getxo(ir)==247;
1634 v = reg.r[rd] & 0xFFFF;
1640 itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
1641 ci->name, rd, ra, rb, ea, v, v);
1646 itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
1647 ci->name, rd, rb, ea, v, v);
1662 v = ((v&0xFF)<<8)|(v&0xFF);
1666 itrace("%s\tr%d,(r%d+r%d) #%lux=#%lux (%ld)",
1667 ci->name, rd, ra, rb, ea, v, v);
1670 itrace("%s\tr%d,(r%d) #%lux=#%lux (%ld)",
1671 ci->name, rd, rb, ea, v, v);
1690 itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
1693 itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
1696 for(i = 0; i < 4; i++)
1697 v = v>>8 | getmem_b(ea++); /* assume unaligned load is allowed */
1715 itrace("%s\tr%d,(r%d+r%d) ea=%lux", ci->name, rd, ra, rb, ea);
1718 itrace("%s\tr%d,(r%d) ea=%lux", ci->name, rd, rb, ea);
1721 for(i = 0; i < 4; i++) {
1722 putmem_b(ea++, v & 0xFF); /* assume unaligned store is allowed */
1731 int rb, ra, rd, n, i, r, b;
1743 itrace("%s\tr%d,(r%d),%d ea=%lux", ci->name, rd, ra, n, ea);
1746 itrace("%s\tr%d,(0),%d ea=0", ci->name, rd, n);
1753 if(ra == 0 || r != ra)
1758 if(ra == 0 || r != ra)
1759 reg.r[r] = (reg.r[r] & ~(0xFF<<i)) | (b << i);
1768 int rb, ra, rd, n, i, r, b;
1778 itrace("%s\tr%d,(r%d+r%d) ea=%lux n=%d", ci->name, rd, ra, rb, ea, n);
1781 itrace("%s\tr%d,(r%d) ea=%lux n=%d", ci->name, rd, rb, ea, n);
1788 if((ra == 0 || r != ra) && r != rb)
1793 if((ra == 0 || r != ra) && r != rb)
1794 reg.r[r] = (reg.r[r] & ~(0xFF<<i)) | (b << i);
1803 int rb, ra, rd, n, i, r;
1813 itrace("%s\tr%d,(r%d+r%d) ea=%lux n=%d", ci->name, rd, ra, rb, ea, n);
1816 itrace("%s\tr%d,(r%d) ea=%lux n=%d", ci->name, rd, rb, ea, n);
1825 putmem_b(ea++, (reg.r[r]>>i)&0xFF);
1834 int rb, ra, rd, n, i, r;
1846 itrace("%s\tr%d,(r%d),%d ea=%lux", ci->name, rd, ra, n, ea);
1849 itrace("%s\tr%d,(0),%d ea=0", ci->name, rd, n);
1858 putmem_b(ea++, (reg.r[r]>>i)&0xFF);
1875 itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
1877 for(r = rd; r <= 31; r++) {
1878 if(r != 0 && r != rd)
1879 reg.r[rd] = getmem_w(ea);
1896 itrace("%s\tr%d,%ld(r%d) ea=%lux", ci->name, rd, imm, ra, ea);
1898 for(r = rd; r <= 31; r++) {
1899 putmem_w(ea, reg.r[rd]);
1913 itrace("twi\t#%.2x,r%d,$0x%lux (%ld)", rd, ra, imm, imm);
1914 if(a < imm && rd&0x10 ||
1915 a > imm && rd&0x08 ||
1916 a == imm && rd&0x04 ||
1917 (ulong)a < imm && rd&0x02 ||
1918 (ulong)a > imm && rd&0x01) {
1919 Bprint(bioout, "program_exception (trap type)\n");
1934 itrace("tw\t#%.2x,r%d,r%d", rd, ra, rb);
1935 if(a < b && rd&0x10 ||
1937 a == b && rd&0x04 ||
1938 (ulong)a < b && rd&0x02 ||
1939 (ulong)a > b && rd&0x01) {
1940 Bprint(bioout, "program_exception (trap type)\n");
1963 itrace("%s\tr%d,r%d", ci->name, ra, rb);
1976 itrace("%s\tr%d,r%d", ci->name, ra, rb);
1989 itrace("%s\tr%d,r%d", ci->name, ra, rb);
2002 itrace("%s\tr%d,r%d", ci->name, ra, rb);
2015 itrace("%s\tr%d,r%d", ci->name, ra, rb);
2028 itrace("%s\tr%d,r%d", ci->name, ra, rb);