2 * realtek rtl8150 10/100 usb ethernet device driver
4 * copy-pasted from shingo watanabe's openbsd url(4) driver
5 * and bill paul's and shunsuke akiyama's freebsd rue(4) driver
16 Mfl = 60, /* min frame len */
20 Rqm = 0x05, /* request mem */
21 Crm = 1, /* command read mem */
22 Cwm = 2, /* command write mem */
25 enum { /* registers */
26 Idr0 = 0x120, /* ether addr, load from 93c46 */
33 Mar0 = 0x126, /* multicast addr */
42 Cr = 0x12e, /* command */
43 Tcr = 0x12f, /* transmit control */
44 Rcr = 0x130, /* receive configuration */
49 Msr = 0x137, /* media status */
50 Phyar = 0x138, /* mii phy addr select */
51 Phydr = 0x139, /* mii phy data */
52 Phycr = 0x13b, /* mii phy control */
54 Wcr = 0x13e, /* wake count */
55 Bmcr = 0x140, /* basic mode control */
56 Bmsr = 0x142, /* basic mode status */
57 Anar = 0x144, /* an advertisement */
58 Anlp = 0x146, /* an link partner ability */
60 Nwtr = 0x14a, /* nway test */
69 Bm0 = 0x158, /* byte mask */
81 We = 1 << 5, /* eeprom write enable */
82 Sr = 1 << 4, /* software reset */
83 Re = 1 << 3, /* ethernet receive enable */
84 Te = 1 << 2, /* ethernet transmit enable */
85 Ep3ce = 1 << 1, /* enable clr of perf counter */
86 Al = 1 << 0 /* auto-load contents of 93c46 */
90 Tr1 = 1 << 7, /* tx retry count */
92 Ifg1 = 1 << 4, /* interframe gap time */
94 Nocrc = 1 << 0 /* no crc appended */
111 Mdx = 1 << 4, /* duplex */
112 S100 = 1 << 3, /* speed 100 */
123 Phyown = 1 << 6, /* own bit */
124 Rwcr = 1 << 5, /* mii mgmt data r/w control */
125 Phyoffmsk = 0x1f /* phy register offset */
129 Spd = 0x2000, /* speed set */
130 Bdx = 0x0100 /* duplex */
134 Ap = 0x0400 /* pause */
138 Lpp = 0x0400 /* pause */
141 enum { /* eeprom address declarations */
143 Eidr0 = Ebase + 0x02,
144 Eidr1 = Ebase + 0x03,
145 Eidr2 = Ebase + 0x03,
146 Eidr3 = Ebase + 0x03,
147 Eidr4 = Ebase + 0x03,
148 Eidr5 = Ebase + 0x03,
149 Eint = Ebase + 0x17 /* interval */
152 enum { /* receive header */
153 Bcm = 0x0fff, /* rx bytes count mask */
154 Vpm = 0x1000, /* valid packet mask */
155 Rpm = 0x2000, /* runt packet mask */
156 Ppm = 0x4000, /* physical match packet mask */
157 Mpm = 0x8000 /* multicast packet mask */
160 static int mem(Dev *, int, int, uchar *, int);
161 static int csr8r(Dev *, int);
162 static int csr16r(Dev *, int);
163 static int csr8w(Dev *, int, int);
164 static int csr16w(Dev *, int, int);
165 static int csr32w(Dev *, int, int);
166 static void reset(Dev *);
167 static int urlread(Dev *, uchar *, int);
168 static void urlwrite(Dev *, uchar *, int);
172 mem(Dev *d, int cmd, int off, uchar *buf, int len)
183 rc = usbcmd(d, r, Rqm, off, 0, buf, len);
185 fprint(2, "%s: mem(%d, %#.4x) failed\n",
192 csr8r(Dev *d, int reg)
197 if(mem(d, Crm, reg, &v, sizeof v) < 0)
203 csr16r(Dev *d, int reg)
208 if(mem(d, Crm, reg, v, sizeof v) < 0)
214 csr8w(Dev *d, int reg, int val)
219 if(mem(d, Cwm, reg, &v, sizeof v) < 0)
225 csr16w(Dev *d, int reg, int val)
230 if(mem(d, Cwm, reg, v, sizeof v) < 0)
236 csr32w(Dev *d, int reg, int val)
241 if(mem(d, Cwm, reg, v, sizeof v) < 0)
251 r = csr8r(d, Cr) | Sr;
254 for(i = 0; i < Timeout; i++) {
255 if((csr8r(d, Cr) & Sr) == 0)
260 fprint(2, "%s: reset failed\n", argv0);
266 urlread(Dev *ep, uchar *p, int plen)
273 nbin = read(ep->dfd, bin, sizeof bin);
285 if((hd & Vpm) == 0) {
286 fprint(2, "url: rx error: %#.4ux\n", hd);
299 urlwrite(Dev *ep, uchar *p, int n)
305 memset(bout+n, 0, Mfl-n);
308 write(ep->dfd, bout, n);
317 if(mem(d, Crm, Idr0, macaddr, sizeof macaddr) < 0)
321 for(i = 0; i < sizeof macaddr; i++)
322 csr8w(d, Idr0+i, macaddr[i]);
324 csr8w(d, Tcr, Tr1|Tr0|Ifg1|Ifg0);
325 csr16w(d, Rcr, Tail|Ad|Ab);
327 r = csr16r(d, Rcr) & ~(Am | Aam | Aap);