18 itrace("ldf\tf%d,0x%lux(r%d) ea=%lux",rd, ea, rs1, ea+reg.r[rs1]);
22 ea = reg.r[rs1] + reg.r[rs2];
24 itrace("ldf\tf%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
27 reg.di[rd] = getmem_w(ea);
40 itrace("lddf\tf%d,0x%lux(r%d) ea=%lux",
41 rd, ea, rs1, ea+reg.r[rs1]);
45 ea = reg.r[rs1] + reg.r[rs2];
47 itrace("lddf\tf%d,[r%d+r%d] ea=%lux", rd, rs1, rs2, ea);
51 Bprint(bioout, "mem_address_not_aligned [load addr %.8lux]\n", ea);
57 reg.di[rd] = getmem_w(ea);
58 reg.di[rd+1] = getmem_w(ea+4);
71 itrace("stf\tf%d,0x%lux(r%d) %lux=%g",
72 rd, ea, rs1, ea+reg.r[rs1], reg.fl[rd]);
76 ea = reg.r[rs1] + reg.r[rs2];
78 itrace("stf\tf%d,[r%d+r%d] %lux=%lux",
79 rd, rs1, rs2, ea, reg.r[rd]);
82 putmem_w(ea, reg.di[rd]);
95 itrace("stdf\tf%d,0x%lux(r%d) %lux=%g",
96 rd, ea, rs1, ea+reg.r[rs1], reg.fl[rd]);
100 ea = reg.r[rs1] + reg.r[rs2];
102 itrace("stdf\tf%d,[r%d+r%d] %lux=%lux",
103 rd, rs1, rs2, ea, reg.r[rd]);
107 Bprint(bioout, "mem_address_not_aligned [store addr %.8lux]\n", ea);
113 putmem_w(ea, reg.di[rd]);
114 putmem_w(ea+4, reg.di[rd+1]);
120 int fc, rd, rs1, rs2;
125 switch((ir>>5)&0x1FF) {
128 case 0x51: /* fcmps */
130 itrace("fcmps\tf%d,f%d", rs1, rs2);
131 if(isNaN(reg.fl[rs1]) || isNaN(reg.fl[rs2])) {
135 if(reg.fl[rs1] == reg.fl[rs2]) {
139 if(reg.fl[rs1] < reg.fl[rs2]) {
143 if(reg.fl[rs1] > reg.fl[rs2]) {
147 print("ki: fcmp error\n");
151 itrace("fcmpd\tf%d,f%d", rs1, rs2);
154 if(isNaN(reg.fd[rs1]) || isNaN(reg.fd[rs2])) {
158 if(reg.fd[rs1] == reg.fd[rs2]) {
162 if(reg.fd[rs1] < reg.fd[rs2]) {
166 if(reg.fd[rs1] > reg.fd[rs2]) {
170 print("ki: fcmp error\n");
172 case 0x55: /* fcmpes */
174 itrace("fcmpes\tf%d,f%d", rs1, rs2);
177 if(isNaN(reg.fl[rs1]) || isNaN(reg.fl[rs2])) {
178 Bprint(bioout, "invalid_fp_register\n");
181 if(reg.fl[rs1] == reg.fl[rs2]) {
185 if(reg.fl[rs1] < reg.fl[rs2]) {
189 if(reg.fl[rs1] > reg.fl[rs2]) {
193 print("ki: fcmp error\n");
197 itrace("fcmped\tf%d,f%d", rs1, rs2);
198 if(isNaN(reg.fd[rs1]) || isNaN(reg.fd[rs2])) {
199 Bprint(bioout, "invalid_fp_register\n");
202 if(reg.fd[rs1] == reg.fd[rs2]) {
206 if(reg.fd[rs1] < reg.fd[rs2]) {
210 if(reg.fd[rs1] > reg.fd[rs2]) {
214 print("ki: fcmp error\n");
218 reg.fpsr = (reg.fpsr&~(0x3<<10)) | (fc<<10);
226 int takeit, fc, ba, anul;
228 fc = (reg.fpsr>>10)&3;
231 switch((ir>>25)&0x0F) {
238 takeit = fc == FP_L || fc == FP_G || fc == FP_U;
242 takeit = fc == FP_L || fc == FP_G;
246 takeit = fc == FP_L || fc == FP_U;
254 takeit = fc == FP_U || fc == FP_G;
275 takeit = fc == FP_E || fc == FP_U;
279 takeit = fc == FP_E || fc == FP_G;
283 takeit = fc == FP_E || fc == FP_G || fc == FP_U;
287 takeit = fc == FP_E || fc == FP_L;
291 takeit = fc == FP_E || fc == FP_L || fc == FP_U;
295 takeit = fc == FP_E || fc == FP_L || fc == FP_G;
302 npc = (npc<<2) + reg.pc;
307 itrace("%s,a\t%lux", op, npc);
309 itrace("%s\t%lux", op, npc);
315 reg.ir = ifetch(reg.pc);
329 reg.ir = ifetch(reg.pc+4);
339 int rd, rs1, rs2, fmt;
343 switch((ir>>5)&0x1FF) {
347 reg.fl[rd] = reg.fl[rs1] + reg.fl[rs2];
351 reg.fd[rd>>1] = reg.fd[rs1>>1] + reg.fd[rs2>>1];
355 reg.fl[rd] = reg.fl[rs1] - reg.fl[rs2];
359 reg.fd[rd>>1] = reg.fd[rs1>>1] - reg.fd[rs2>>1];
363 if(reg.fl[rs2] == 0.0) {
364 Bprint(bioout, "fp_exception DZ\n");
367 reg.fl[rd] = reg.fl[rs1] / reg.fl[rs2];
371 if(reg.fd[rs2>>1] == 0.0) {
372 Bprint(bioout, "fp_exception DZ\n");
375 reg.fd[rd>>1] = reg.fd[rs1>>1] / reg.fd[rs2>>1];
379 reg.fl[rd] = reg.fl[rs1] * reg.fl[rs2];
383 reg.fd[rd>>1] = reg.fd[rs1>>1] * reg.fd[rs2>>1];
387 reg.fl[rd] = (long)reg.di[rs2];
392 reg.fd[rd>>1] = (long)reg.di[rs2];
409 reg.di[rd] = reg.di[rs2];
414 reg.fl[rd] = -reg.fl[rs2];
419 reg.fl[rd] = fabs(reg.fl[rs2]);
424 reg.fd[rd>>1] = reg.fl[rs2];
429 reg.fl[rd] = reg.fd[rs2>>1];
438 itrace("%s\tf%d,f%d,f%d", op, rs1, rs2, rd);
441 itrace("%s\tf%d,f%d", op, rs2, rd);