2 * Generic VGA registers.
5 MiscW = 0x03C2, /* Miscellaneous Output (W) */
6 MiscR = 0x03CC, /* Miscellaneous Output (R) */
7 Status0 = 0x03C2, /* Input status 0 (R) */
8 Status1 = 0x03DA, /* Input Status 1 (R) */
9 FeatureR = 0x03CA, /* Feature Control (R) */
10 FeatureW = 0x03DA, /* Feature Control (W) */
12 Seqx = 0x03C4, /* Sequencer Index, Data at Seqx+1 */
13 Crtx = 0x03D4, /* CRT Controller Index, Data at Crtx+1 */
14 Grx = 0x03CE, /* Graphics Controller Index, Data at Grx+1 */
15 Attrx = 0x03C0, /* Attribute Controller Index and Data */
17 PaddrW = 0x03C8, /* Palette Address Register, write */
18 Pdata = 0x03C9, /* Palette Data Register */
19 Pixmask = 0x03C6, /* Pixel Mask Register */
20 PaddrR = 0x03C7, /* Palette Address Register, read */
21 Pstatus = 0x03C7, /* DAC Status (RO) */
23 Pcolours = 256, /* Palette */
33 RefFreq = 14318180, /* External Reference Clock frequency */
42 typedef struct Ctlr Ctlr;
43 typedef struct Vga Vga;
47 void (*snarf)(Vga*, Ctlr*);
48 void (*options)(Vga*, Ctlr*);
49 void (*init)(Vga*, Ctlr*);
50 void (*load)(Vga*, Ctlr*);
51 void (*dump)(Vga*, Ctlr*);
60 Fsnarf = 0x00000001, /* snarf done */
61 Foptions = 0x00000002, /* options done */
62 Finit = 0x00000004, /* init done */
63 Fload = 0x00000008, /* load done */
64 Fdump = 0x00000010, /* dump done */
65 Ferror = 0x00000020, /* error during snarf */
67 Hpclk2x8 = 0x00000100, /* have double 8-bit mode */
68 Upclk2x8 = 0x00000200, /* use double 8-bit mode */
69 Henhanced = 0x00000400, /* have enhanced mode */
70 Uenhanced = 0x00000800, /* use enhanced mode */
71 Hpvram = 0x00001000, /* have parallel VRAM */
72 Upvram = 0x00002000, /* use parallel VRAM */
73 Hextsid = 0x00004000, /* have external SID mode */
74 Uextsid = 0x00008000, /* use external SID mode */
75 Hclk2 = 0x00010000, /* have clock-doubler */
76 Uclk2 = 0x00020000, /* use clock-doubler */
77 Hlinear = 0x00040000, /* have linear-address mode */
78 Ulinear = 0x00080000, /* use linear-address mode */
79 Hclkdiv = 0x00100000, /* have a clock-divisor */
80 Uclkdiv = 0x00200000, /* use clock-divisor */
81 Hsid32 = 0x00400000, /* have a 32-bit (as opposed to 64-bit) SID */
84 typedef struct Attr Attr;
93 char type[Namelen+1]; /* monitor type e.g. "vs1782" */
94 char size[Namelen+1]; /* size e.g. "1376x1024x8" */
95 char chan[Namelen+1]; /* channel descriptor, e.g. "m8" or "r8g8b8a8" */
96 char name[Namelen+1]; /* optional */
98 int frequency; /* Dot Clock (MHz) */
99 int deffrequency; /* Default dot clock if calculation can't be done */
100 int x; /* Horizontal Display End (Crt01), from .size[] */
101 int y; /* Vertical Display End (Crt18), from .size[] */
102 int z; /* depth, from .size[] */
104 int ht; /* Horizontal Total (Crt00) */
105 int shb; /* Start Horizontal Blank (Crt02) */
106 int ehb; /* End Horizontal Blank (Crt03) */
108 int shs; /* optional Start Horizontal Sync (Crt04) */
109 int ehs; /* optional End Horizontal Sync (Crt05) */
111 int vt; /* Vertical Total (Crt06) */
112 int vrs; /* Vertical Retrace Start (Crt10) */
113 int vre; /* Vertical Retrace End (Crt11) */
124 typedef struct Modelist Modelist;
130 typedef struct Edid {
131 char mfr[4]; /* manufacturer */
132 char serialstr[16]; /* serial number as string (in extended data) */
133 char name[16]; /* monitor name as string (in extended data) */
134 ushort product; /* product code, 0 = unused */
135 ulong serial; /* serial number, 0 = unused */
136 uchar version; /* major version number */
137 uchar revision; /* minor version number */
138 uchar mfrweek; /* week of manufacture, 0 = unused */
139 int mfryear; /* year of manufacture, 0 = unused */
140 uchar dxcm; /* horizontal image size in cm. */
141 uchar dycm; /* vertical image size in cm. */
142 int gamma; /* gamma*100 */
143 int rrmin; /* minimum vertical refresh rate */
144 int rrmax; /* maximum vertical refresh rate */
145 int hrmin; /* minimum horizontal refresh rate */
146 int hrmax; /* maximum horizontal refresh rate */
147 ulong pclkmax; /* maximum pixel clock */
149 Modelist *modelist; /* list of supported modes */
152 typedef struct Flag {
158 * The sizes of the register sets are large as many SVGA and GUI chips have extras.
159 * The Crt registers are ushorts in order to keep overflow bits handy.
160 * The clock elements are used for communication between the VGA, RAMDAC and clock chips;
161 * they can use them however they like, it's assumed they will be used compatibly.
163 * The mode->x, mode->y coordinates are the physical size of the screen.
164 * Virtx and virty are the coordinates of the underlying memory image.
165 * This can be used to implement panning around a larger screen or to cope
166 * with chipsets that need the in-memory pixel line width to be a round number.
167 * For example, virge.c uses this because the Savage chipset needs the pixel
168 * width to be a multiple of 16. Also, mga2164w.c needs the pixel width
169 * to be a multiple of 128.
171 * Vga->panning differentiates between these two uses of virtx, virty.
173 * (14 October 2001, rsc) Most drivers don't know the difference between
174 * mode->x and virtx, a bug that should be corrected. Vga.c, virge.c, and
175 * mga2164w.c know. For the others, the computation that sets crt[0x13]
176 * should use virtx instead of mode->x (and maybe other places change too,
177 * dependent on the driver).
182 uchar sequencer[256];
185 uchar attribute[256];
188 uchar palette[Pcolours][3];
190 ulong f[2]; /* clock */
199 ulong vma; /* video memory linear-address alignment */
200 ulong vmb; /* video memory linear-address base */
201 ulong apz; /* aperture size */
202 ulong vmz; /* video memory size */
204 ulong membw; /* memory bandwidth, MB/s */
206 long offset; /* BIOS string offset */
207 char* bios; /* matching BIOS string */
208 Pcidev* pci; /* matching PCI device if any */
212 ulong virtx; /* resolution of virtual screen */
215 int panning; /* pan the virtual screen */
226 Edid* edid[8]; /* edid information for connected monitors */
233 extern Ctlr tdfxhwgc;
236 extern Ctlr ark2000pv;
237 extern Ctlr ark2000pvhwgc;
240 extern Ctlr att20c490;
241 extern Ctlr att20c491;
242 extern Ctlr att20c492;
245 extern uchar attdaci(uchar);
246 extern void attdaco(uchar, uchar);
247 extern Ctlr att21c498;
250 extern uchar bt485i(uchar);
251 extern void bt485o(uchar, uchar);
258 extern void clgd54xxclock(Vga*, Ctlr*);
259 extern Ctlr clgd542x;
260 extern Ctlr clgd542xhwgc;
263 extern Ctlr clgd546x;
264 extern Ctlr clgd546xhwgc;
269 extern Ctlr ct65545hwgc;
272 extern Ctlr cyber938x;
273 extern Ctlr cyber938xhwgc;
278 extern Ctlr *ctlrs[];
279 extern ushort dacxreg[4];
282 extern Attr* mkattr(Attr*, char*, char*, ...);
283 extern char* dbattr(Attr*, char*);
284 extern int dbctlr(char*, Vga*);
285 extern Mode* dbmode(char*, char*, char*);
286 extern void dbdumpmode(Mode*);
290 Fdigital = 1<<0, /* is a digital display */
291 Fdpmsstandby = 1<<1, /* supports DPMS standby mode */
292 Fdpmssuspend = 1<<2, /* supports DPMS suspend mode */
293 Fdpmsactiveoff = 1<<3, /* supports DPMS active off mode */
294 Fmonochrome = 1<<4, /* is a monochrome display */
295 Fgtf = 1<<5, /* supports VESA GTF: see /public/doc/vesa/gtf10.pdf */
297 extern Flag edidflags[];
298 extern void printflags(Flag *f, int b);
299 extern Edid* parseedid128(void *v);
300 extern void printedid(Edid *e);
303 extern void error(char*, ...);
304 extern void trace(char*, ...);
305 extern int vflag, Vflag;
311 extern Ctlr et4000hwgc;
314 extern Ctlr hiqvideo;
315 extern Ctlr hiqvideohwgc;
319 extern Ctlr i81xhwgc;
325 extern Ctlr icd2061a;
329 extern Ctlr ics2494a;
335 extern uchar inportb(long);
336 extern void outportb(long, uchar);
337 extern ushort inportw(long);
338 extern void outportw(long, ushort);
339 extern ulong inportl(long);
340 extern void outportl(long, ulong);
341 extern char* vgactlr(char*, char*);
342 extern void vgactlw(char*, char*);
343 extern char* readbios(long, long);
344 extern void dumpbios(long);
345 extern void error(char*, ...);
346 extern void* alloc(ulong);
347 extern void printitem(char*, char*);
348 extern void printreg(ulong);
349 extern void printflag(ulong);
350 extern void setpalette(int, int, int, int);
351 extern int curprintindex;
352 extern uvlong rdmsr(long);
353 extern void wrmsr(long, uvlong);
357 extern Ctlr geodehwgc;
361 extern Ctlr igfxhwgc;
370 extern Ctlr mach64xx;
371 extern Ctlr mach64xxhwgc;
374 extern char* chanstr[];
375 extern void resyncinit(Vga*, Ctlr*, ulong, ulong);
376 extern void sequencer(Vga*, int);
377 extern void main(int, char*[]);
381 extern Ctlr mga2164w;
382 extern Ctlr mga2164whwgc;
385 extern Ctlr neomagic;
386 extern Ctlr neomagichwgc;
390 extern Ctlr nvidiahwgc;
394 extern Ctlr radeonhwgc;
400 typedef struct Pcidev Pcidev;
402 extern int pcicfgr8(Pcidev*, int);
403 extern int pcicfgr16(Pcidev*, int);
404 extern int pcicfgr32(Pcidev*, int);
405 extern void pcicfgw8(Pcidev*, int, int);
406 extern void pcicfgw16(Pcidev*, int, int);
407 extern void pcicfgw32(Pcidev*, int, int);
408 extern void pcihinv(Pcidev*);
409 extern Pcidev* pcimatch(Pcidev*, int, int);
415 extern uchar (*rgb524mnxi)(Vga*, int);
416 extern void (*rgb524mnxo)(Vga*, int, uchar);
417 extern Ctlr rgb524mn;
430 extern Ctlr s3generic;
433 extern Ctlr bt485hwgc;
434 extern Ctlr rgb524hwgc;
436 extern Ctlr tvp3020hwgc;
437 extern Ctlr tvp3026hwgc;
447 extern Ctlr t2r4hwgc;
450 extern void trio64clock(Vga*, Ctlr*);
454 extern uchar tvp3020i(uchar);
455 extern uchar tvp3020xi(uchar);
456 extern void tvp3020o(uchar, uchar);
457 extern void tvp3020xo(uchar, uchar);
464 extern Ctlr tvp3025clock;
467 extern uchar tvp3026xi(uchar);
468 extern void tvp3026xo(uchar, uchar);
472 extern Ctlr tvp3026clock;
475 extern uchar vgai(long);
476 extern uchar vgaxi(long, uchar);
477 extern void vgao(long, uchar);
478 extern void vgaxo(long, uchar, uchar);
483 extern Ctlr softhwgc; /* has to go somewhere */
484 extern int dbvesa(Vga*);
485 extern Mode *dbvesamode(Vga*,char*);
486 extern void vesatextmode(void);
489 extern Mode *vesamodes[];
495 extern Ctlr vision864;
498 extern Ctlr vision964;
501 extern Ctlr vision968;
505 extern Ctlr vmwarehwgc;
512 extern Ctlr mga4xxhwgc;
514 #pragma varargck argpos error 1
515 #pragma varargck argpos trace 1
516 #pragma varargck argpos mkattr 3