9 * IBM RGB52x and compatibles.
10 * High Performance Palette DAC.
12 uchar (*rgb524mnxi)(Vga*, int);
13 void (*rgb524mnxo)(Vga*, int, uchar);
15 enum { /* index registers */
20 PaletteControl = 0x07,
24 Pixel16Control = 0x0C,
25 Pixel32Control = 0x0E,
37 clock(Vga* vga, Ctlr*, ulong fref, ulong maxpclk)
40 ulong df, f, m, n, vrf;
43 for(df = 0; df < 4; df++){
44 for(m = 2; m < 64; m++){
45 for(n = 2; n < 32; n++){
50 if(vrf > maxpclk/4 || vrf < 1000000)
56 if(vrf > maxpclk/2 || vrf < 1000000)
62 if(vrf > maxpclk || vrf < 1000000)
68 if(vrf > maxpclk || vrf < 1000000)
90 init(Vga* vga, Ctlr* ctlr)
96 * Part comes in at least a -170MHz speed-grade.
99 if(p = strrchr(ctlr->name, '-'))
100 maxpclk = strtoul(p+1, 0, 0) * 1000000;
103 * If we don't already have a desired pclk,
104 * take it from the mode.
105 * Check it's within range.
108 vga->f[0] = vga->mode->frequency;
109 if(vga->f[0] > maxpclk)
110 error("%s: invalid pclk - %ld\n", ctlr->name, vga->f[0]);
111 if(val = dbattr(vga->attr, "rgb524mnrefclk"))
112 fref = strtol(val, 0, 0);
117 * Initialise the PLL parameters.
120 clock(vga, ctlr, fref, maxpclk);
127 load(Vga* vga, Ctlr* ctlr)
132 if(rgb524mnxi == nil && rgb524mnxo == nil)
133 error("%s->load: no access routines\n", ctlr->name);
136 * Set the m/n values for the desired frequency and
137 * set pixel control to use compatibility mode with
138 * internal frequency select using the specified set
141 rgb524mnxo(vga, M0+vga->i[0]*2, vga->d[0]<<6|vga->m[0]);
142 rgb524mnxo(vga, N0+vga->i[0]*2, vga->n[0]);
143 rgb524mnxo(vga, PLLControl2, vga->i[0]);
144 rgb524mnxo(vga, PLLControl1, 0x03);
147 * Enable pixel programming in MiscClock;
148 * nothing to do in MiscControl1;
149 * set internal PLL clock and !vga in MiscControl2;
151 x = rgb524mnxi(vga, MiscClock) & ~0x01;
153 rgb524mnxo(vga, MiscClock, x);
155 x = rgb524mnxi(vga, MiscControl2) & ~0x41;
157 rgb524mnxo(vga, MiscControl2, x);
163 if(vga->mode->hsync == '+')
165 if(vga->mode->vsync == '+')
167 rgb524mnxo(vga, SyncControl, x);
168 if(val = dbattr(vga->mode->attr, "hsyncdelay"))
169 hsyncdelay = strtol(val, 0, 0);
170 else switch(vga->mode->z){
183 rgb524mnxo(vga, HSyncControl, hsyncdelay);
185 rgb524mnxo(vga, SYSCLKM, 0x50);
186 rgb524mnxo(vga, SYSCLKN, 0x08);
188 //rgb524mnxo(vga, SYSCLKM, 0x6F);
189 //rgb524mnxo(vga, SYSCLKN, 0x0F);
193 * Set the palette for the desired format.
194 * ****NEEDS WORK FOR OTHER THAN 8-BITS****
196 rgb524mnxo(vga, PaletteControl, 0x00);
197 switch(vga->mode->z){
199 rgb524mnxo(vga, PixelFormat, 0x03);
200 rgb524mnxo(vga, Pixel8Control, 0x00);
203 rgb524mnxo(vga, PixelFormat, 0x04);
204 rgb524mnxo(vga, Pixel16Control, 0xC4);
206 rgb524mnxo(vga, PixelFormat, 0x04);
207 rgb524mnxo(vga, Pixel16Control, 0xC6);
210 rgb524mnxo(vga, PixelFormat, 0x06);
211 rgb524mnxo(vga, Pixel32Control, 0x03);
217 dumpclock(Vga*, Ctlr* ctlr, ulong fref, ulong m, ulong n, char* name)
240 printitem(ctlr->name, name);
241 Bprint(&stdout, "%12lud\n", f);
245 dump(Vga* vga, Ctlr* ctlr)
252 if(rgb524mnxi == nil && rgb524mnxo == nil)
253 error("%s->dump: no access routines\n", ctlr->name);
255 printitem(ctlr->name, "index00");
256 for(i = 0x00; i < 0x0F; i++){
257 x[i] = rgb524mnxi(vga, i);
260 printitem(ctlr->name, "index10");
261 for(i = 0x10; i < 0x18; i++){
262 x[i] = rgb524mnxi(vga, i);
265 printitem(ctlr->name, "index20");
266 for(i = 0x20; i < 0x30; i++){
267 x[i] = rgb524mnxi(vga, i);
270 printitem(ctlr->name, "index30");
271 for(i = 0x30; i < 0x39; i++){
272 x[i] = rgb524mnxi(vga, i);
275 printitem(ctlr->name, "index40");
276 for(i = 0x40; i < 0x49; i++){
277 x[i] = rgb524mnxi(vga, i);
280 printitem(ctlr->name, "index60");
281 for(i = 0x60; i < 0x63; i++){
282 x[i] = rgb524mnxi(vga, i);
285 printitem(ctlr->name, "index70");
286 for(i = 0x70; i < 0x73; i++){
287 x[i] = rgb524mnxi(vga, i);
290 printitem(ctlr->name, "index8E");
291 for(i = 0x8E; i < 0x92; i++){
292 x[i] = rgb524mnxi(vga, i);
296 if(val = dbattr(vga->attr, "rgb524mnrefclk"))
297 fref = strtol(val, 0, 0);
300 if(!(x[SYSCLKControl] & 0x04))
301 dumpclock(vga, ctlr, fref, x[0x16], x[0x15], "sysclk");
302 fs = x[PLLControl1] & 0x07;
303 if(fs == 0x01 || fs == 0x03){
305 i = ((vga->misc>>2) & 0x03)*2;
307 i = x[PLLControl2] & 0x07;
308 dumpclock(vga, ctlr, fref, x[M0+i*2], x[N0+i*2], "pllclk");
313 "rgb524mn", /* name */