10 * For now assumed to be hooked to either a Tseng Labs ET4000-W32p
11 * (Hercules Dynamite Power, the Hercules generates RS2 using CLK3)
12 * or an ARK2000pv (Diamond Stealth64 Graphics 2001).
15 setrs2(Vga* vga, Ctlr* ctlr)
20 if(strncmp(vga->ctlr->name, "et4000-w32", 10) == 0){
21 rs2 = vgaxi(Crtx, 0x31);
22 vgaxo(Crtx, 0x31, 0x40|rs2);
24 else if(strncmp(vga->ctlr->name, "ark2000pv", 9) == 0){
25 rs2 = vgaxi(Seqx, 0x1C);
26 vgaxo(Seqx, 0x1C, 0x80|rs2);
29 error("%s: not configured for %s\n", vga->ctlr->name, ctlr->name);
35 restorers2(Vga* vga, uchar rs2)
37 if(strncmp(vga->ctlr->name, "et4000-w32", 10) == 0)
38 vgaxo(Crtx, 0x31, rs2);
39 else if(strncmp(vga->ctlr->name, "ark2000pv", 9) == 0)
40 vgaxo(Seqx, 0x1C, rs2);
44 options(Vga*, Ctlr* ctlr)
46 ctlr->flag |= Hpclk2x8|Foptions;
50 clock(Vga* vga, Ctlr* ctlr)
53 double fmin, fmax, t, tok;
56 * The PLL frequency is defined by:
58 * Fout = ------------ x Fref
60 * where M, N and R have the following contraints:
61 * 1) 2MHz < Fref < 32MHz
63 * 600KHz < ----- <= 8Mhz
66 * 60MHz <= ------------ <= 270MHz
69 * 5) 1 <= M <= 127, 1 <= N <= 31, 0 <= R <= 3
71 * First determine R by finding the highest value
73 * 2**R x Fout <= 270Mhz
74 * The datasheet says that if the multiplexed 16-bit
75 * pseudo-colour mode is used then N2 (vga->r) must
78 if(ctlr->flag & Upclk2x8)
82 for(r = 0; r <= 3; r++){
84 if(60000000 < f && f <= 270000000)
88 error("%s: pclk %lud out of range\n",
89 ctlr->name, vga->f[0]);
93 * Now find the closest match for M and N.
94 * Lower values of M and N give better noise rejection.
96 fmin = vga->f[0]*0.995;
97 fmax = vga->f[0]*1.005;
99 for(n = 31; n >= 1; n--){
101 if(600000 >= t || t > 8000000)
104 t = vga->f[0]*(n+2)*(1<<vga->r[0]);
111 t /= (n+2)*(1<<vga->r[0]);
113 if(fmin <= t && t < fmax){
121 error("%s: pclk %lud out of range\n", ctlr->name, vga->f[0]);
125 init(Vga* vga, Ctlr* ctlr)
131 * Part comes in -135, -110 and -80MHz speed-grades.
134 if(p = strrchr(ctlr->name, '-'))
135 pclk = strtoul(p+1, 0, 0) * 1000000;
138 * If we don't already have a desired pclk,
139 * take it from the mode.
140 * Check it's within range.
143 vga->f[0] = vga->mode->frequency;
145 error("%s: invalid pclk - %ld\n", ctlr->name, vga->f[0]);
148 * Determine whether to use 2x8-bit mode or not.
149 * If yes and the clock has already been initialised,
150 * initialise it again.
152 if(vga->ctlr && (vga->ctlr->flag & Hpclk2x8) && vga->mode->z == 8 && vga->f[0] >= pclk/2){
154 resyncinit(vga, ctlr, Upclk2x8, 0);
158 * Clock bits. If the desired video clock is
159 * one of the two standard VGA clocks it can just be
160 * set using bits <3:2> of vga->misc, otherwise we
161 * need to programme the DCLK PLL.
164 if(vga->f[0] == VgaFreq0)
166 else if(vga->f[0] == VgaFreq1){
172 * Initialise the PLL parameters.
173 * Use CLK0 f7 internal clock (there are only 3
174 * clock-select bits).
184 load(Vga* vga, Ctlr* ctlr)
186 uchar rs2, mode, pll;
188 rs2 = setrs2(vga, ctlr);
191 * Put the chip into snooze mode,
195 outportb(Pixmask, 0x01);
197 if(ctlr->flag & Upclk2x8)
201 * If necessary, set the PLL parameters for CLK0 f7
202 * and make sure the PLL control register selects the
203 * correct clock. Preserve the memory clock setting.
205 outportb(PaddrR, 0x0E);
206 pll = inportb(Pdata) & 0x10;
207 if(vga->i[0] == 0x07){
208 outportb(PaddrW, vga->i[0]);
209 outportb(Pdata, vga->m[0]);
210 outportb(Pdata, (vga->r[0]<<5)|vga->n[0]);
213 outportb(PaddrW, 0x0E);
214 outportb(Pdata, pll);
215 outportb(Pixmask, mode);
217 restorers2(vga, rs2);
222 dump(Vga* vga, Ctlr* ctlr)
229 rs2 = setrs2(vga, ctlr);
231 printitem(ctlr->name, "command");
232 printreg(inportb(Pixmask));
234 outportb(PaddrR, 0x00);
235 for(i = 0; i < 0x0E; i++){
236 sprint(buf, "f%X m n", i);
237 printitem(ctlr->name, buf);
245 f /= 1<<((n>>5) & 0x03);
246 Bprint(&stdout, "%12lud", f);
248 printitem(ctlr->name, "control");
249 printreg(inportb(Pdata));
251 restorers2(vga, rs2);
255 "ics534x", /* name */
257 options, /* options */