5 { ATEXT, C_LEXT, C_NONE, C_LCON, 0, 0, 0 },
6 { ATEXT, C_LEXT, C_REG, C_LCON, 0, 0, 0 },
7 { ATEXT, C_ADDR, C_NONE, C_LCON, 0, 0, 0 },
8 { ATEXT, C_ADDR, C_REG, C_LCON, 0, 0, 0 },
10 /* arithmetic operations */
11 { AADD, C_REG, C_REG, C_REG, 1, 4, 0 },
12 { AADD, C_REG, C_NONE, C_REG, 1, 4, 0 },
13 { AADC, C_REG, C_REG, C_REG, 1, 4, 0 },
14 { AADC, C_REG, C_NONE, C_REG, 1, 4, 0 },
15 { ANEG, C_REG, C_NONE, C_REG, 25, 4, 0 },
16 { ANGC, C_REG, C_NONE, C_REG, 17, 4, 0 },
17 { ACMP, C_REG, C_RSP, C_NONE, 1, 4, 0 },
19 { AADD, C_ADDCON, C_RSP, C_RSP, 2, 4, 0 },
20 { AADD, C_ADDCON, C_NONE, C_RSP, 2, 4, 0 },
21 { ACMP, C_ADDCON, C_RSP, C_NONE, 2, 4, 0 },
23 { AADD, C_LCON, C_REG, C_REG, 13, 8, 0, LFROM },
24 { AADD, C_LCON, C_NONE, C_REG, 13, 8, 0, LFROM },
25 { ACMP, C_LCON, C_REG, C_NONE, 13, 8, 0, LFROM },
27 { AADD, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
28 { AADD, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
29 { AMVN, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
30 { ACMP, C_SHIFT,C_REG, C_NONE, 3, 4, 0 },
31 { ANEG, C_SHIFT,C_NONE, C_REG, 26, 4, 0 },
33 { AADD, C_REG, C_RSP, C_RSP, 27, 4, 0 },
34 { AADD, C_REG, C_NONE, C_RSP, 27, 4, 0 },
35 { AADD, C_EXTREG,C_RSP, C_RSP, 27, 4, 0 },
36 { AADD, C_EXTREG,C_NONE, C_RSP, 27, 4, 0 },
37 { AMVN, C_EXTREG,C_NONE, C_RSP, 27, 4, 0 },
38 { ACMP, C_EXTREG,C_RSP, C_NONE, 27, 4, 0 },
40 { AADD, C_REG, C_REG, C_REG, 1, 4, 0 },
41 { AADD, C_REG, C_NONE, C_REG, 1, 4, 0 },
43 /* logical operations */
44 { AAND, C_REG, C_REG, C_REG, 1, 4, 0 },
45 { AANDW, C_REG, C_REG, C_REG, 1, 4, 0 },
46 { AAND, C_REG, C_NONE, C_REG, 1, 4, 0 },
47 { AANDW, C_REG, C_NONE, C_REG, 1, 4, 0 },
48 { ABIC, C_REG, C_REG, C_REG, 1, 4, 0 },
49 { ABICW, C_REG, C_REG, C_REG, 1, 4, 0 },
50 { ABIC, C_REG, C_NONE, C_REG, 1, 4, 0 },
51 { ABICW, C_REG, C_NONE, C_REG, 1, 4, 0 },
53 { AAND, C_BITCON64,C_REG,C_REG, 53, 4, 0 },
54 { AANDW, C_BITCON32,C_REG,C_REG, 53, 4, 0 },
55 { AAND, C_BITCON64,C_NONE,C_REG, 53, 4, 0 },
56 { AANDW, C_BITCON32,C_NONE,C_REG, 53, 4, 0 },
58 { AAND, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
59 { AANDW, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
60 { AAND, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
61 { AANDW, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
62 { ABIC, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
63 { ABICW, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
64 { ABIC, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
65 { ABICW, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
67 { AAND, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
68 { AANDW, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
69 { AAND, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
70 { AANDW, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
71 { ABIC, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
72 { ABICW, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
73 { ABIC, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
74 { ABICW, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
77 { AMOV, C_RSP, C_NONE, C_RSP, 24, 4, 0 },
78 { AMVN, C_REG, C_NONE, C_REG, 24, 4, 0 },
79 { AMOVB, C_REG, C_NONE, C_REG, 45, 4, 0 },
80 { AMOVBU, C_REG, C_NONE, C_REG, 45, 4, 0 },
81 { AMOVH, C_REG, C_NONE, C_REG, 45, 4, 0 }, /* also MOVHU */
82 { AMOVW, C_REG, C_NONE, C_REG, 45, 4, 0 }, /* also MOVWU */
83 /* TO DO: MVN C_SHIFT */
85 /* MOVs that become MOVK/MOVN/MOVZ/ADD/SUB/OR */
86 { AMOVW, C_MOVCON, C_NONE, C_REG, 32, 4, 0 },
87 { AMOV, C_MOVCON, C_NONE, C_REG, 32, 4, 0 },
88 // { AMOVW, C_ADDCON, C_NONE, C_REG, 2, 4, 0 },
89 // { AMOV, C_ADDCON, C_NONE, C_REG, 2, 4, 0 },
91 { AMOV, C_BITCON64, C_NONE, C_REG, 53, 4, 0 },
92 { AMOVW, C_BITCON32, C_NONE, C_REG, 53, 4, 0 },
94 { AMOVK, C_LCON, C_NONE, C_REG, 33, 4, 0 },
96 { AMOV, C_AECON,C_NONE, C_REG, 4, 4, REGSB },
97 { AMOV, C_AACON,C_NONE, C_REG, 4, 4, REGSP },
99 { ASDIV, C_REG, C_NONE, C_REG, 1, 4, 0 },
100 { ASDIV, C_REG, C_REG, C_REG, 1, 4, 0 },
102 { AB, C_NONE, C_NONE, C_SBRA, 5, 4, 0 },
103 { ABL, C_NONE, C_NONE, C_SBRA, 5, 4, 0 },
105 { AB, C_NONE, C_NONE, C_ZOREG, 6, 4, 0 },
106 { ABL, C_NONE, C_NONE, C_ZOREG, 6, 4, 0 },
107 { ARET, C_NONE, C_NONE, C_REG, 6, 4, 0 },
108 { ARET, C_NONE, C_NONE, C_ZOREG, 6, 4, 0 },
110 { AADRP, C_SBRA, C_NONE, C_REG, 60, 4, 0 },
111 { AADR, C_SBRA, C_NONE, C_REG, 61, 4, 0 },
113 { ABFM, C_LCON, C_REG, C_REG, 42, 4, 0 },
114 { ABFI, C_LCON, C_REG, C_REG, 43, 4, 0 },
116 { AEXTR, C_LCON, C_REG, C_REG, 44, 4, 0 },
117 { ASXTB, C_REG, C_NONE, C_REG, 45, 4, 0 },
118 { ACLS, C_REG, C_NONE, C_REG, 46, 4, 0 },
120 { ABEQ, C_NONE, C_NONE, C_SBRA, 7, 4, 0 },
122 { ALSL, C_LCON, C_REG, C_REG, 8, 4, 0 },
123 { ALSL, C_LCON, C_NONE, C_REG, 8, 4, 0 },
125 { ALSL, C_REG, C_NONE, C_REG, 9, 4, 0 },
126 { ALSL, C_REG, C_REG, C_REG, 9, 4, 0 },
128 { ASVC, C_NONE, C_NONE, C_LCON, 10, 4, 0 },
129 { ASVC, C_NONE, C_NONE, C_NONE, 10, 4, 0 },
131 { ADWORD, C_NONE, C_NONE, C_VCON, 11, 8, 0 },
132 { ADWORD, C_NONE, C_NONE, C_LEXT, 11, 8, 0 },
133 { ADWORD, C_NONE, C_NONE, C_ADDR, 11, 8, 0 },
135 { AWORD, C_NONE, C_NONE, C_LCON, 14, 4, 0 },
136 { AWORD, C_NONE, C_NONE, C_LEXT, 14, 4, 0 },
137 { AWORD, C_NONE, C_NONE, C_ADDR, 14, 4, 0 },
139 { AMOVW, C_LCON, C_NONE, C_REG, 12, 4, 0, LFROM },
140 { AMOV, C_LCON, C_NONE, C_REG, 12, 4, 0, LFROM },
142 { AMOVW, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO },
143 { AMOVB, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO },
144 { AMOVBU, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO },
145 { AMOVW, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM },
146 { AMOVBU, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM },
148 { AMUL, C_REG, C_REG, C_REG, 15, 4, 0 },
149 { AMUL, C_REG, C_NONE, C_REG, 15, 4, 0 },
150 { AMADD, C_REG, C_REG, C_REG, 15, 4, 0 },
152 { AREM, C_REG, C_REG, C_REG, 16, 8, 0 },
153 { AREM, C_REG, C_NONE, C_REG, 16, 8, 0 },
155 { ACSEL, C_COND, C_REG, C_REG, 18, 4, 0 }, /* from3 optional */
156 { ACSET, C_COND, C_NONE, C_REG, 18, 4, 0 },
158 { ACCMN, C_COND, C_REG, C_LCON, 19, 4, 0 }, /* from3 either C_REG or C_LCON */
160 /* scaled 12-bit unsigned displacement store */
162 { AMOVB, C_REG, C_NONE, C_SEXT1, 20, 4, REGSB }, //
163 { AMOVB, C_REG, C_NONE, C_UAUTO4K, 20, 4, REGSP }, //
164 { AMOVB, C_REG, C_NONE, C_UOREG4K, 20, 4, 0 }, //
165 { AMOVBU, C_REG, C_NONE, C_SEXT1, 20, 4, REGSB }, //
166 { AMOVBU, C_REG, C_NONE, C_UAUTO4K, 20, 4, REGSP }, //
167 { AMOVBU, C_REG, C_NONE, C_UOREG4K, 20, 4, 0 }, //
169 { AMOVH, C_REG, C_NONE, C_SEXT2, 20, 4, REGSB }, //
170 { AMOVH, C_REG, C_NONE, C_UAUTO8K, 20, 4, REGSP }, //
171 { AMOVH, C_REG, C_NONE, C_ZOREG, 20, 4, 0 }, //
172 { AMOVH, C_REG, C_NONE, C_UOREG8K, 20, 4, 0 }, //
174 { AMOVW, C_REG, C_NONE, C_SEXT4, 20, 4, REGSB }, //
175 { AMOVW, C_REG, C_NONE, C_UAUTO16K, 20, 4, REGSP }, //
176 { AMOVW, C_REG, C_NONE, C_ZOREG, 20, 4, 0 }, //
177 { AMOVW, C_REG, C_NONE, C_UOREG16K, 20, 4, 0 }, //
179 /* unscaled 9-bit signed displacement store */
180 { AMOVB, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
181 { AMOVB, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
182 { AMOVBU, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
183 { AMOVBU, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
185 { AMOVH, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
186 { AMOVH, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
187 { AMOVW, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
188 { AMOVW, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
190 { AMOV, C_REG, C_NONE, C_SEXT8, 20, 4, REGSB },
191 { AMOV, C_REG, C_NONE, C_UAUTO32K, 20, 4, REGSP },
192 { AMOV, C_REG, C_NONE, C_ZOREG, 20, 4, 0 },
193 { AMOV, C_REG, C_NONE, C_UOREG32K, 20, 4, 0 },
195 { AMOV, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
196 { AMOV, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
198 /* short displacement load */
200 { AMOVB, C_SEXT1, C_NONE, C_REG, 21, 4, REGSB }, //
201 { AMOVB, C_UAUTO4K,C_NONE, C_REG, 21, 4, REGSP }, //
202 { AMOVB, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP }, //
203 { AMOVB, C_ZOREG,C_NONE, C_REG, 21, 4, 0 }, //
204 { AMOVB, C_UOREG4K,C_NONE, C_REG, 21, 4, REGSP }, //
205 { AMOVB, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP }, //
207 { AMOVBU, C_SEXT1, C_NONE, C_REG, 21, 4, REGSB }, //
208 { AMOVBU, C_UAUTO4K,C_NONE, C_REG, 21, 4, REGSP }, //
209 { AMOVBU, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP }, //
210 { AMOVBU, C_ZOREG,C_NONE, C_REG, 21, 4, 0 }, //
211 { AMOVBU, C_UOREG4K,C_NONE, C_REG, 21, 4, REGSP }, //
212 { AMOVBU, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP }, //
214 { AMOVH, C_SEXT2, C_NONE, C_REG, 21, 4, REGSB }, //
215 { AMOVH, C_UAUTO8K,C_NONE, C_REG, 21, 4, REGSP }, //
216 { AMOVH, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP }, //
217 { AMOVH, C_ZOREG,C_NONE, C_REG, 21, 4, 0 }, //
218 { AMOVH, C_UOREG8K,C_NONE, C_REG, 21, 4, REGSP }, //
219 { AMOVH, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP }, //
221 { AMOVW, C_SEXT4, C_NONE, C_REG, 21, 4, REGSB }, //
222 { AMOVW, C_UAUTO16K,C_NONE, C_REG, 21, 4, REGSP }, //
223 { AMOVW, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP }, //
224 { AMOVW, C_ZOREG,C_NONE, C_REG, 21, 4, 0 }, //
225 { AMOVW, C_UOREG16K,C_NONE, C_REG, 21, 4, REGSP }, //
226 { AMOVW, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP }, //
228 { AMOV, C_SEXT8, C_NONE, C_REG, 21, 4, REGSB },
229 { AMOV, C_UAUTO32K,C_NONE, C_REG, 21, 4, REGSP },
230 { AMOV, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP },
231 { AMOV, C_ZOREG,C_NONE, C_REG, 21, 4, 0 },
232 { AMOV, C_UOREG32K,C_NONE, C_REG, 21, 4, REGSP },
233 { AMOV, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP },
235 /* large displacement store */
236 { AMOVB, C_REG, C_NONE, C_LEXT, 30, 8, REGSB, LTO },
237 { AMOVB, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO },
238 { AMOVB, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO },
239 { AMOVBU, C_REG, C_NONE, C_LEXT, 30, 8, REGSB, LTO },
240 { AMOVBU, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO },
241 { AMOVBU, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO },
243 { AMOVH, C_REG, C_NONE, C_LEXT, 30, 8, REGSB, LTO },
244 { AMOVH, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO },
245 { AMOVH, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO },
247 { AMOVW, C_REG, C_NONE, C_LEXT, 30, 8, REGSB, LTO },
248 { AMOVW, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO },
249 { AMOVW, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO },
251 { AMOV, C_REG, C_NONE, C_LEXT, 30, 8, REGSB, LTO },
252 { AMOV, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO },
253 { AMOV, C_REG, C_NONE, C_LOREG, 30, 8, 0, LTO },
255 /* large displacement load */
256 { AMOVB, C_LEXT, C_NONE, C_REG, 31, 8, REGSB, LFROM },
257 { AMOVB, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP, LFROM },
258 { AMOVB, C_LOREG,C_NONE, C_REG, 31, 8, 0, LFROM },
259 { AMOVBU, C_LEXT, C_NONE, C_REG, 31, 8, REGSB, LFROM },
260 { AMOVBU, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP, LFROM },
261 { AMOVBU, C_LOREG,C_NONE, C_REG, 31, 8, 0, LFROM },
263 { AMOVH, C_LEXT, C_NONE, C_REG, 31, 8, REGSB, LFROM },
264 { AMOVH, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP, LFROM },
265 { AMOVH, C_LOREG,C_NONE, C_REG, 31, 8, 0, LFROM },
267 { AMOVW, C_LEXT, C_NONE, C_REG, 31, 8, REGSB, LFROM },
268 { AMOVW, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP, LFROM },
269 { AMOVW, C_LOREG,C_NONE, C_REG, 31, 8, 0, LFROM },
271 { AMOV, C_LEXT, C_NONE, C_REG, 31, 8, REGSB, LFROM },
272 { AMOV, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP, LFROM },
273 { AMOV, C_LOREG,C_NONE, C_REG, 31, 8, 0, LFROM },
275 /* load large effective stack address (load large offset and add) */
276 { AMOV, C_LACON,C_NONE, C_REG, 34, 8, REGSP, LFROM },
278 /* pre/post-indexed load (unscaled, signed 9-bit offset) */
279 { AMOV, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
280 { AMOVW, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
281 { AMOVH, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
282 { AMOVB, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
283 { AMOVBU, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
284 { AFMOVS, C_XPOST, C_NONE, C_FREG, 22, 4, 0 },
285 { AFMOVD, C_XPOST, C_NONE, C_FREG, 22, 4, 0 },
287 { AMOV, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
288 { AMOVW, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
289 { AMOVH, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
290 { AMOVB, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
291 { AMOVBU, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
292 { AFMOVS, C_XPRE, C_NONE, C_FREG, 22, 4, 0 },
293 { AFMOVD, C_XPRE, C_NONE, C_FREG, 22, 4, 0 },
295 /* pre/post-indexed store (unscaled, signed 9-bit offset) */
296 { AMOV, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
297 { AMOVW, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
298 { AMOVH, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
299 { AMOVB, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
300 { AMOVBU, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
301 { AFMOVS, C_FREG, C_NONE, C_XPOST, 23, 4, 0 },
302 { AFMOVD, C_FREG, C_NONE, C_XPOST, 23, 4, 0 },
304 { AMOV, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
305 { AMOVW, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
306 { AMOVH, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
307 { AMOVB, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
308 { AMOVBU, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
309 { AFMOVS, C_FREG, C_NONE, C_XPRE, 23, 4, 0 },
310 { AFMOVD, C_FREG, C_NONE, C_XPRE, 23, 4, 0 },
312 { AMOVP, C_PPAUTO, C_REG, C_REG, 66, 4, 0 },
313 { AMOVP, C_PPOREG, C_REG, C_REG, 66, 4, 0 },
314 { AMOVP, C_NPAUTO, C_REG, C_REG, 66, 4, 0 },
315 { AMOVP, C_NPOREG, C_REG, C_REG, 66, 4, 0 },
316 { AMOVP, C_XPOST, C_REG, C_REG, 66, 4, 0 },
317 { AMOVP, C_XPRE, C_REG, C_REG, 66, 4, 0 },
319 { AMOVP, C_REG, C_REG, C_PPAUTO, 67, 4, 0 },
320 { AMOVP, C_REG, C_REG, C_PPOREG, 67, 4, 0 },
321 { AMOVP, C_REG, C_REG, C_NPAUTO, 67, 4, 0 },
322 { AMOVP, C_REG, C_REG, C_NPOREG, 67, 4, 0 },
323 { AMOVP, C_REG, C_REG, C_XPOST, 67, 4, 0 },
324 { AMOVP, C_REG, C_REG, C_XPRE, 67, 4, 0 },
327 { AMOV, C_SPR, C_NONE, C_REG, 35, 4, 0 },
328 { AMRS, C_SPR, C_NONE, C_REG, 35, 4, 0 },
330 { AMOV, C_REG, C_NONE, C_SPR, 36, 4, 0 },
331 { AMSR, C_REG, C_NONE, C_SPR, 36, 4, 0 },
333 { AMOV, C_LCON, C_NONE, C_SPR, 37, 4, 0 },
334 { AMSR, C_LCON, C_NONE, C_SPR, 37, 4, 0 },
336 { AERET, C_NONE, C_NONE, C_NONE, 41, 4, 0 },
338 { AFMOVS, C_FREG, C_NONE, C_SEXT4, 20, 4, REGSB },
339 { AFMOVS, C_FREG, C_NONE, C_UAUTO16K, 20, 4, REGSP },
340 { AFMOVS, C_FREG, C_NONE, C_NSAUTO, 20, 4, REGSP },
341 { AFMOVS, C_FREG, C_NONE, C_ZOREG, 20, 4, 0 },
342 { AFMOVS, C_FREG, C_NONE, C_UOREG16K, 20, 4, 0 },
343 { AFMOVS, C_FREG, C_NONE, C_NSOREG, 20, 4, 0 },
345 { AFMOVD, C_FREG, C_NONE, C_SEXT8, 20, 4, REGSB },
346 { AFMOVD, C_FREG, C_NONE, C_UAUTO32K, 20, 4, REGSP },
347 { AFMOVD, C_FREG, C_NONE, C_NSAUTO, 20, 4, REGSP },
348 { AFMOVD, C_FREG, C_NONE, C_ZOREG, 20, 4, 0 },
349 { AFMOVD, C_FREG, C_NONE, C_UOREG32K, 20, 4, 0 },
350 { AFMOVD, C_FREG, C_NONE, C_NSOREG, 20, 4, 0 },
352 { AFMOVS, C_SEXT4, C_NONE, C_FREG, 21, 4, REGSB },
353 { AFMOVS, C_UAUTO16K,C_NONE, C_FREG, 21, 4, REGSP },
354 { AFMOVS, C_NSAUTO,C_NONE, C_FREG, 21, 4, REGSP },
355 { AFMOVS, C_ZOREG,C_NONE, C_FREG, 21, 4, 0 },
356 { AFMOVS, C_UOREG16K,C_NONE, C_FREG, 21, 4, 0 },
357 { AFMOVS, C_NSOREG,C_NONE, C_FREG, 21, 4, 0 },
359 { AFMOVD, C_SEXT8, C_NONE, C_FREG, 21, 4, REGSB },
360 { AFMOVD, C_UAUTO32K,C_NONE, C_FREG, 21, 4, REGSP },
361 { AFMOVD, C_NSAUTO,C_NONE, C_FREG, 21, 4, REGSP },
362 { AFMOVD, C_ZOREG,C_NONE, C_FREG, 21, 4, 0 },
363 { AFMOVD, C_UOREG32K,C_NONE, C_FREG, 21, 4, 0 },
364 { AFMOVD, C_NSOREG,C_NONE, C_FREG, 21, 4, 0 },
366 { AFMOVS, C_FREG, C_NONE, C_LEXT, 30, 8, REGSB, LTO },
367 { AFMOVS, C_FREG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO },
368 { AFMOVS, C_FREG, C_NONE, C_LOREG, 30, 8, 0, LTO },
370 { AFMOVD, C_FREG, C_NONE, C_LEXT, 30, 8, REGSB, LTO },
371 { AFMOVD, C_FREG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO },
372 { AFMOVD, C_FREG, C_NONE, C_LOREG, 30, 8, 0, LTO },
374 { AFMOVS, C_LEXT, C_NONE, C_FREG, 31, 8, REGSB, LFROM },
375 { AFMOVS, C_LAUTO,C_NONE, C_FREG, 31, 8, REGSP, LFROM },
376 { AFMOVS, C_LOREG,C_NONE, C_FREG, 31, 8, 0, LFROM },
378 { AFMOVD, C_LEXT, C_NONE, C_FREG, 31, 8, REGSB, LFROM },
379 { AFMOVD, C_LAUTO,C_NONE, C_FREG, 31, 8, REGSP, LFROM },
380 { AFMOVD, C_LOREG,C_NONE, C_FREG, 31, 8, 0, LFROM },
382 { AFMOVS, C_FREG, C_NONE, C_ADDR, 64, 8, 0, LTO },
383 { AFMOVS, C_ADDR, C_NONE, C_FREG, 65, 8, 0, LFROM },
385 { AFADDS, C_FREG, C_NONE, C_FREG, 54, 4, 0 },
386 { AFADDS, C_FREG, C_REG, C_FREG, 54, 4, 0 },
387 { AFADDS, C_FCON, C_NONE, C_FREG, 54, 4, 0 },
388 { AFADDS, C_FCON, C_REG, C_FREG, 54, 4, 0 },
390 { AFMOVS, C_FCON, C_NONE, C_FREG, 54, 4, 0 },
391 { AFMOVS, C_FREG, C_NONE, C_FREG, 54, 4, 0 },
392 { AFMOVD, C_FCON, C_NONE, C_FREG, 54, 4, 0 },
393 { AFMOVD, C_FREG, C_NONE, C_FREG, 54, 4, 0 },
395 { AFCVTZSD, C_FREG, C_NONE, C_REG, 29, 4, 0 },
396 { ASCVTFD, C_REG, C_NONE, C_FREG, 29, 4, 0 },
398 { AFCMPS, C_FREG, C_REG, C_NONE, 56, 4, 0 },
399 { AFCMPS, C_FCON, C_REG, C_NONE, 56, 4, 0 },
401 { AFCCMPS, C_COND, C_REG, C_LCON, 57, 4, 0 },
403 { AFCSELD, C_COND, C_REG, C_FREG, 18, 4, 0 },
405 { AFCVTSD, C_FREG, C_NONE, C_FREG, 29, 4, 0 },
407 { ACASE, C_REG, C_NONE, C_REG, 62, 4*4, 0 },
408 { ABCASE, C_NONE, C_NONE, C_SBRA, 63, 4, 0 },
410 { ACLREX, C_NONE, C_NONE, C_LCON, 38, 4, 0 },
411 { ACLREX, C_NONE, C_NONE, C_NONE, 38, 4, 0 },
413 { ACBZ, C_REG, C_NONE, C_SBRA, 39, 4, 0 },
414 { ATBZ, C_LCON, C_REG, C_SBRA, 40, 4, 0 },
416 { ASYS, C_LCON, C_NONE, C_NONE, 50, 4, 0 },
417 { ASYS, C_LCON, C_REG, C_NONE, 50, 4, 0 },
418 { ASYSL, C_LCON, C_NONE, C_REG, 50, 4, 0 },
420 { ADMB, C_LCON, C_NONE, C_NONE, 51, 4, 0 },
421 { AHINT, C_LCON, C_NONE, C_NONE, 52, 4, 0 },
423 { ALDXR, C_ZOREG, C_NONE, C_REG, 58, 4, 0 },
424 { ALDXP, C_ZOREG, C_REG, C_REG, 58, 4, 0 },
425 { ASTXR, C_REG, C_REG, C_ZOREG, 59, 4, 0 },
426 { ASTXP, C_REG, C_REG, C_ZOREG, 59, 4, 0 },
428 { AAESD, C_VREG, C_NONE, C_VREG, 29, 4, 0 },
429 { ASHA1C, C_VREG, C_REG, C_VREG, 1, 4, 0 },
431 { AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0 },