5 { ATEXT, C_LEXT, C_NONE, C_LCON, 0, 0, 0 },
6 { ATEXT, C_LEXT, C_REG, C_LCON, 0, 0, 0 },
7 { ATEXT, C_ADDR, C_NONE, C_LCON, 0, 0, 0 },
8 { ATEXT, C_ADDR, C_REG, C_LCON, 0, 0, 0 },
10 /* arithmetic operations */
11 { AADD, C_REG, C_REG, C_REG, 1, 4, 0 },
12 { AADD, C_REG, C_NONE, C_REG, 1, 4, 0 },
13 { AADC, C_REG, C_REG, C_REG, 1, 4, 0 },
14 { AADC, C_REG, C_NONE, C_REG, 1, 4, 0 },
15 { ANEG, C_REG, C_NONE, C_REG, 25, 4, 0 },
16 { ANGC, C_REG, C_NONE, C_REG, 17, 4, 0 },
17 { ACMP, C_REG, C_RSP, C_NONE, 1, 4, 0 },
19 { AADD, C_ADDCON, C_RSP, C_RSP, 2, 4, 0 },
20 { AADD, C_ADDCON, C_NONE, C_RSP, 2, 4, 0 },
21 { ACMP, C_ADDCON, C_RSP, C_NONE, 2, 4, 0 },
23 { AADD, C_LCON, C_REG, C_REG, 13, 8, 0, LFROM },
24 { AADD, C_LCON, C_NONE, C_REG, 13, 8, 0, LFROM },
25 { ACMP, C_LCON, C_REG, C_NONE, 13, 8, 0, LFROM },
27 { AADD, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
28 { AADD, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
29 { AMVN, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
30 { ACMP, C_SHIFT,C_REG, C_NONE, 3, 4, 0 },
31 { ANEG, C_SHIFT,C_NONE, C_REG, 26, 4, 0 },
33 { AADD, C_REG, C_RSP, C_RSP, 27, 4, 0 },
34 { AADD, C_REG, C_NONE, C_RSP, 27, 4, 0 },
35 { AADD, C_EXTREG,C_RSP, C_RSP, 27, 4, 0 },
36 { AADD, C_EXTREG,C_NONE, C_RSP, 27, 4, 0 },
37 { AMVN, C_EXTREG,C_NONE, C_RSP, 27, 4, 0 },
38 { ACMP, C_EXTREG,C_RSP, C_NONE, 27, 4, 0 },
40 { AADD, C_REG, C_REG, C_REG, 1, 4, 0 },
41 { AADD, C_REG, C_NONE, C_REG, 1, 4, 0 },
43 /* logical operations */
44 { AAND, C_REG, C_REG, C_REG, 1, 4, 0 },
45 { AAND, C_REG, C_NONE, C_REG, 1, 4, 0 },
46 { ABIC, C_REG, C_REG, C_REG, 1, 4, 0 },
47 { ABIC, C_REG, C_NONE, C_REG, 1, 4, 0 },
49 { AAND, C_BITCON, C_REG, C_REG, 53, 4, 0 },
50 { AAND, C_BITCON, C_NONE, C_REG, 53, 4, 0 },
51 { ABIC, C_BITCON, C_REG, C_REG, 53, 4, 0 },
52 { ABIC, C_BITCON, C_NONE, C_REG, 53, 4, 0 },
54 { AAND, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
55 { AAND, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
56 { ABIC, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
57 { ABIC, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
59 { AAND, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
60 { AAND, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
61 { ABIC, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
62 { ABIC, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
64 { AMOV, C_RSP, C_NONE, C_RSP, 24, 4, 0 },
65 { AMVN, C_REG, C_NONE, C_REG, 24, 4, 0 },
66 { AMOVB, C_REG, C_NONE, C_REG, 45, 4, 0 },
67 { AMOVBU, C_REG, C_NONE, C_REG, 45, 4, 0 },
68 { AMOVH, C_REG, C_NONE, C_REG, 45, 4, 0 }, /* also MOVHU */
69 { AMOVW, C_REG, C_NONE, C_REG, 45, 4, 0 }, /* also MOVWU */
70 /* TO DO: MVN C_SHIFT */
72 /* MOVs that become MOVK/MOVN/MOVZ/ADD/SUB/OR */
73 { AMOVW, C_MOVCON, C_NONE, C_REG, 32, 4, 0 },
74 { AMOV, C_MOVCON, C_NONE, C_REG, 32, 4, 0 },
75 // { AMOVW, C_ADDCON, C_NONE, C_REG, 2, 4, 0 },
76 // { AMOV, C_ADDCON, C_NONE, C_REG, 2, 4, 0 },
77 // { AMOVW, C_BITCON, C_NONE, C_REG, 53, 4, 0 },
78 // { AMOV, C_BITCON, C_NONE, C_REG, 53, 4, 0 },
80 { AMOVK, C_LCON, C_NONE, C_REG, 33, 4, 0 },
82 { AMOV, C_AECON,C_NONE, C_REG, 4, 4, REGSB },
83 { AMOV, C_AACON,C_NONE, C_REG, 4, 4, REGSP },
85 { ASDIV, C_REG, C_NONE, C_REG, 1, 4, 0 },
86 { ASDIV, C_REG, C_REG, C_REG, 1, 4, 0 },
88 { AB, C_NONE, C_NONE, C_SBRA, 5, 4, 0 },
89 { ABL, C_NONE, C_NONE, C_SBRA, 5, 4, 0 },
91 { AB, C_NONE, C_NONE, C_ZOREG, 6, 4, 0 },
92 { ABL, C_NONE, C_NONE, C_ZOREG, 6, 4, 0 },
93 { ARET, C_NONE, C_NONE, C_REG, 6, 4, 0 },
94 { ARET, C_NONE, C_NONE, C_ZOREG, 6, 4, 0 },
96 { AADRP, C_SBRA, C_NONE, C_REG, 60, 4, 0 },
97 { AADR, C_SBRA, C_NONE, C_REG, 61, 4, 0 },
99 { ABFM, C_LCON, C_REG, C_REG, 42, 4, 0 },
100 { ABFI, C_LCON, C_REG, C_REG, 43, 4, 0 },
102 { AEXTR, C_LCON, C_REG, C_REG, 44, 4, 0 },
103 { ASXTB, C_REG, C_NONE, C_REG, 45, 4, 0 },
104 { ACLS, C_REG, C_NONE, C_REG, 46, 4, 0 },
106 { ABEQ, C_NONE, C_NONE, C_SBRA, 7, 4, 0 },
108 { ALSL, C_LCON, C_REG, C_REG, 8, 4, 0 },
109 { ALSL, C_LCON, C_NONE, C_REG, 8, 4, 0 },
111 { ALSL, C_REG, C_NONE, C_REG, 9, 4, 0 },
112 { ALSL, C_REG, C_REG, C_REG, 9, 4, 0 },
114 { ASVC, C_NONE, C_NONE, C_LCON, 10, 4, 0 },
115 { ASVC, C_NONE, C_NONE, C_NONE, 10, 4, 0 },
117 { ADWORD, C_NONE, C_NONE, C_VCON, 11, 8, 0 },
118 { ADWORD, C_NONE, C_NONE, C_LEXT, 11, 8, 0 },
119 { ADWORD, C_NONE, C_NONE, C_ADDR, 11, 8, 0 },
121 { AWORD, C_NONE, C_NONE, C_LCON, 14, 4, 0 },
122 { AWORD, C_NONE, C_NONE, C_LEXT, 14, 4, 0 },
123 { AWORD, C_NONE, C_NONE, C_ADDR, 14, 4, 0 },
125 { AMOVW, C_LCON, C_NONE, C_REG, 12, 4, 0, LFROM },
126 { AMOV, C_LCON, C_NONE, C_REG, 12, 4, 0, LFROM },
128 { AMOVW, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO },
129 { AMOVB, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO },
130 { AMOVBU, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO },
131 { AMOVW, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM },
132 { AMOVBU, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM },
134 { AMUL, C_REG, C_REG, C_REG, 15, 4, 0 },
135 { AMUL, C_REG, C_NONE, C_REG, 15, 4, 0 },
136 { AMADD, C_REG, C_REG, C_REG, 15, 4, 0 },
138 { AREM, C_REG, C_REG, C_REG, 16, 8, 0 },
139 { AREM, C_REG, C_NONE, C_REG, 16, 8, 0 },
141 { ACSEL, C_COND, C_REG, C_REG, 18, 4, 0 }, /* from3 optional */
142 { ACSET, C_COND, C_NONE, C_REG, 18, 4, 0 },
144 { ACCMN, C_COND, C_REG, C_LCON, 19, 4, 0 }, /* from3 either C_REG or C_LCON */
146 /* scaled 12-bit unsigned displacement store */
148 { AMOVB, C_REG, C_NONE, C_SEXT1, 20, 4, REGSB }, //
149 { AMOVB, C_REG, C_NONE, C_UAUTO4K, 20, 4, REGSP }, //
150 { AMOVB, C_REG, C_NONE, C_UOREG4K, 20, 4, 0 }, //
151 { AMOVBU, C_REG, C_NONE, C_SEXT1, 20, 4, REGSB }, //
152 { AMOVBU, C_REG, C_NONE, C_UAUTO4K, 20, 4, REGSP }, //
153 { AMOVBU, C_REG, C_NONE, C_UOREG4K, 20, 4, 0 }, //
155 { AMOVH, C_REG, C_NONE, C_SEXT2, 20, 4, REGSB }, //
156 { AMOVH, C_REG, C_NONE, C_UAUTO8K, 20, 4, REGSP }, //
157 { AMOVH, C_REG, C_NONE, C_ZOREG, 20, 4, 0 }, //
158 { AMOVH, C_REG, C_NONE, C_UOREG8K, 20, 4, 0 }, //
160 { AMOVW, C_REG, C_NONE, C_SEXT4, 20, 4, REGSB }, //
161 { AMOVW, C_REG, C_NONE, C_UAUTO16K, 20, 4, REGSP }, //
162 { AMOVW, C_REG, C_NONE, C_ZOREG, 20, 4, 0 }, //
163 { AMOVW, C_REG, C_NONE, C_UOREG16K, 20, 4, 0 }, //
165 /* unscaled 9-bit signed displacement store */
166 { AMOVB, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
167 { AMOVB, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
168 { AMOVBU, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
169 { AMOVBU, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
171 { AMOVH, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
172 { AMOVH, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
173 { AMOVW, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
174 { AMOVW, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
176 { AMOV, C_REG, C_NONE, C_SEXT8, 20, 4, REGSB },
177 { AMOV, C_REG, C_NONE, C_UAUTO32K, 20, 4, REGSP },
178 { AMOV, C_REG, C_NONE, C_ZOREG, 20, 4, 0 },
179 { AMOV, C_REG, C_NONE, C_UOREG32K, 20, 4, 0 },
181 { AMOV, C_REG, C_NONE, C_NSOREG, 20, 4, 0 }, //
182 { AMOV, C_REG, C_NONE, C_NSAUTO, 20, 4, REGSP }, //
184 /* short displacement load */
186 { AMOVB, C_SEXT1, C_NONE, C_REG, 21, 4, REGSB }, //
187 { AMOVB, C_UAUTO4K,C_NONE, C_REG, 21, 4, REGSP }, //
188 { AMOVB, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP }, //
189 { AMOVB, C_ZOREG,C_NONE, C_REG, 21, 4, 0 }, //
190 { AMOVB, C_UOREG4K,C_NONE, C_REG, 21, 4, REGSP }, //
191 { AMOVB, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP }, //
193 { AMOVBU, C_SEXT1, C_NONE, C_REG, 21, 4, REGSB }, //
194 { AMOVBU, C_UAUTO4K,C_NONE, C_REG, 21, 4, REGSP }, //
195 { AMOVBU, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP }, //
196 { AMOVBU, C_ZOREG,C_NONE, C_REG, 21, 4, 0 }, //
197 { AMOVBU, C_UOREG4K,C_NONE, C_REG, 21, 4, REGSP }, //
198 { AMOVBU, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP }, //
200 { AMOVH, C_SEXT2, C_NONE, C_REG, 21, 4, REGSB }, //
201 { AMOVH, C_UAUTO8K,C_NONE, C_REG, 21, 4, REGSP }, //
202 { AMOVH, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP }, //
203 { AMOVH, C_ZOREG,C_NONE, C_REG, 21, 4, 0 }, //
204 { AMOVH, C_UOREG8K,C_NONE, C_REG, 21, 4, REGSP }, //
205 { AMOVH, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP }, //
207 { AMOVW, C_SEXT4, C_NONE, C_REG, 21, 4, REGSB }, //
208 { AMOVW, C_UAUTO16K,C_NONE, C_REG, 21, 4, REGSP }, //
209 { AMOVW, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP }, //
210 { AMOVW, C_ZOREG,C_NONE, C_REG, 21, 4, 0 }, //
211 { AMOVW, C_UOREG16K,C_NONE, C_REG, 21, 4, REGSP }, //
212 { AMOVW, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP }, //
214 { AMOV, C_SEXT8, C_NONE, C_REG, 21, 4, REGSB },
215 { AMOV, C_UAUTO32K,C_NONE, C_REG, 21, 4, REGSP },
216 { AMOV, C_NSAUTO,C_NONE, C_REG, 21, 4, REGSP },
217 { AMOV, C_ZOREG,C_NONE, C_REG, 21, 4, 0 },
218 { AMOV, C_UOREG32K,C_NONE, C_REG, 21, 4, REGSP },
219 { AMOV, C_NSOREG,C_NONE, C_REG, 21, 4, REGSP },
221 /* long displacement store */
222 { AMOVB, C_REG, C_NONE, C_LEXT, 30, 8, REGSB }, //
223 { AMOVB, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP }, //
224 { AMOVB, C_REG, C_NONE, C_LOREG, 30, 8, 0 }, //
225 { AMOVH, C_REG, C_NONE, C_LEXT, 30, 8, REGSB }, //
226 { AMOVH, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP }, //
227 { AMOVH, C_REG, C_NONE, C_LOREG, 30, 8, 0 }, //
228 { AMOVW, C_REG, C_NONE, C_LEXT, 30, 8, REGSB }, //
229 { AMOVW, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP }, //
230 { AMOVW, C_REG, C_NONE, C_LOREG, 30, 8, 0 }, //
231 { AMOV, C_REG, C_NONE, C_LEXT, 30, 8, REGSB }, //
232 { AMOV, C_REG, C_NONE, C_LAUTO, 30, 8, REGSP }, //
233 { AMOV, C_REG, C_NONE, C_LOREG, 30, 8, 0 }, //
235 /* long displacement load */
236 { AMOVB, C_LEXT, C_NONE, C_REG, 31, 8, REGSB }, //
237 { AMOVB, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP }, //
238 { AMOVB, C_LOREG,C_NONE, C_REG, 31, 8, 0 }, //
239 { AMOVB, C_LOREG,C_NONE, C_REG, 31, 8, 0 }, //
240 { AMOVH, C_LEXT, C_NONE, C_REG, 31, 8, REGSB }, //
241 { AMOVH, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP }, //
242 { AMOVH, C_LOREG,C_NONE, C_REG, 31, 8, 0 }, //
243 { AMOVH, C_LOREG,C_NONE, C_REG, 31, 8, 0 }, //
244 { AMOVW, C_LEXT, C_NONE, C_REG, 31, 8, REGSB }, //
245 { AMOVW, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP }, //
246 { AMOVW, C_LOREG,C_NONE, C_REG, 31, 8, 0 }, //
247 { AMOVW, C_LOREG,C_NONE, C_REG, 31, 8, 0 }, //
248 { AMOV, C_LEXT, C_NONE, C_REG, 31, 8, REGSB }, //
249 { AMOV, C_LAUTO,C_NONE, C_REG, 31, 8, REGSP }, //
250 { AMOV, C_LOREG,C_NONE, C_REG, 31, 8, 0 }, //
251 { AMOV, C_LOREG,C_NONE, C_REG, 31, 8, 0 }, //
253 /* load long effective stack address (load long offset and add) */
254 { AMOV, C_LACON,C_NONE, C_REG, 34, 8, REGSP, LFROM }, //
256 /* pre/post-indexed load (unscaled, signed 9-bit offset) */
257 { AMOV, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
258 { AMOVW, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
259 { AMOVH, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
260 { AMOVB, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
261 { AMOVBU, C_XPOST, C_NONE, C_REG, 22, 4, 0 },
262 { AFMOVS, C_XPOST, C_NONE, C_FREG, 22, 4, 0 },
263 { AFMOVD, C_XPOST, C_NONE, C_FREG, 22, 4, 0 },
265 { AMOV, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
266 { AMOVW, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
267 { AMOVH, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
268 { AMOVB, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
269 { AMOVBU, C_XPRE, C_NONE, C_REG, 22, 4, 0 },
270 { AFMOVS, C_XPRE, C_NONE, C_FREG, 22, 4, 0 },
271 { AFMOVD, C_XPRE, C_NONE, C_FREG, 22, 4, 0 },
273 /* pre/post-indexed store (unscaled, signed 9-bit offset) */
274 { AMOV, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
275 { AMOVW, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
276 { AMOVH, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
277 { AMOVB, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
278 { AMOVBU, C_REG, C_NONE, C_XPOST, 23, 4, 0 },
279 { AFMOVS, C_FREG, C_NONE, C_XPOST, 23, 4, 0 },
280 { AFMOVD, C_FREG, C_NONE, C_XPOST, 23, 4, 0 },
282 { AMOV, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
283 { AMOVW, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
284 { AMOVH, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
285 { AMOVB, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
286 { AMOVBU, C_REG, C_NONE, C_XPRE, 23, 4, 0 },
287 { AFMOVS, C_FREG, C_NONE, C_XPRE, 23, 4, 0 },
288 { AFMOVD, C_FREG, C_NONE, C_XPRE, 23, 4, 0 },
291 { AMOV, C_SPR, C_NONE, C_REG, 35, 4, 0 },
292 { AMRS, C_SPR, C_NONE, C_REG, 35, 4, 0 },
294 { AMOV, C_REG, C_NONE, C_SPR, 36, 4, 0 },
295 { AMSR, C_REG, C_NONE, C_SPR, 36, 4, 0 },
297 { AMOV, C_LCON, C_NONE, C_SPR, 37, 4, 0 },
298 { AMSR, C_LCON, C_NONE, C_SPR, 37, 4, 0 },
300 { AERET, C_NONE, C_NONE, C_NONE, 41, 4, 0 },
302 { AFMOVS, C_FREG, C_NONE, C_SEXT4, 20, 4, REGSB },
303 { AFMOVS, C_FREG, C_NONE, C_UAUTO16K, 20, 4, REGSP },
304 { AFMOVS, C_FREG, C_NONE, C_NSAUTO, 20, 4, REGSP },
305 { AFMOVS, C_FREG, C_NONE, C_ZOREG, 20, 4, 0 },
306 { AFMOVS, C_FREG, C_NONE, C_UOREG16K, 20, 4, 0 },
307 { AFMOVS, C_FREG, C_NONE, C_NSOREG, 20, 4, 0 },
309 { AFMOVD, C_FREG, C_NONE, C_SEXT8, 20, 4, REGSB },
310 { AFMOVD, C_FREG, C_NONE, C_UAUTO32K, 20, 4, REGSP },
311 { AFMOVD, C_FREG, C_NONE, C_NSAUTO, 20, 4, REGSP },
312 { AFMOVD, C_FREG, C_NONE, C_ZOREG, 20, 4, 0 },
313 { AFMOVD, C_FREG, C_NONE, C_UOREG32K, 20, 4, 0 },
314 { AFMOVD, C_FREG, C_NONE, C_NSOREG, 20, 4, 0 },
316 { AFMOVS, C_SEXT4, C_NONE, C_FREG, 21, 4, REGSB },
317 { AFMOVS, C_UAUTO16K,C_NONE, C_FREG, 21, 4, REGSP },
318 { AFMOVS, C_NSAUTO,C_NONE, C_FREG, 21, 4, REGSP },
319 { AFMOVS, C_ZOREG,C_NONE, C_FREG, 21, 4, 0 },
320 { AFMOVS, C_UOREG16K,C_NONE, C_FREG, 21, 4, 0 },
321 { AFMOVS, C_NSOREG,C_NONE, C_FREG, 21, 4, 0 },
323 { AFMOVD, C_SEXT8, C_NONE, C_FREG, 21, 4, REGSB },
324 { AFMOVD, C_UAUTO32K,C_NONE, C_FREG, 21, 4, REGSP },
325 { AFMOVD, C_NSAUTO,C_NONE, C_FREG, 21, 4, REGSP },
326 { AFMOVD, C_ZOREG,C_NONE, C_FREG, 21, 4, 0 },
327 { AFMOVD, C_UOREG32K,C_NONE, C_FREG, 21, 4, 0 },
328 { AFMOVD, C_NSOREG,C_NONE, C_FREG, 21, 4, 0 },
330 { AFMOVS, C_FREG, C_NONE, C_LEXT, 30, 8, REGSB, LTO },
331 { AFMOVS, C_FREG, C_NONE, C_LAUTO, 30, 8, REGSP, LTO },
332 { AFMOVS, C_FREG, C_NONE, C_LOREG, 30, 8, 0, LTO },
334 { AFMOVS, C_LEXT, C_NONE, C_FREG, 31, 8, REGSB, LFROM },
335 { AFMOVS, C_LAUTO,C_NONE, C_FREG, 31, 8, REGSP, LFROM },
336 { AFMOVS, C_LOREG,C_NONE, C_FREG, 31, 8, 0, LFROM },
338 { AFMOVS, C_FREG, C_NONE, C_ADDR, 64, 8, 0, LTO },
339 { AFMOVS, C_ADDR, C_NONE, C_FREG, 65, 8, 0, LFROM },
341 { AFADDS, C_FREG, C_NONE, C_FREG, 54, 4, 0 },
342 { AFADDS, C_FREG, C_REG, C_FREG, 54, 4, 0 },
343 { AFADDS, C_FCON, C_NONE, C_FREG, 54, 4, 0 },
344 { AFADDS, C_FCON, C_REG, C_FREG, 54, 4, 0 },
346 { AFMOVS, C_FCON, C_NONE, C_FREG, 54, 4, 0 },
347 { AFMOVS, C_FREG, C_NONE, C_FREG, 54, 4, 0 },
348 { AFMOVD, C_FCON, C_NONE, C_FREG, 54, 4, 0 },
349 { AFMOVD, C_FREG, C_NONE, C_FREG, 54, 4, 0 },
351 { AFCVTZSD, C_FREG, C_NONE, C_REG, 29, 4, 0 },
352 { ASCVTFD, C_REG, C_NONE, C_FREG, 29, 4, 0 },
354 { AFCMPS, C_FREG, C_REG, C_NONE, 56, 4, 0 },
355 { AFCMPS, C_FCON, C_REG, C_NONE, 56, 4, 0 },
357 { AFCCMPS, C_COND, C_REG, C_LCON, 57, 4, 0 },
359 { AFCSELD, C_COND, C_REG, C_FREG, 18, 4, 0 },
361 { AFCVTSD, C_FREG, C_NONE, C_FREG, 29, 4, 0 },
363 { ACASE, C_REG, C_NONE, C_REG, 62, 4*4, 0 },
364 { ABCASE, C_NONE, C_NONE, C_SBRA, 63, 4, 0 },
366 { ACLREX, C_NONE, C_NONE, C_LCON, 38, 4, 0 },
367 { ACLREX, C_NONE, C_NONE, C_NONE, 38, 4, 0 },
369 { ACBZ, C_REG, C_NONE, C_SBRA, 39, 4, 0 },
370 { ATBZ, C_LCON, C_REG, C_SBRA, 40, 4, 0 },
372 { ASYS, C_LCON, C_NONE, C_NONE, 50, 4, 0 },
373 { ASYS, C_LCON, C_REG, C_NONE, 50, 4, 0 },
374 { ASYSL, C_LCON, C_NONE, C_REG, 50, 4, 0 },
376 { ADMB, C_LCON, C_NONE, C_NONE, 51, 4, 0 },
377 { AHINT, C_LCON, C_NONE, C_NONE, 52, 4, 0 },
379 { ALDXR, C_ZOREG, C_NONE, C_REG, 58, 4, 0 },
380 { ALDXP, C_ZOREG, C_REG, C_REG, 58, 4, 0 },
381 { ASTXR, C_REG, C_REG, C_ZOREG, 59, 4, 0 },
382 { ASTXP, C_REG, C_REG, C_ZOREG, 59, 4, 0 },
384 { AAESD, C_VREG, C_NONE, C_VREG, 29, 4, 0 },
385 { ASHA1C, C_VREG, C_REG, C_VREG, 1, 4, 0 },
387 { AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0 },