14 /* R1 to R7 are potential parameter/return registers */
15 #define REGIRL 8 /* indirect result location (TO DO) */
16 /* compiler allocates R9 up as temps */
17 /* compiler allocates register variables R10 up */
23 /* compiler allocates external registers R27 down */
36 /* compiler allocates register variables F0 up */
37 /* compiler allocates external registers F15 down */
296 * Do not reorder or fragment the conditional branch
297 * opcodes, or the predication code will break
432 /* form offset parameter to SYS; special register number */
433 #define SYSARG5(op0,op1,Cn,Cm,op2) ((op0)<<19|(op1)<<16|(Cn)<<12|(Cm)<<8|(op2)<<5)
434 #define SYSARG4(op1,Cn,Cm,op2) SYSARG5(0,op1,Cn,Cm,op2)
450 D_OREG, /* offset(reg) */
451 D_XPRE, /* offset(reg)! - pre-indexed */
452 D_XPOST, /* (reg)offset! - post-indexed */
453 D_CONST, /* 32-bit constant */
454 D_DCONST, /* 64-bit constant */
455 D_FCONST, /* floating-point constant */
456 D_SCONST, /* short string constant */
457 D_REG, /* Rn = Wn or Xn depending on op */
458 D_SP, /* distinguish REGSP from REGZERO */
459 D_FREG, /* Fn = Sn or Dn depending on op */
460 D_VREG, /* Vn = SIMD register */
461 D_SPR, /* special processor register */
463 D_OCONST, /* absolute address constant (unused) */
466 D_SHIFT, /* Rm{, ashift #imm} */
467 D_PAIR, /* pair of gprs */
468 D_ADDR, /* address constant (dynamic loading) */
469 D_ADRP, /* pc-relative addressing, page */
470 D_ADRLO, /* low-order 12 bits of external reference */
471 D_EXTREG, /* Rm{, ext #imm} */
472 D_ROFF, /* register offset Rn+ext(Rm)<<s */
473 D_COND, /* condition EQ, NE, etc */
474 D_VLANE, /* Vn lane */
475 D_VSET, /* set of Vn */
477 /* offset iff type is D_SPR */
478 D_DAIF = SYSARG5(3,3,4,2,1),
479 D_NZCV = SYSARG5(3,3,4,2,0),
480 D_FPSR = SYSARG5(3,3,4,4,1),
481 D_FPCR = SYSARG5(3,3,4,4,0),
482 D_SPSR_EL1 = SYSARG5(3,0,4,0,0),
483 D_ELR_EL1 = SYSARG5(3,0,4,0,1),
484 D_SPSR_EL2 = SYSARG5(3,4,4,0,0),
485 D_ELR_EL2 = SYSARG5(3,4,4,0,1),
486 // D_SPSR_EL3 = SYSARG5(3,x,4,x,x),
487 // D_ELR_EL3 = SYSARG5(3,x,4,x,x),
488 // D_LR_EL0 = SYSARG5(3,x,4,x,x),
489 D_CurrentEL = SYSARG5(3,0,4,2,2),
490 D_SP_EL0 = SYSARG5(3,0,4,1,0),
491 // D_SP_EL1 = SYSARG5(3,x,4,x,x),
492 // D_SP_EL2 = SYSARG5(3,x,4,x,x),
493 D_SPSel = SYSARG5(3,0,4,2,0),
494 // D_SPSR_abt = SYSARG5(3,x,4,x,x),
495 // D_SPSR_fiq = SYSARG5(3,x,4,x,x),
496 // D_SPSR_ieq = SYSARG5(3,x,4,x,x),
497 // D_SPSR_und = SYSARG5(3,x,4,x,x),
498 D_DAIFSet = (1<<30)|0,
499 D_DAIFClr = (1<<30)|1
503 * this is the ranlib header
505 #define SYMDEF "__.SYMDEF"
508 * this is the simulated IEEE floating point
510 typedef struct Ieee Ieee;
513 long l; /* contains ls-man 0xffffffff */
514 long h; /* contains sign 0x80000000