4 #define SET(R, V) MOVW $(V), R0 ; MOVW R0, (R)(Rb)
5 #define RMW(r, m, v) MOVW (r)(Rb), R0; BIC $(m), R0; ORR $(v), R0; MOVW R0, (r)(Rb)
18 MOVW $(1<<7|1<<6|0x13), R0
22 MCR CpMMU, 0, R0, C(12), C(0)
24 SET(SLCR_UNLOCK, UNLOCK_KEY)
26 MCR 15, 0, R0, C(8), C(7), 0
27 MCR 15, 0, R0, C(7), C(5), 0
28 MCR 15, 0, R0, C(7), C(5), 6
30 MCR 15, 0, R1, C(1), C(0), 0
57 SET(SLCR_LOCK, LOCK_KEY)
66 SET(ARM_PLL_CFG, ARM_PLL_CFG_VAL)
67 SET(DDR_PLL_CFG, DDR_PLL_CFG_VAL)
68 SET(IO_PLL_CFG, IO_PLL_CFG_VAL)
70 MOVW $(ARM_FDIV | PLL_BYPASS_FORCE), R0
71 MOVW R0, ARM_PLL_CTRL(Rb)
73 MOVW R4, ARM_PLL_CTRL(Rb)
74 MOVW R0, ARM_PLL_CTRL(Rb)
76 MOVW $(DDR_FDIV | PLL_BYPASS_FORCE), R0
77 MOVW R0, DDR_PLL_CTRL(Rb)
79 MOVW R4, DDR_PLL_CTRL(Rb)
80 MOVW R0, DDR_PLL_CTRL(Rb)
82 MOVW $(IO_FDIV | PLL_BYPASS_FORCE), R0
83 MOVW R0, IO_PLL_CTRL(Rb)
85 MOVW R4, IO_PLL_CTRL(Rb)
86 MOVW R0, IO_PLL_CTRL(Rb)
89 MOVW PLL_STATUS(Rb), R0
94 SET(ARM_PLL_CTRL, ARM_FDIV)
95 SET(DDR_PLL_CTRL, DDR_FDIV)
96 SET(IO_PLL_CTRL, IO_FDIV)
98 SET(ARM_CLK_CTRL, 0x1f << 24 | CPU_DIV << 8)
99 SET(UART_CLK_CTRL, UART_DIV << 8 | 3)
100 SET(DDR_CLK_CTRL, DDR_DIV3 << 20 | DDR_DIV2 << 26 | 3)
101 SET(DCI_CLK_CTRL, DCI_DIV0 << 8 | DCI_DIV1 << 20 | 1)
102 SET(GEM0_RCLK_CTRL, 1)
103 SET(GEM1_RCLK_CTRL, 0)
104 SET(GEM0_CLK_CTRL, ETH_DIV0 << 8 | ETH_DIV1 << 20 | 1)
105 SET(GEM1_CLK_CTRL, 0)
106 SET(GPIOB_CTRL, VREF_SW_EN)
107 SET(APER_CLK_CTRL, LQSPI_CLK_EN | GPIO_CLK_EN | UART0_CLK_EN | UART1_CLK_EN | I2C0_CLK_EN | SDIO1_CLK_EN | GEM0_CLK_EN | USB0_CLK_EN | USB1_CLK_EN | DMA_CLK_EN)
108 SET(SMC_CLK_CTRL, 0x3C20)
109 SET(LQSPI_CLK_CTRL, QSPI_DIV << 8 | 1)
110 SET(SDIO_CLK_CTRL, SDIO_DIV << 8 | 2)
111 SET(SPI_CLK_CTRL, 0x3F00)
112 SET(CAN_CLK_CTRL, 0x501900)
113 SET(PCAP_CLK_CTRL, PCAP_DIV << 8 | 1)
116 TEXT miosetup(SB), $0
118 SET(UART_RST_CTRL, 0xf)
119 SET(UART_RST_CTRL, 0)
121 MOVW $miodata(SB), R1
122 ADD $MIO_PIN_0, Rb, R2
127 MOVW R0, MIO_MST_TRI0(Rb)
128 MOVW R0, MIO_MST_TRI1(Rb)
139 TEXT ddrsetup(SB), $0
141 RMW(DDRIOB_DCI_CTRL, DCI_RESET, DCI_RESET)
142 RMW(DDRIOB_DCI_CTRL, DCI_RESET, 0)
143 RMW(DDRIOB_DCI_CTRL, DDRIOB_DCI_CTRL_MASK, DCI_NREF | DCI_ENABLE | DCI_RESET)
146 ADD $DDRIOB_ADDR0, Rb, R2
150 MOVW $ddrdata(SB), R1
164 MOVW DDRIOB_DCI_STATUS(Rb), R0
168 RMW(DDRC_CTRL, 0x1ffff, 0x81)
170 MOVW DDR_MODE_STS(Rb), R0
180 ADD $(1024 * 1024 * 10), R0, R1
202 TEXT uartsetup(SB), $0
219 MOVW UART_STAT(Rb), R1
223 MOVW R0, UART_DATA(Rb)
237 #define LVCMOS18 (1<<9)
238 #define LVCMOS25 (2<<9)
239 #define LVCMOS33 (3<<9)
241 #define PULLUP (1<<12)
242 #define NORECV (1<<13)
244 #define MUX(a, b, c, d) ((a)<<1 | (b)<<2 | (c)<<3 | (d)<<5)
246 #define NO (TRI | LVCMOS33)
247 #define SPI (MUX(1, 0, 0, 0) | LVCMOS33)
248 #define UART (MUX(0, 0, 0, 7) | LVCMOS33)
249 #define SD (MUX(0, 0, 0, 4) | LVCMOS33)
250 #define ETX (MUX(1, 0, 0, 0) | HSTL | NORECV | PULLUP)
251 #define ERX (MUX(1, 0, 0, 0) | HSTL | TRI | PULLUP)
252 #define USB (MUX(0, 1, 0, 0) | LVCMOS18)
253 #define MDCLK (MUX(0, 0, 0, 4) | HSTL)
254 #define MDDATA (MUX(0, 0, 0, 4) | HSTL)
256 TEXT miodata(SB), $-4
266 WORD $(UART|TRI) // 9