4 * initialise bridge mappings if the PCI BIOS didn't.
14 enum { /* configuration mechanism #1 */
15 PciADDR = 0xCF8, /* CONFIG_ADDRESS */
16 PciDATA = 0xCFC, /* CONFIG_DATA */
18 /* configuration mechanism #2 */
19 PciCSE = 0xCF8, /* configuration space enable */
20 PciFORWARD = 0xCFA, /* which bus */
27 { /* command register */
36 static Lock pcicfglock;
37 static Lock pcicfginitlock;
38 static int pcicfgmode = -1;
39 static int pcimaxbno = 7;
41 static Pcidev* pciroot;
42 static Pcidev* pcilist;
43 static Pcidev* pcitail;
45 static int pcicfgrw32(int, int, int, int);
46 static int pcicfgrw8(int, int, int, int);
49 pcibarsize(Pcidev *p, int rno)
53 v = pcicfgrw32(p->tbdf, rno, 0, 1);
54 pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
55 size = pcicfgrw32(p->tbdf, rno, 0, 1);
58 pcicfgrw32(p->tbdf, rno, v, 0);
60 return -(size & ~0x0F);
63 /* side effect: if a video controller is seen, set vga non-zero */
65 pciscan(int bno, Pcidev** list)
67 Pcidev *p, *head, *tail;
68 int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
73 for(dno = 0; dno <= pcimaxdno; dno++){
75 for(fno = 0; fno <= maxfno; fno++){
77 * For this possible device, form the
78 * bus+device+function triplet needed to address it
79 * and try to read the vendor and device ID.
80 * If successful, allocate a device struct and
81 * start to fill it in with some useful information
82 * from the device's configuration space.
84 tbdf = MKBUS(BusPCI, bno, dno, fno);
85 l = pcicfgrw32(tbdf, PciVID, 0, 1);
86 if(l == 0xFFFFFFFF || l == 0)
88 p = malloc(sizeof(*p));
99 p->rid = pcicfgr8(p, PciRID);
100 p->ccrp = pcicfgr8(p, PciCCRp);
101 p->ccru = pcicfgr8(p, PciCCRu);
102 p->ccrb = pcicfgr8(p, PciCCRb);
103 p->pcr = pcicfgr32(p, PciPCR);
105 p->intl = pcicfgr8(p, PciINTL);
108 * If the device is a multi-function device adjust the
109 * loop count so all possible functions are checked.
111 hdt = pcicfgr8(p, PciHDT);
116 * If appropriate, read the base address registers
117 * and work out the sizes.
121 case 0x03: /* display controller */
124 case 0x01: /* mass storage controller */
125 case 0x02: /* network controller */
126 case 0x04: /* multimedia device */
127 case 0x07: /* simple comm. controllers */
128 case 0x08: /* base system peripherals */
129 case 0x09: /* input devices */
130 case 0x0A: /* docking stations */
131 case 0x0B: /* processors */
132 case 0x0C: /* serial bus controllers */
133 if((hdt & 0x7F) != 0)
136 for(i = 0; i < nelem(p->mem); i++){
138 p->mem[i].bar = pcicfgr32(p, rno);
139 p->mem[i].size = pcibarsize(p, rno);
144 case 0x05: /* memory controller */
145 case 0x06: /* bridge device */
159 for(p = head; p != nil; p = p->link){
161 * Find PCI-PCI and PCI-Cardbus bridges
162 * and recursively descend the tree.
164 if(p->ccrb != 0x06 || p->ccru != 0x04)
168 * If the secondary or subordinate bus number is not
169 * initialised try to do what the PCI BIOS should have
170 * done and fill in the numbers as the tree is descended.
171 * On the way down the subordinate bus number is set to
172 * the maximum as it's not known how many buses are behind
173 * this one; the final value is set on the way back up.
175 ubn = pcicfgr8(p, PciUBN);
176 sbn = pcicfgr8(p, PciSBN);
178 if(sbn == 0 || ubn == 0){
181 * Make sure memory, I/O and master enables are
182 * off, set the primary, secondary and subordinate
183 * bus numbers and clear the secondary status before
184 * attempting to scan the secondary bus.
186 * Initialisation of the bridge should be done here.
188 pcicfgw32(p, PciPCR, 0xFFFF0000);
189 l = (MaxUBN<<16)|(sbn<<8)|bno;
190 pcicfgw32(p, PciPBN, l);
191 pcicfgw16(p, PciSPSR, 0xFFFF);
192 maxubn = pciscan(sbn, &p->bridge);
193 l = (maxubn<<16)|(sbn<<8)|bno;
195 pcicfgw32(p, PciPBN, l);
200 * This shouldn't be possible, but the
201 * Iwill DK8-HTX seems to have subordinate
202 * bus numbers which get smaller on the
203 * way down. Need to look more closely at
208 pciscan(sbn, &p->bridge);
216 null_link(Pcidev *, uchar )
222 null_init(Pcidev *, uchar , uchar )
227 pIIx_link(Pcidev *router, uchar link)
231 /* link should be 0x60, 0x61, 0x62, 0x63 */
232 pirq = pcicfgr8(router, link);
233 return (pirq < 16)? pirq: 0;
237 pIIx_init(Pcidev *router, uchar link, uchar irq)
239 pcicfgw8(router, link, irq);
243 via_link(Pcidev *router, uchar link)
247 /* link should be 1, 2, 3, 5 */
248 pirq = (link < 6)? pcicfgr8(router, 0x55 + (link>>1)): 0;
250 return (link & 1)? (pirq >> 4): (pirq & 15);
254 via_init(Pcidev *router, uchar link, uchar irq)
258 pirq = pcicfgr8(router, 0x55 + (link >> 1));
259 pirq &= (link & 1)? 0x0f: 0xf0;
260 pirq |= (link & 1)? (irq << 4): (irq & 15);
261 pcicfgw8(router, 0x55 + (link>>1), pirq);
265 opti_link(Pcidev *router, uchar link)
269 /* link should be 0x02, 0x12, 0x22, 0x32 */
270 if ((link & 0xcf) == 0x02)
271 pirq = pcicfgr8(router, 0xb8 + (link >> 5));
272 return (link & 0x10)? (pirq >> 4): (pirq & 15);
276 opti_init(Pcidev *router, uchar link, uchar irq)
280 pirq = pcicfgr8(router, 0xb8 + (link >> 5));
281 pirq &= (link & 0x10)? 0x0f : 0xf0;
282 pirq |= (link & 0x10)? (irq << 4): (irq & 15);
283 pcicfgw8(router, 0xb8 + (link >> 5), pirq);
287 ali_link(Pcidev *router, uchar link)
289 /* No, you're not dreaming */
290 static const uchar map[] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
293 /* link should be 0x01..0x08 */
294 pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
295 return (link & 1)? map[pirq&15]: map[pirq>>4];
299 ali_init(Pcidev *router, uchar link, uchar irq)
301 /* Inverse of map in ali_link */
302 static const uchar map[] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
305 pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
306 pirq &= (link & 1)? 0x0f: 0xf0;
307 pirq |= (link & 1)? (map[irq] << 4): (map[irq] & 15);
308 pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
312 cyrix_link(Pcidev *router, uchar link)
316 /* link should be 1, 2, 3, 4 */
317 pirq = pcicfgr8(router, 0x5c + ((link-1)>>1));
318 return ((link & 1)? pirq >> 4: pirq & 15);
322 cyrix_init(Pcidev *router, uchar link, uchar irq)
326 pirq = pcicfgr8(router, 0x5c + (link>>1));
327 pirq &= (link & 1)? 0x0f: 0xf0;
328 pirq |= (link & 1)? (irq << 4): (irq & 15);
329 pcicfgw8(router, 0x5c + (link>>1), pirq);
333 ushort sb_vid, sb_did;
334 uchar (*sb_translate)(Pcidev *, uchar);
335 void (*sb_initialize)(Pcidev *, uchar, uchar);
338 static bridge_t southbridges[] = {
339 { 0x8086, 0x122e, pIIx_link, pIIx_init }, // Intel 82371FB
340 { 0x8086, 0x1234, pIIx_link, pIIx_init }, // Intel 82371MX
341 { 0x8086, 0x7000, pIIx_link, pIIx_init }, // Intel 82371SB
342 { 0x8086, 0x7110, pIIx_link, pIIx_init }, // Intel 82371AB
343 { 0x8086, 0x7198, pIIx_link, pIIx_init }, // Intel 82443MX (fn 1)
344 { 0x8086, 0x2410, pIIx_link, pIIx_init }, // Intel 82801AA
345 { 0x8086, 0x2420, pIIx_link, pIIx_init }, // Intel 82801AB
346 { 0x8086, 0x2440, pIIx_link, pIIx_init }, // Intel 82801BA
347 { 0x8086, 0x244c, pIIx_link, pIIx_init }, // Intel 82801BAM
348 { 0x8086, 0x2480, pIIx_link, pIIx_init }, // Intel 82801CA
349 { 0x8086, 0x248c, pIIx_link, pIIx_init }, // Intel 82801CAM
350 { 0x8086, 0x24c0, pIIx_link, pIIx_init }, // Intel 82801DBL
351 { 0x8086, 0x24cc, pIIx_link, pIIx_init }, // Intel 82801DBM
352 { 0x8086, 0x24d0, pIIx_link, pIIx_init }, // Intel 82801EB
353 { 0x8086, 0x25a1, pIIx_link, pIIx_init }, // Intel 6300ESB
354 { 0x8086, 0x2640, pIIx_link, pIIx_init }, // Intel 82801FB
355 { 0x8086, 0x2641, pIIx_link, pIIx_init }, // Intel 82801FBM
356 { 0x8086, 0x27b8, pIIx_link, pIIx_init }, // Intel 82801GB
357 { 0x8086, 0x27b9, pIIx_link, pIIx_init }, // Intel 82801GBM
358 { 0x1106, 0x0586, via_link, via_init }, // Viatech 82C586
359 { 0x1106, 0x0596, via_link, via_init }, // Viatech 82C596
360 { 0x1106, 0x0686, via_link, via_init }, // Viatech 82C686
361 { 0x1106, 0x3227, via_link, via_init }, // Viatech VT8237
362 { 0x1045, 0xc700, opti_link, opti_init }, // Opti 82C700
363 { 0x10b9, 0x1533, ali_link, ali_init }, // Al M1533
364 { 0x1039, 0x0008, pIIx_link, pIIx_init }, // SI 503
365 { 0x1039, 0x0496, pIIx_link, pIIx_init }, // SI 496
366 { 0x1078, 0x0100, cyrix_link, cyrix_init }, // Cyrix 5530 Legacy
368 { 0x1002, 0x4377, nil, nil }, // ATI Radeon Xpress 200M
369 { 0x1002, 0x4372, nil, nil }, // ATI SB400
370 { 0x1022, 0x746B, nil, nil }, // AMD 8111
371 { 0x10DE, 0x00D1, nil, nil }, // NVIDIA nForce 3
372 { 0x10DE, 0x00E0, nil, nil }, // NVIDIA nForce 3 250 Series
373 { 0x10DE, 0x00E1, nil, nil }, // NVIDIA nForce 3 250 Series
374 { 0x1166, 0x0200, nil, nil }, // ServerWorks ServerSet III LE
378 uchar e_bus; // Pci bus number
379 uchar e_dev; // Pci device number
380 uchar e_maps[12]; // Avoid structs! Link and mask.
381 uchar e_slot; // Add-in/built-in slot
386 uchar rt_signature[4]; // Routing table signature
387 uchar rt_version[2]; // Version number
388 uchar rt_size[2]; // Total table size
389 uchar rt_bus; // Interrupt router bus number
390 uchar rt_devfn; // Router's devfunc
391 uchar rt_pciirqs[2]; // Exclusive PCI irqs
392 uchar rt_compat[4]; // Compatible PCI interrupt router
393 uchar rt_miniport[4]; // Miniport data
394 uchar rt_reserved[11];
398 static ushort pciirqs; // Exclusive PCI irqs
399 static bridge_t *southbridge; // Which southbridge to use.
413 for (p = (uchar *)KADDR(0xf0000); p < (uchar *)KADDR(0xfffff); p += 16)
414 if (p[0] == '$' && p[1] == 'P' && p[2] == 'I' && p[3] == 'R')
417 if (p >= (uchar *)KADDR(0xfffff))
422 // print("PCI interrupt routing table version %d.%d at %.6uX\n",
423 // r->rt_version[0], r->rt_version[1], (ulong)r & 0xfffff);
425 tbdf = (BusPCI << 24)|(r->rt_bus << 16)|(r->rt_devfn << 8);
426 vdid = pcicfgrw32(tbdf, PciVID, 0, 1);
430 for (i = 0; i != nelem(southbridges); i++)
431 if (vid == southbridges[i].sb_vid && did == southbridges[i].sb_did)
434 if (i == nelem(southbridges)) {
435 print("pcirouting: South bridge %.4uX, %.4uX not found\n", vid, did);
438 southbridge = &southbridges[i];
440 if ((sbpci = pcimatch(nil, vid, did)) == nil) {
441 print("pcirouting: Cannot match south bridge %.4uX, %.4uX\n",
446 pciirqs = (r->rt_pciirqs[1] << 8)|r->rt_pciirqs[0];
448 size = (r->rt_size[1] << 8)|r->rt_size[0];
449 for (e = (slot_t *)&r[1]; (uchar *)e < p + size; e++) {
450 // print("%.2uX/%.2uX %.2uX: ", e->e_bus, e->e_dev, e->e_slot);
451 // for (i = 0; i != 4; i++) {
452 // uchar *m = &e->e_maps[i * 3];
453 // print("[%d] %.2uX %.4uX ",
454 // i, m[0], (m[2] << 8)|m[1]);
458 for (fn = 0; fn != 8; fn++) {
461 // Retrieve the did and vid through the devfn before
462 // obtaining the Pcidev structure.
463 tbdf = (BusPCI << 24)|(e->e_bus << 16)|((e->e_dev | fn) << 8);
464 vdid = pcicfgrw32(tbdf, PciVID, 0, 1);
465 if (vdid == 0xFFFFFFFF || vdid == 0)
472 while ((pci = pcimatch(pci, vid, did)) != nil) {
473 if (pci->intl != 0 && pci->intl != 0xFF)
476 pin = pcicfgr8(pci, PciINTP);
477 if (pin == 0 || pin == 0xff)
480 m = &e->e_maps[(pin - 1) * 3];
481 irq = southbridge->sb_translate(sbpci, m[0]);
483 print("pcirouting: %.4uX/%.4uX at pin %d irq %d\n",
485 pcicfgw8(pci, PciINTL, irq);
500 lock(&pcicfginitlock);
505 * Try to determine which PCI configuration mode is implemented.
506 * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
507 * a DWORD at 0xCF8 and another at 0xCFC and will pass through
508 * any non-DWORD accesses as normal I/O cycles. There shouldn't be
509 * a device behind these addresses so if Mode1 accesses fail try
510 * for Mode2 (Mode2 is deprecated).
514 * Bits [30:24] of PciADDR must be 0,
515 * according to the spec.
518 if(!(n & 0x7FF00000)){
519 outl(PciADDR, 0x80000000);
521 if(inl(PciADDR) & 0x80000000){
530 * The 'key' part of PciCSE should be 0.
535 if(inb(PciCSE) == 0x0E){
547 if(p = getconf("*pcimaxbno"))
548 pcimaxbno = strtoul(p, 0, 0);
549 if(p = getconf("*pcimaxdno"))
550 pcimaxdno = strtoul(p, 0, 0);
553 for(bno = 0; bno <= pcimaxbno; bno++) {
554 bno = pciscan(bno, list);
556 list = &(*list)->link;
562 unlock(&pcicfginitlock);
564 if(getconf("*pcihinv"))
570 pcicfgrw8(int tbdf, int rno, int data, int read)
582 if(BUSDNO(tbdf) > pcimaxdno)
591 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
595 outb(PciDATA+o, data);
600 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
601 outb(PciFORWARD, BUSBNO(tbdf));
603 x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
605 outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
615 pcicfgr8(Pcidev* pcidev, int rno)
617 return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
621 pcicfgw8(Pcidev* pcidev, int rno, int data)
623 pcicfgrw8(pcidev->tbdf, rno, data, 0);
627 pcicfgrw16(int tbdf, int rno, int data, int read)
639 if(BUSDNO(tbdf) > pcimaxdno)
648 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
652 outs(PciDATA+o, data);
657 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
658 outb(PciFORWARD, BUSBNO(tbdf));
660 x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
662 outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
672 pcicfgr16(Pcidev* pcidev, int rno)
674 return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
678 pcicfgw16(Pcidev* pcidev, int rno, int data)
680 pcicfgrw16(pcidev->tbdf, rno, data, 0);
684 pcicfgrw32(int tbdf, int rno, int data, int read)
696 if(BUSDNO(tbdf) > pcimaxdno)
704 outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
713 outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
714 outb(PciFORWARD, BUSBNO(tbdf));
716 x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
718 outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
728 pcicfgr32(Pcidev* pcidev, int rno)
730 return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
734 pcicfgw32(Pcidev* pcidev, int rno, int data)
736 pcicfgrw32(pcidev->tbdf, rno, data, 0);
740 pcimatch(Pcidev* prev, int vid, int did)
751 if((vid == 0 || prev->vid == vid)
752 && (did == 0 || prev->did == did))
760 pciipin(Pcidev *pci, uchar pin)
768 if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
771 if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
780 pciimask(Pcidev *pci)
786 if (pcicfgr8(pci, PciINTP) && pci->intl < 16)
787 imask |= 1 << pci->intl;
790 imask |= pciimask(pci->bridge);
806 imask = pciimask(pci) | 1;
807 for (i = 0; i != 16; i++)
808 if ((imask & (1 << i)) == 0)
814 pcihinv(Pcidev* p, int base)
824 print("bus dev type vid did intl memory\n");
826 for(t = p; t != nil; t = t->link) {
827 if (base >= 0 && base != t->ccrb)
829 print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
830 BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
831 t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
833 for(i = 0; i < nelem(p->mem); i++) {
834 if(t->mem[i].size == 0)
836 print("%d:%.8lux %d ", i,
837 t->mem[i].bar, t->mem[i].size);
843 pcihinv(p->bridge, base);
857 for(p = pcilist; p != nil; p = p->list){
858 pcr = pcicfgr16(p, PciPSR);
859 pcicfgw16(p, PciPSR, pcr & ~0x04);
867 pcicfgw16(p, PciPCR, p->pcr);
874 pcicfgw16(p, PciPCR, p->pcr);
881 pcicfgw16(p, PciPCR, p->pcr);
888 pcicfgw16(p, PciPCR, p->pcr);
895 pcicfgw16(p, PciPCR, p->pcr);
902 pcicfgw16(p, PciPCR, p->pcr);
906 pcigetpmrb(Pcidev* p)
915 * If there are no extended capabilities implemented,
916 * (bit 4 in the status register) assume there's no standard
917 * power management method.
918 * Find the capabilities pointer based on PCI header type.
920 if(!(pcicfgr16(p, PciPSR) & 0x0010))
922 switch(pcicfgr8(p, PciHDT)){
925 case 0: /* all other */
926 case 1: /* PCI to PCI bridge */
929 case 2: /* CardBus bridge */
933 ptr = pcicfgr32(p, ptr);
937 * Check for validity.
938 * Can't be in standard header and must be double
941 if(ptr < 0x40 || (ptr & ~0xFC))
943 if(pcicfgr8(p, ptr) == 0x01){
948 ptr = pcicfgr8(p, ptr+1);
959 if((ptr = pcigetpmrb(p)) == -1)
963 * Power Management Register Block:
964 * offset 0: Capability ID
965 * 1: next item pointer
968 * 6: bridge support extensions
971 pmcsr = pcicfgr16(p, ptr+4);
973 return pmcsr & 0x0003;
977 pcisetpms(Pcidev* p, int state)
979 int ostate, pmc, pmcsr, ptr;
981 if((ptr = pcigetpmrb(p)) == -1)
984 pmc = pcicfgr16(p, ptr+2);
985 pmcsr = pcicfgr16(p, ptr+4);
986 ostate = pmcsr & 0x0003;
1006 pcicfgw16(p, ptr+4, pmcsr);