sys/src/boot/pc/etherigbe.c

   1 /*
   2  * bootstrap driver for
   3  * Intel RS-82543GC Gigabit Ethernet PCI Controllers
   4  * as found on the Intel PRO/1000[FT] Server Adapter.
   5  * The older non-[FT] cards use the 82542 (LSI L2A1157) chip; no attempt
   6  * is made to handle the older chip although it should be possible.
   7  *
   8  * updated just enough to cope with the
   9  * Intel 8254[0347]NN Gigabit Ethernet Controller
  10  * as found on the Intel PRO/1000 series of adapters:
  11  *      82540EM Intel PRO/1000 MT
  12  *      82543GC Intel PRO/1000 T
  13  *      82544EI Intel PRO/1000 XT
  14  *      82547EI built-in
  15  *
  16  * The datasheet is not very clear about running on a big-endian system
  17  * and this driver assumes little-endian throughout.
  18  * To do:
  19  *      GMII/MII
  20  *      check recovery from receive no buffers condition
  21  *      automatic ett adjustment
  22  */
  23 #include "u.h"
  24 #include "lib.h"
  25 #include "mem.h"
  26 #include "dat.h"
  27 #include "fns.h"
  28 #include "io.h"
  29
  30 #include "etherif.h"
  31 #include "ethermii.h"
  32
  33 enum {
  34         Debug = 0,              /* mostly for X60 debugging */
  35 };
  36 enum {
  37         i82542          = (0x1000<<16)|0x8086,
  38         i82543gc        = (0x1004<<16)|0x8086,
  39         i82544ei        = (0x1008<<16)|0x8086,
  40         i82544eif       = (0x1009<<16)|0x8086,
  41         i82544gc        = (0x100d<<16)|0x8086,
  42         i82540em        = (0x100E<<16)|0x8086,
  43         i82540eplp      = (0x101E<<16)|0x8086,
  44         i82545em        = (0x100F<<16)|0x8086,
  45         i82545gmc       = (0x1026<<16)|0x8086,
  46         i82547ei        = (0x1019<<16)|0x8086,
  47         i82547gi        = (0x1075<<16)|0x8086,
  48         i82541ei        = (0x1013<<16)|0x8086,
  49         i82541gi        = (0x1076<<16)|0x8086,
  50         i82541gi2       = (0x1077<<16)|0x8086,
  51         i82541pi        = (0x107c<<16)|0x8086,
  52         i82546gb        = (0x1079<<16)|0x8086,
  53         i82546eb        = (0x1010<<16)|0x8086,
  54 };
  55
  56 /* compatibility with cpu kernels */
  57 #define iallocb allocb
  58 #ifndef CACHELINESZ
  59 #define CACHELINESZ     32              /* pentium & later */
  60 #endif
  61
  62 /* from pci.c */
  63 enum
  64 {                                       /* command register (pcidev->pcr) */
  65         IOen            = (1<<0),
  66         MEMen           = (1<<1),
  67         MASen           = (1<<2),
  68         MemWrInv        = (1<<4),
  69         PErrEn          = (1<<6),
  70         SErrEn          = (1<<8),
  71 };
  72 enum {
  73         Ctrl            = 0x00000000,   /* Device Control */
  74         Status          = 0x00000008,   /* Device Status */
  75         Eecd            = 0x00000010,   /* EEPROM/Flash Control/Data */
  76         Ctrlext         = 0x00000018,   /* Extended Device Control */
  77         Mdic            = 0x00000020,   /* MDI Control */
  78         Fcal            = 0x00000028,   /* Flow Control Address Low */
  79         Fcah            = 0x0000002C,   /* Flow Control Address High */
  80         Fct             = 0x00000030,   /* Flow Control Type */
  81         Icr             = 0x000000C0,   /* Interrupt Cause Read */
  82         Ics             = 0x000000C8,   /* Interrupt Cause Set */
  83         Ims             = 0x000000D0,   /* Interrupt Mask Set/Read */
  84         Imc             = 0x000000D8,   /* Interrupt mask Clear */
  85         Rctl            = 0x00000100,   /* Receive Control */
  86         Fcttv           = 0x00000170,   /* Flow Control Transmit Timer Value */
  87         Txcw            = 0x00000178,   /* Transmit Configuration Word */
  88         Tctl            = 0x00000400,   /* Transmit Control */
  89         Tipg            = 0x00000410,   /* Transmit IPG */
  90         Tbt             = 0x00000448,   /* Transmit Burst Timer */
  91         Ait             = 0x00000458,   /* Adaptive IFS Throttle */
  92         Fcrtl           = 0x00002160,   /* Flow Control RX Threshold Low */
  93         Fcrth           = 0x00002168,   /* Flow Control Rx Threshold High */
  94         Rdbal           = 0x00002800,   /* Rdesc Base Address Low */
  95         Rdbah           = 0x00002804,   /* Rdesc Base Address High */
  96         Rdlen           = 0x00002808,   /* Receive Descriptor Length */
  97         Rdh             = 0x00002810,   /* Receive Descriptor Head */
  98         Rdt             = 0x00002818,   /* Receive Descriptor Tail */
  99         Rdtr            = 0x00002820,   /* Receive Descriptor Timer Ring */
 100         Rxdctl          = 0x00002828,   /* Receive Descriptor Control */
 101         Radv            = 0x0000282C,   /* Receive Interrupt Absolute Delay Timer */
 102         Txdmac          = 0x00003000,   /* Transfer DMA Control */
 103         Ett             = 0x00003008,   /* Early Transmit Control */
 104         Tdbal           = 0x00003800,   /* Tdesc Base Address Low */
 105         Tdbah           = 0x00003804,   /* Tdesc Base Address High */
 106         Tdlen           = 0x00003808,   /* Transmit Descriptor Length */
 107         Tdh             = 0x00003810,   /* Transmit Descriptor Head */
 108         Tdt             = 0x00003818,   /* Transmit Descriptor Tail */
 109         Tidv            = 0x00003820,   /* Transmit Interrupt Delay Value */
 110         Txdctl          = 0x00003828,   /* Transmit Descriptor Control */
 111         Tadv            = 0x0000382C,   /* Transmit Interrupt Absolute Delay Timer */
 112
 113         Statistics      = 0x00004000,   /* Start of Statistics Area */
 114         Gorcl           = 0x88/4,       /* Good Octets Received Count */
 115         Gotcl           = 0x90/4,       /* Good Octets Transmitted Count */
 116         Torl            = 0xC0/4,       /* Total Octets Received */
 117         Totl            = 0xC8/4,       /* Total Octets Transmitted */
 118         Nstatistics     = 64,
 119
 120         Rxcsum          = 0x00005000,   /* Receive Checksum Control */
 121         Mta             = 0x00005200,   /* Multicast Table Array */
 122         Ral             = 0x00005400,   /* Receive Address Low */
 123         Rah             = 0x00005404,   /* Receive Address High */
 124         Manc            = 0x00005820,   /* Management Control */
 125 };
 126
 127 enum {                                  /* Ctrl */
 128         Bem             = 0x00000002,   /* Big Endian Mode */
 129         Prior           = 0x00000004,   /* Priority on the PCI bus */
 130         Lrst            = 0x00000008,   /* Link Reset */
 131         Asde            = 0x00000020,   /* Auto-Speed Detection Enable */
 132         Slu             = 0x00000040,   /* Set Link Up */
 133         Ilos            = 0x00000080,   /* Invert Loss of Signal (LOS) */
 134         SspeedMASK      = 0x00000300,   /* Speed Selection */
 135         SspeedSHIFT     = 8,
 136         Sspeed10        = 0x00000000,   /* 10Mb/s */
 137         Sspeed100       = 0x00000100,   /* 100Mb/s */
 138         Sspeed1000      = 0x00000200,   /* 1000Mb/s */
 139         Frcspd          = 0x00000800,   /* Force Speed */
 140         Frcdplx         = 0x00001000,   /* Force Duplex */
 141         SwdpinsloMASK   = 0x003C0000,   /* Software Defined Pins - lo nibble */
 142         SwdpinsloSHIFT  = 18,
 143         SwdpioloMASK    = 0x03C00000,   /* Software Defined Pins - I or O */
 144         SwdpioloSHIFT   = 22,
 145         Devrst          = 0x04000000,   /* Device Reset */
 146         Rfce            = 0x08000000,   /* Receive Flow Control Enable */
 147         Tfce            = 0x10000000,   /* Transmit Flow Control Enable */
 148         Vme             = 0x40000000,   /* VLAN Mode Enable */
 149 };
 150
 151 /*
 152  * can't find Tckok nor Rbcok in any Intel docs,
 153  * but even 82543gc docs define Lanid.
 154  */
 155 enum {                                  /* Status */
 156         Lu              = 0x00000002,   /* Link Up */
 157         Lanid           = 0x0000000C,   /* mask for Lan ID. (function id) */
 158 //      Tckok           = 0x00000004,   /* Transmit clock is running */
 159 //      Rbcok           = 0x00000008,   /* Receive clock is running */
 160         Txoff           = 0x00000010,   /* Transmission Paused */
 161         Tbimode         = 0x00000020,   /* TBI Mode Indication */
 162         SpeedMASK       = 0x000000C0,
 163         Speed10         = 0x00000000,   /* 10Mb/s */
 164         Speed100        = 0x00000040,   /* 100Mb/s */
 165         Speed1000       = 0x00000080,   /* 1000Mb/s */
 166         Mtxckok         = 0x00000400,   /* MTX clock is running */
 167         Pci66           = 0x00000800,   /* PCI Bus speed indication */
 168         Bus64           = 0x00001000,   /* PCI Bus width indication */
 169 };
 170
 171 enum {                                  /* Ctrl and Status */
 172         Fd              = 0x00000001,   /* Full-Duplex */
 173         AsdvMASK        = 0x00000300,
 174         Asdv10          = 0x00000000,   /* 10Mb/s */
 175         Asdv100         = 0x00000100,   /* 100Mb/s */
 176         Asdv1000        = 0x00000200,   /* 1000Mb/s */
 177 };
 178
 179 enum {                                  /* Eecd */
 180         Sk              = 0x00000001,   /* Clock input to the EEPROM */
 181         Cs              = 0x00000002,   /* Chip Select */
 182         Di              = 0x00000004,   /* Data Input to the EEPROM */
 183         Do              = 0x00000008,   /* Data Output from the EEPROM */
 184         Areq            = 0x00000040,   /* EEPROM Access Request */
 185         Agnt            = 0x00000080,   /* EEPROM Access Grant */
 186         Eepresent       = 0x00000100,   /* EEPROM Present */
 187         Eesz256         = 0x00000200,   /* EEPROM is 256 words not 64 */
 188         Eeszaddr        = 0x00000400,   /* EEPROM size for 8254[17] */
 189         Spi             = 0x00002000,   /* EEPROM is SPI not Microwire */
 190 };
 191
 192 enum {                                  /* Ctrlext */
 193         Gpien           = 0x0000000F,   /* General Purpose Interrupt Enables */
 194         SwdpinshiMASK   = 0x000000F0,   /* Software Defined Pins - hi nibble */
 195         SwdpinshiSHIFT  = 4,
 196         SwdpiohiMASK    = 0x00000F00,   /* Software Defined Pins - I or O */
 197         SwdpiohiSHIFT   = 8,
 198         Asdchk          = 0x00001000,   /* ASD Check */
 199         Eerst           = 0x00002000,   /* EEPROM Reset */
 200         Ips             = 0x00004000,   /* Invert Power State */
 201         Spdbyps         = 0x00008000,   /* Speed Select Bypass */
 202 };
 203
 204 enum {                                  /* EEPROM content offsets */
 205         Ea              = 0x00,         /* Ethernet Address */
 206         Cf              = 0x03,         /* Compatibility Field */
 207         Pba             = 0x08,         /* Printed Board Assembly number */
 208         Icw1            = 0x0A,         /* Initialization Control Word 1 */
 209         Sid             = 0x0B,         /* Subsystem ID */
 210         Svid            = 0x0C,         /* Subsystem Vendor ID */
 211         Did             = 0x0D,         /* Device ID */
 212         Vid             = 0x0E,         /* Vendor ID */
 213         Icw2            = 0x0F,         /* Initialization Control Word 2 */
 214 };
 215
 216 enum {                                  /* Mdic */
 217         MDIdMASK        = 0x0000FFFF,   /* Data */
 218         MDIdSHIFT       = 0,
 219         MDIrMASK        = 0x001F0000,   /* PHY Register Address */
 220         MDIrSHIFT       = 16,
 221         MDIpMASK        = 0x03E00000,   /* PHY Address */
 222         MDIpSHIFT       = 21,
 223         MDIwop          = 0x04000000,   /* Write Operation */
 224         MDIrop          = 0x08000000,   /* Read Operation */
 225         MDIready        = 0x10000000,   /* End of Transaction */
 226         MDIie           = 0x20000000,   /* Interrupt Enable */
 227         MDIe            = 0x40000000,   /* Error */
 228 };
 229
 230 enum {                                  /* Icr, Ics, Ims, Imc */
 231         Txdw            = 0x00000001,   /* Transmit Descriptor Written Back */
 232         Txqe            = 0x00000002,   /* Transmit Queue Empty */
 233         Lsc             = 0x00000004,   /* Link Status Change */
 234         Rxseq           = 0x00000008,   /* Receive Sequence Error */
 235         Rxdmt0          = 0x00000010,   /* Rdesc Minimum Threshold Reached */
 236         Rxo             = 0x00000040,   /* Receiver Overrun */
 237         Rxt0            = 0x00000080,   /* Receiver Timer Interrupt */
 238         Mdac            = 0x00000200,   /* MDIO Access Completed */
 239         Rxcfg           = 0x00000400,   /* Receiving /C/ ordered sets */
 240         Gpi0            = 0x00000800,   /* General Purpose Interrupts */
 241         Gpi1            = 0x00001000,
 242         Gpi2            = 0x00002000,
 243         Gpi3            = 0x00004000,
 244 };
 245
 246 /*
 247  * The Mdic register isn't implemented on the 82543GC,
 248  * the software defined pins are used instead.
 249  * These definitions work for the Intel PRO/1000 T Server Adapter.
 250  * The direction pin bits are read from the EEPROM.
 251  */
 252 enum {
 253         Mdd             = ((1<<2)<<SwdpinsloSHIFT),     /* data */
 254         Mddo            = ((1<<2)<<SwdpioloSHIFT),      /* pin direction */
 255         Mdc             = ((1<<3)<<SwdpinsloSHIFT),     /* clock */
 256         Mdco            = ((1<<3)<<SwdpioloSHIFT),      /* pin direction */
 257         Mdr             = ((1<<0)<<SwdpinshiSHIFT),     /* reset */
 258         Mdro            = ((1<<0)<<SwdpiohiSHIFT),      /* pin direction */
 259 };
 260
 261 enum {                                  /* Txcw */
 262         TxcwFd          = 0x00000020,   /* Full Duplex */
 263         TxcwHd          = 0x00000040,   /* Half Duplex */
 264         TxcwPauseMASK   = 0x00000180,   /* Pause */
 265         TxcwPauseSHIFT  = 7,
 266         TxcwPs          = (1<<TxcwPauseSHIFT),  /* Pause Supported */
 267         TxcwAs          = (2<<TxcwPauseSHIFT),  /* Asymmetric FC desired */
 268         TxcwRfiMASK     = 0x00003000,   /* Remote Fault Indication */
 269         TxcwRfiSHIFT    = 12,
 270         TxcwNpr         = 0x00008000,   /* Next Page Request */
 271         TxcwConfig      = 0x40000000,   /* Transmit COnfig Control */
 272         TxcwAne         = 0x80000000,   /* Auto-Negotiation Enable */
 273 };
 274
 275 enum {                                  /* Rctl */
 276         Rrst            = 0x00000001,   /* Receiver Software Reset */
 277         Ren             = 0x00000002,   /* Receiver Enable */
 278         Sbp             = 0x00000004,   /* Store Bad Packets */
 279         Upe             = 0x00000008,   /* Unicast Promiscuous Enable */
 280         Mpe             = 0x00000010,   /* Multicast Promiscuous Enable */
 281         Lpe             = 0x00000020,   /* Long Packet Reception Enable */
 282         LbmMASK         = 0x000000C0,   /* Loopback Mode */
 283         LbmOFF          = 0x00000000,   /* No Loopback */
 284         LbmTBI          = 0x00000040,   /* TBI Loopback */
 285         LbmMII          = 0x00000080,   /* GMII/MII Loopback */
 286         LbmXCVR         = 0x000000C0,   /* Transceiver Loopback */
 287         RdtmsMASK       = 0x00000300,   /* Rdesc Minimum Threshold Size */
 288         RdtmsHALF       = 0x00000000,   /* Threshold is 1/2 Rdlen */
 289         RdtmsQUARTER    = 0x00000100,   /* Threshold is 1/4 Rdlen */
 290         RdtmsEIGHTH     = 0x00000200,   /* Threshold is 1/8 Rdlen */
 291         MoMASK          = 0x00003000,   /* Multicast Offset */
 292         Bam             = 0x00008000,   /* Broadcast Accept Mode */
 293         BsizeMASK       = 0x00030000,   /* Receive Buffer Size */
 294         Bsize2048       = 0x00000000,
 295         Bsize1024       = 0x00010000,
 296         Bsize512        = 0x00020000,
 297         Bsize256        = 0x00030000,
 298         Vfe             = 0x00040000,   /* VLAN Filter Enable */
 299         Cfien           = 0x00080000,   /* Canonical Form Indicator Enable */
 300         Cfi             = 0x00100000,   /* Canonical Form Indicator value */
 301         Dpf             = 0x00400000,   /* Discard Pause Frames */
 302         Pmcf            = 0x00800000,   /* Pass MAC Control Frames */
 303         Bsex            = 0x02000000,   /* Buffer Size Extension */
 304         Secrc           = 0x04000000,   /* Strip CRC from incoming packet */
 305 };
 306
 307 enum {                                  /* Tctl */
 308         Trst            = 0x00000001,   /* Transmitter Software Reset */
 309         Ten             = 0x00000002,   /* Transmit Enable */
 310         Psp             = 0x00000008,   /* Pad Short Packets */
 311         CtMASK          = 0x00000FF0,   /* Collision Threshold */
 312         CtSHIFT         = 4,
 313         ColdMASK        = 0x003FF000,   /* Collision Distance */
 314         ColdSHIFT       = 12,
 315         Swxoff          = 0x00400000,   /* Sofware XOFF Transmission */
 316         Pbe             = 0x00800000,   /* Packet Burst Enable */
 317         Rtlc            = 0x01000000,   /* Re-transmit on Late Collision */
 318         Nrtu            = 0x02000000,   /* No Re-transmit on Underrrun */
 319 };
 320
 321 enum {                                  /* [RT]xdctl */
 322         PthreshMASK     = 0x0000003F,   /* Prefetch Threshold */
 323         PthreshSHIFT    = 0,
 324         HthreshMASK     = 0x00003F00,   /* Host Threshold */
 325         HthreshSHIFT    = 8,
 326         WthreshMASK     = 0x003F0000,   /* Writebacj Threshold */
 327         WthreshSHIFT    = 16,
 328         Gran            = 0x01000000,   /* Granularity */
 329 };
 330
 331 enum {                                  /* Rxcsum */
 332         PcssMASK        = 0x000000FF,   /* Packet Checksum Start */
 333         PcssSHIFT       = 0,
 334         Ipofl           = 0x00000100,   /* IP Checksum Off-load Enable */
 335         Tuofl           = 0x00000200,   /* TCP/UDP Checksum Off-load Enable */
 336 };
 337
 338 enum {                                  /* Manc */
 339         Arpen           = 0x00002000,   /* Enable ARP Request Filtering */
 340 };
 341
 342 typedef struct Rdesc {                  /* Receive Descriptor */
 343         uint    addr[2];
 344         ushort  length;
 345         ushort  checksum;
 346         uchar   status;
 347         uchar   errors;
 348         ushort  special;
 349 } Rdesc;
 350
 351 enum {                                  /* Rdesc status */
 352         Rdd             = 0x01,         /* Descriptor Done */
 353         Reop            = 0x02,         /* End of Packet */
 354         Ixsm            = 0x04,         /* Ignore Checksum Indication */
 355         Vp              = 0x08,         /* Packet is 802.1Q (matched VET) */
 356         Tcpcs           = 0x20,         /* TCP Checksum Calculated on Packet */
 357         Ipcs            = 0x40,         /* IP Checksum Calculated on Packet */
 358         Pif             = 0x80,         /* Passed in-exact filter */
 359 };
 360
 361 enum {                                  /* Rdesc errors */
 362         Ce              = 0x01,         /* CRC Error or Alignment Error */
 363         Se              = 0x02,         /* Symbol Error */
 364         Seq             = 0x04,         /* Sequence Error */
 365         Cxe             = 0x10,         /* Carrier Extension Error */
 366         Tcpe            = 0x20,         /* TCP/UDP Checksum Error */
 367         Ipe             = 0x40,         /* IP Checksum Error */
 368         Rxe             = 0x80,         /* RX Data Error */
 369 };
 370
 371 typedef struct Tdesc {                  /* Legacy+Normal Transmit Descriptor */
 372         uint    addr[2];
 373         uint    control;                /* varies with descriptor type */
 374         uint    status;                 /* varies with descriptor type */
 375 } Tdesc;
 376
 377 enum {                                  /* Tdesc control */
 378         LenMASK         = 0x000FFFFF,   /* Data/Packet Length Field */
 379         LenSHIFT        = 0,
 380         DtypeCD         = 0x00000000,   /* Data Type 'Context Descriptor' */
 381         DtypeDD         = 0x00100000,   /* Data Type 'Data Descriptor' */
 382         PtypeTCP        = 0x01000000,   /* TCP/UDP Packet Type (CD) */
 383         Teop            = 0x01000000,   /* End of Packet (DD) */
 384         PtypeIP         = 0x02000000,   /* IP Packet Type (CD) */
 385         Ifcs            = 0x02000000,   /* Insert FCS (DD) */
 386         Tse             = 0x04000000,   /* TCP Segmentation Enable */
 387         Rs              = 0x08000000,   /* Report Status */
 388         Rps             = 0x10000000,   /* Report Status Sent */
 389         Dext            = 0x20000000,   /* Descriptor Extension */
 390         Vle             = 0x40000000,   /* VLAN Packet Enable */
 391         Ide             = 0x80000000,   /* Interrupt Delay Enable */
 392 };
 393
 394 enum {                                  /* Tdesc status */
 395         Tdd             = 0x00000001,   /* Descriptor Done */
 396         Ec              = 0x00000002,   /* Excess Collisions */
 397         Lc              = 0x00000004,   /* Late Collision */
 398         Tu              = 0x00000008,   /* Transmit Underrun */
 399         CssMASK         = 0x0000FF00,   /* Checksum Start Field */
 400         CssSHIFT        = 8,
 401 };
 402
 403 enum {
 404         Nrdesc          = 32,           /* multiple of 8 */
 405         Ntdesc          = 8,            /* multiple of 8 */
 406 };
 407
 408 typedef struct Ctlr Ctlr;
 409 typedef struct Ctlr {
 410         int     port;
 411         Pcidev* pcidev;
 412         Ctlr*   next;
 413         int     active;
 414         int     id;
 415         int     cls;
 416         ushort  eeprom[0x40];
 417
 418         int*    nic;
 419         Lock    imlock;
 420         int     im;                     /* interrupt mask */
 421
 422         Mii*    mii;
 423
 424         Lock    slock;
 425         uint    statistics[Nstatistics];
 426
 427         uchar   ra[Eaddrlen];           /* receive address */
 428         ulong   mta[128];               /* multicast table array */
 429
 430         Rdesc*  rdba;                   /* receive descriptor base address */
 431         Block** rb;                     /* receive buffers */
 432         int     rdh;                    /* receive descriptor head */
 433         int     rdt;                    /* receive descriptor tail */
 434
 435         Tdesc*  tdba;                   /* transmit descriptor base address */
 436         Lock    tdlock;
 437         Block** tb;                     /* transmit buffers */
 438         int     tdh;                    /* transmit descriptor head */
 439         int     tdt;                    /* transmit descriptor tail */
 440         int     ett;                    /* early transmit threshold */
 441
 442         int     txcw;
 443         int     fcrtl;
 444         int     fcrth;
 445
 446         /* bootstrap goo */
 447         Block*  bqhead; /* transmission queue */
 448         Block*  bqtail;
 449 } Ctlr;
 450
 451 static Ctlr* ctlrhead;
 452 static Ctlr* ctlrtail;
 453
 454 #define csr32r(c, r)    (*((c)->nic+((r)/4)))
 455 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
 456
 457 static void
 458 igbeim(Ctlr* ctlr, int im)
 459 {
 460         ilock(&ctlr->imlock);
 461         ctlr->im |= im;
 462         csr32w(ctlr, Ims, ctlr->im);
 463         iunlock(&ctlr->imlock);
 464 }
 465
 466 static void
 467 igbeattach(Ether* edev)
 468 {
 469         int ctl;
 470         Ctlr *ctlr;
 471
 472         /*
 473          * To do here:
 474          *      one-time stuff;
 475          *      start off a kproc for link status change:
 476          *              adjust queue length depending on speed;
 477          *              flow control.
 478          *      more needed here...
 479          */
 480         ctlr = edev->ctlr;
 481         igbeim(ctlr, 0);
 482         ctl = csr32r(ctlr, Rctl)|Ren;
 483         csr32w(ctlr, Rctl, ctl);
 484         ctl = csr32r(ctlr, Tctl)|Ten;
 485         csr32w(ctlr, Tctl, ctl);
 486 }
 487
 488 static char* statistics[Nstatistics] = {
 489         "CRC Error",
 490         "Alignment Error",
 491         "Symbol Error",
 492         "RX Error",
 493         "Missed Packets",
 494         "Single Collision",
 495         "Excessive Collisions",
 496         "Multiple Collision",
 497         "Late Collisions",
 498         nil,
 499         "Collision",
 500         "Transmit Underrun",
 501         "Defer",
 502         "Transmit - No CRS",
 503         "Sequence Error",
 504         "Carrier Extension Error",
 505         "Receive Error Length",
 506         nil,
 507         "XON Received",
 508         "XON Transmitted",
 509         "XOFF Received",
 510         "XOFF Transmitted",
 511         "FC Received Unsupported",
 512         "Packets Received (64 Bytes)",
 513         "Packets Received (65-127 Bytes)",
 514         "Packets Received (128-255 Bytes)",
 515         "Packets Received (256-511 Bytes)",
 516         "Packets Received (512-1023 Bytes)",
 517         "Packets Received (1024-1522 Bytes)",
 518         "Good Packets Received",
 519         "Broadcast Packets Received",
 520         "Multicast Packets Received",
 521         "Good Packets Transmitted",
 522         nil,
 523         "Good Octets Received",
 524         nil,
 525         "Good Octets Transmitted",
 526         nil,
 527         nil,
 528         nil,
 529         "Receive No Buffers",
 530         "Receive Undersize",
 531         "Receive Fragment",
 532         "Receive Oversize",
 533         "Receive Jabber",
 534         nil,
 535         nil,
 536         nil,
 537         "Total Octets Received",
 538         nil,
 539         "Total Octets Transmitted",
 540         nil,
 541         "Total Packets Received",
 542         "Total Packets Transmitted",
 543         "Packets Transmitted (64 Bytes)",
 544         "Packets Transmitted (65-127 Bytes)",
 545         "Packets Transmitted (128-255 Bytes)",
 546         "Packets Transmitted (256-511 Bytes)",
 547         "Packets Transmitted (512-1023 Bytes)",
 548         "Packets Transmitted (1024-1522 Bytes)",
 549         "Multicast Packets Transmitted",
 550         "Broadcast Packets Transmitted",
 551         "TCP Segmentation Context Transmitted",
 552         "TCP Segmentation Context Fail",
 553 };
 554
 555 static void
 556 txstart(Ether *edev)
 557 {
 558         int tdh, tdt, len, olen;
 559         Ctlr *ctlr = edev->ctlr;
 560         Block *bp;
 561         Tdesc *tdesc;
 562
 563         /*
 564          * Try to fill the ring back up, moving buffers from the transmit q.
 565          */
 566         tdh = PREV(ctlr->tdh, Ntdesc);
 567         for(tdt = ctlr->tdt; tdt != tdh; tdt = NEXT(tdt, Ntdesc)){
 568                 /* pull off the head of the transmission queue */
 569                 if((bp = ctlr->bqhead) == nil)          /* was qget(edev->oq) */
 570                         break;
 571                 ctlr->bqhead = bp->next;
 572                 if (ctlr->bqtail == bp)
 573                         ctlr->bqtail = nil;
 574                 len = olen = BLEN(bp);
 575
 576                 /*
 577                  * if packet is too short, make it longer rather than relying
 578                  * on ethernet interface to pad it and complain so the caller
 579                  * will get fixed.  I don't think Psp is working right, or it's
 580                  * getting cleared.
 581                  */
 582                 if (len < ETHERMINTU) {
 583                         if (bp->rp + ETHERMINTU <= bp->lim)
 584                                 bp->wp = bp->rp + ETHERMINTU;
 585                         else
 586                                 bp->wp = bp->lim;
 587                         len = BLEN(bp);
 588                         print("txstart: extended short pkt %d -> %d bytes\n",
 589                                 olen, len);
 590                 }
 591
 592                 /* set up a descriptor for it */
 593                 tdesc = &ctlr->tdba[tdt];
 594                 tdesc->addr[0] = PCIWADDR(bp->rp);
 595                 tdesc->addr[1] = 0;
 596                 tdesc->control = /* Ide| */ Rs|Dext|Ifcs|Teop|DtypeDD|len;
 597                 tdesc->status = 0;
 598
 599                 ctlr->tb[tdt] = bp;
 600         }
 601         ctlr->tdt = tdt;
 602         csr32w(ctlr, Tdt, tdt);
 603         igbeim(ctlr, Txdw);
 604 }
 605
 606 static Block *
 607 fromringbuf(Ether *ether)
 608 {
 609         RingBuf *tb = &ether->tb[ether->ti];
 610         Block *bp = allocb(tb->len);
 611
 612         memmove(bp->wp, tb->pkt, tb->len);
 613         memmove(bp->wp+Eaddrlen, ether->ea, Eaddrlen);
 614         bp->wp += tb->len;
 615         return bp;
 616 }
 617
 618 static void
 619 igbetransmit(Ether* edev)
 620 {
 621         Block *bp;
 622         Ctlr *ctlr;
 623         Tdesc *tdesc;
 624         RingBuf *tb;
 625         int tdh;
 626
 627         /*
 628          * For now there are no smarts here. Tuning comes later.
 629          */
 630         ctlr = edev->ctlr;
 631         ilock(&ctlr->tdlock);
 632
 633         /*
 634          * Free any completed packets
 635          * - try to get the soft tdh to catch the tdt;
 636          * - if the packet had an underrun bump the threshold
 637          *   - the Tu bit doesn't seem to ever be set, perhaps
 638          *     because Rs mode is used?
 639          */
 640         tdh = ctlr->tdh;
 641         for(;;){
 642                 tdesc = &ctlr->tdba[tdh];
 643                 if(!(tdesc->status & Tdd))
 644                         break;
 645                 if(tdesc->status & Tu){
 646                         ctlr->ett++;
 647                         csr32w(ctlr, Ett, ctlr->ett);
 648                 }
 649                 tdesc->status = 0;
 650                 if(ctlr->tb[tdh] != nil){
 651                         freeb(ctlr->tb[tdh]);
 652                         ctlr->tb[tdh] = nil;
 653                 }
 654                 tdh = NEXT(tdh, Ntdesc);
 655         }
 656         ctlr->tdh = tdh;
 657
 658         /* copy packets from the software RingBuf to the transmission q */
 659         /* from boot ether83815.c */
 660         while((tb = &edev->tb[edev->ti])->owner == Interface){
 661                 bp = fromringbuf(edev);
 662
 663                 /* put the buffer on the transmit queue */
 664                 if(ctlr->bqhead)
 665                         ctlr->bqtail->next = bp;
 666                 else
 667                         ctlr->bqhead = bp;
 668                 ctlr->bqtail = bp;
 669
 670                 txstart(edev);          /* kick transmitter */
 671                 tb->owner = Host;       /* give descriptor back */
 672
 673                 edev->ti = NEXT(edev->ti, edev->ntb);
 674         }
 675
 676         iunlock(&ctlr->tdlock);
 677 }
 678
 679 static void
 680 igbereplenish(Ctlr* ctlr)
 681 {
 682         int rdt;
 683         Block *bp;
 684         Rdesc *rdesc;
 685
 686         rdt = ctlr->rdt;
 687         while(NEXT(rdt, Nrdesc) != ctlr->rdh){
 688                 rdesc = &ctlr->rdba[rdt];
 689                 if(ctlr->rb[rdt] != nil){
 690                         /* nothing to do */
 691                 }
 692                 else if((bp = iallocb(2048)) != nil){
 693                         ctlr->rb[rdt] = bp;
 694                         rdesc->addr[0] = PCIWADDR(bp->rp);
 695                         rdesc->addr[1] = 0;
 696                 }
 697                 else
 698                         break;
 699                 rdesc->status = 0;
 700
 701                 rdt = NEXT(rdt, Nrdesc);
 702         }
 703         ctlr->rdt = rdt;
 704         csr32w(ctlr, Rdt, rdt);
 705 }
 706
 707 static void
 708 toringbuf(Ether *ether, Block *bp)
 709 {
 710         RingBuf *rb = &ether->rb[ether->ri];
 711
 712         if (rb->owner == Interface) {
 713                 rb->len = BLEN(bp);
 714                 memmove(rb->pkt, bp->rp, rb->len);
 715                 rb->owner = Host;
 716                 ether->ri = NEXT(ether->ri, ether->nrb);
 717         }
 718         /* else no one is expecting packets from the network */
 719 }
 720
 721 static void
 722 igbeinterrupt(Ureg*, void* arg)
 723 {
 724         Block *bp;
 725         Ctlr *ctlr;
 726         Ether *edev;
 727         Rdesc *rdesc;
 728         int icr, im, rdh, txdw = 0;
 729
 730         edev = arg;
 731         ctlr = edev->ctlr;
 732
 733         ilock(&ctlr->imlock);
 734         csr32w(ctlr, Imc, ~0);
 735         im = ctlr->im;
 736
 737         for(icr = csr32r(ctlr, Icr); icr & ctlr->im; icr = csr32r(ctlr, Icr)){
 738                 /*
 739                  * Link status changed.
 740                  */
 741                 if(icr & (Rxseq|Lsc)){
 742                         /*
 743                          * should be more here...
 744                          */
 745                 }
 746
 747                 /*
 748                  * Process any received packets.
 749                  */
 750                 rdh = ctlr->rdh;
 751                 for(;;){
 752                         rdesc = &ctlr->rdba[rdh];
 753                         if(!(rdesc->status & Rdd))
 754                                 break;
 755                         if ((rdesc->status & Reop) && rdesc->errors == 0) {
 756                                 bp = ctlr->rb[rdh];
 757                                 ctlr->rb[rdh] = nil;
 758                                 /*
 759                                  * it appears that the original 82543 needed
 760                                  * to have the Ethernet CRC excluded, but that
 761                                  * the newer chips do not?
 762                                  */
 763                                 bp->wp += rdesc->length /* -4 */;
 764                                 toringbuf(edev, bp);
 765                                 freeb(bp);
 766                         } else if ((rdesc->status & Reop) && rdesc->errors)
 767                                 print("igbe: input packet error 0x%ux\n",
 768                                         rdesc->errors);
 769                         rdesc->status = 0;
 770                         rdh = NEXT(rdh, Nrdesc);
 771                 }
 772                 ctlr->rdh = rdh;
 773
 774                 if(icr & Rxdmt0)
 775                         igbereplenish(ctlr);
 776                 if(icr & Txdw){
 777                         im &= ~Txdw;
 778                         txdw++;
 779                 }
 780         }
 781
 782         ctlr->im = im;
 783         csr32w(ctlr, Ims, im);
 784         iunlock(&ctlr->imlock);
 785
 786         if(txdw)
 787                 igbetransmit(edev);
 788 }
 789
 790 static int
 791 igbeinit(Ether* edev)
 792 {
 793         int csr, i, r, ctrl;
 794         MiiPhy *phy;
 795         Ctlr *ctlr;
 796
 797         ctlr = edev->ctlr;
 798
 799         /*
 800          * Set up the receive addresses.
 801          * There are 16 addresses. The first should be the MAC address.
 802          * The others are cleared and not marked valid (MS bit of Rah).
 803          */
 804         csr = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
 805         csr32w(ctlr, Ral, csr);
 806         csr = 0x80000000|(edev->ea[5]<<8)|edev->ea[4];
 807         csr32w(ctlr, Rah, csr);
 808         for(i = 1; i < 16; i++){
 809                 csr32w(ctlr, Ral+i*8, 0);
 810                 csr32w(ctlr, Rah+i*8, 0);
 811         }
 812
 813         /*
 814          * Clear the Multicast Table Array.
 815          * It's a 4096 bit vector accessed as 128 32-bit registers.
 816          */
 817         for(i = 0; i < 128; i++)
 818                 csr32w(ctlr, Mta+i*4, 0);
 819
 820         /*
 821          * Receive initialisation.
 822          * Mostly defaults from the datasheet, will
 823          * need some tuning for performance:
 824          *      Rctl    descriptor mimimum threshold size
 825          *              discard pause frames
 826          *              strip CRC
 827          *      Rdtr    interrupt delay
 828          *      Rxdctl  all the thresholds
 829          */
 830         csr32w(ctlr, Rctl, 0);
 831
 832         /*
 833          * Allocate the descriptor ring and load its
 834          * address and length into the NIC.
 835          */
 836         ctlr->rdba = xspanalloc(Nrdesc*sizeof(Rdesc), 128 /* was 16 */, 0);
 837         csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
 838         csr32w(ctlr, Rdbah, 0);
 839         csr32w(ctlr, Rdlen, Nrdesc*sizeof(Rdesc));
 840
 841         /*
 842          * Initialise the ring head and tail pointers and
 843          * populate the ring with Blocks.
 844          * The datasheet says the tail pointer is set to beyond the last
 845          * descriptor hardware can process, which implies the initial
 846          * condition is Rdh == Rdt. However, experience shows Rdt must
 847          * always be 'behind' Rdh; the replenish routine ensures this.
 848          */
 849         ctlr->rdh = 0;
 850         csr32w(ctlr, Rdh, ctlr->rdh);
 851         ctlr->rdt = 0;
 852         csr32w(ctlr, Rdt, ctlr->rdt);
 853         ctlr->rb = malloc(sizeof(Block*)*Nrdesc);
 854         igbereplenish(ctlr);
 855
 856         /*
 857          * Set up Rctl but don't enable receiver (yet).
 858          */
 859         csr32w(ctlr, Rdtr, 0);
 860         switch(ctlr->id){
 861         case i82540em:
 862         case i82540eplp:
 863         case i82541gi:
 864         case i82541gi2:
 865         case i82541pi:
 866         case i82545em:
 867         case i82545gmc:
 868         case i82546gb:
 869         case i82546eb:
 870         case i82547gi:
 871                 csr32w(ctlr, Radv, 64);
 872                 break;
 873         }
 874         csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
 875         /*
 876          * Enable checksum offload.
 877          */
 878         csr32w(ctlr, Rxcsum, Tuofl|Ipofl|(ETHERHDRSIZE<<PcssSHIFT));
 879
 880         csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF);
 881         igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
 882
 883         /*
 884          * Transmit initialisation.
 885          * Mostly defaults from the datasheet, will
 886          * need some tuning for performance. The normal mode will
 887          * be full-duplex and things to tune for half-duplex are
 888          *      Tctl    re-transmit on late collision
 889          *      Tipg    all IPG times
 890          *      Tbt     burst timer
 891          *      Ait     adaptive IFS throttle
 892          * and in general
 893          *      Txdmac  packet prefetching
 894          *      Ett     transmit early threshold
 895          *      Tidv    interrupt delay value
 896          *      Txdctl  all the thresholds
 897          */
 898         csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT));        /* Fd */
 899         switch(ctlr->id){
 900         default:
 901                 r = 6;
 902                 break;
 903         case i82543gc:
 904         case i82544ei:
 905         case i82544eif:
 906         case i82544gc:
 907         case i82540em:
 908         case i82540eplp:
 909         case i82541ei:
 910         case i82541gi:
 911         case i82541gi2:
 912         case i82541pi:
 913         case i82546gb:
 914         case i82546eb:
 915         case i82547gi:
 916         case i82547ei:
 917         case i82545em:
 918         case i82545gmc:
 919                 r = 8;
 920                 break;
 921         }
 922         csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r);
 923         csr32w(ctlr, Ait, 0);
 924         csr32w(ctlr, Txdmac, 0);
 925         csr32w(ctlr, Tidv, 128);
 926
 927         /*
 928          * Allocate the descriptor ring and load its
 929          * address and length into the NIC.
 930          */
 931         ctlr->tdba = xspanalloc(Ntdesc*sizeof(Tdesc), 128 /* was 16 */, 0);
 932         csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
 933         csr32w(ctlr, Tdbah, 0);
 934         csr32w(ctlr, Tdlen, Ntdesc*sizeof(Tdesc));
 935
 936         /*
 937          * Initialise the ring head and tail pointers.
 938          */
 939         ctlr->tdh = 0;
 940         csr32w(ctlr, Tdh, ctlr->tdh);
 941         ctlr->tdt = 0;
 942         csr32w(ctlr, Tdt, ctlr->tdt);
 943         ctlr->tb = malloc(sizeof(Block*)*Ntdesc);
 944 //      ctlr->im |= Txqe|Txdw;
 945
 946         r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
 947         switch(ctlr->id){
 948         default:
 949                 break;
 950         case i82540em:
 951         case i82540eplp:
 952         case i82547gi:
 953         case i82545em:
 954         case i82545gmc:
 955         case i82546gb:
 956         case i82546eb:
 957         case i82541gi:
 958         case i82541gi2:
 959         case i82541pi:
 960                 r = csr32r(ctlr, Txdctl);
 961                 r &= ~WthreshMASK;
 962                 r |= Gran|(4<<WthreshSHIFT);
 963
 964                 csr32w(ctlr, Tadv, 64);
 965                 break;
 966         }
 967         csr32w(ctlr, Txdctl, r);
 968
 969         r = csr32r(ctlr, Tctl);
 970         r |= Ten;
 971         csr32w(ctlr, Tctl, r);
 972
 973         if(ctlr->mii == nil || ctlr->mii->curphy == nil) {
 974                 print("igbe: no mii (yet)\n");
 975                 return 0;
 976         }
 977         /* wait for the link to come up */
 978         if (miistatus(ctlr->mii) < 0)
 979                 return -1;
 980         print("igbe: phy: ");
 981         phy = ctlr->mii->curphy;
 982         if (phy->fd)
 983                 print("full duplex");
 984         else
 985                 print("half duplex");
 986         print(", %d Mb/s\n", phy->speed);
 987
 988         /*
 989          * Flow control.
 990          */
 991         ctrl = csr32r(ctlr, Ctrl);
 992         if(phy->rfc)
 993                 ctrl |= Rfce;
 994         if(phy->tfc)
 995                 ctrl |= Tfce;
 996         csr32w(ctlr, Ctrl, ctrl);
 997
 998         return 0;
 999 }
1000
1001 static int
1002 i82543mdior(Ctlr* ctlr, int n)
1003 {
1004         int ctrl, data, i, r;
1005
1006         /*
1007          * Read n bits from the Management Data I/O Interface.
1008          */
1009         ctrl = csr32r(ctlr, Ctrl);
1010         r = (ctrl & ~Mddo)|Mdco;
1011         data = 0;
1012         for(i = n-1; i >= 0; i--){
1013                 if(csr32r(ctlr, Ctrl) & Mdd)
1014                         data |= (1<<i);
1015                 csr32w(ctlr, Ctrl, Mdc|r);
1016                 csr32w(ctlr, Ctrl, r);
1017         }
1018         csr32w(ctlr, Ctrl, ctrl);
1019
1020         return data;
1021 }
1022
1023 static int
1024 i82543mdiow(Ctlr* ctlr, int bits, int n)
1025 {
1026         int ctrl, i, r;
1027
1028         /*
1029          * Write n bits to the Management Data I/O Interface.
1030          */
1031         ctrl = csr32r(ctlr, Ctrl);
1032         r = Mdco|Mddo|ctrl;
1033         for(i = n-1; i >= 0; i--){
1034                 if(bits & (1<<i))
1035                         r |= Mdd;
1036                 else
1037                         r &= ~Mdd;
1038                 csr32w(ctlr, Ctrl, Mdc|r);
1039                 csr32w(ctlr, Ctrl, r);
1040         }
1041         csr32w(ctlr, Ctrl, ctrl);
1042
1043         return 0;
1044 }
1045
1046 static int
1047 i82543miimir(Mii* mii, int pa, int ra)
1048 {
1049         int data;
1050         Ctlr *ctlr;
1051
1052         ctlr = mii->ctlr;
1053
1054         /*
1055          * MII Management Interface Read.
1056          *
1057          * Preamble;
1058          * ST+OP+PHYAD+REGAD;
1059          * TA + 16 data bits.
1060          */
1061         i82543mdiow(ctlr, 0xFFFFFFFF, 32);
1062         i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
1063         data = i82543mdior(ctlr, 18);
1064
1065         if(data & 0x10000)
1066                 return -1;
1067
1068         return data & 0xFFFF;
1069 }
1070
1071 static int
1072 i82543miimiw(Mii* mii, int pa, int ra, int data)
1073 {
1074         Ctlr *ctlr;
1075
1076         ctlr = mii->ctlr;
1077
1078         /*
1079          * MII Management Interface Write.
1080          *
1081          * Preamble;
1082          * ST+OP+PHYAD+REGAD+TA + 16 data bits;
1083          * Z.
1084          */
1085         i82543mdiow(ctlr, 0xFFFFFFFF, 32);
1086         data &= 0xFFFF;
1087         data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
1088         i82543mdiow(ctlr, data, 32);
1089
1090         return 0;
1091 }
1092
1093 static int
1094 igbemiimir(Mii* mii, int pa, int ra)
1095 {
1096         Ctlr *ctlr;
1097         int mdic, timo;
1098
1099         ctlr = mii->ctlr;
1100
1101         csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT));
1102         mdic = 0;
1103         for(timo = 64; timo; timo--){
1104                 mdic = csr32r(ctlr, Mdic);
1105                 if(mdic & (MDIe|MDIready))
1106                         break;
1107                 microdelay(1);
1108         }
1109
1110         if((mdic & (MDIe|MDIready)) == MDIready)
1111                 return mdic & 0xFFFF;
1112         return -1;
1113 }
1114
1115 static int
1116 igbemiimiw(Mii* mii, int pa, int ra, int data)
1117 {
1118         Ctlr *ctlr;
1119         int mdic, timo;
1120
1121         ctlr = mii->ctlr;
1122
1123         data &= MDIdMASK;
1124         csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data);
1125         mdic = 0;
1126         for(timo = 64; timo; timo--){
1127                 mdic = csr32r(ctlr, Mdic);
1128                 if(mdic & (MDIe|MDIready))
1129                         break;
1130                 microdelay(1);
1131         }
1132         if((mdic & (MDIe|MDIready)) == MDIready)
1133                 return 0;
1134         return -1;
1135 }
1136
1137 static int
1138 igbemii(Ctlr* ctlr)
1139 {
1140         MiiPhy *phy = (MiiPhy *)1;
1141         int ctrl, p, r;
1142
1143         USED(phy);
1144         r = csr32r(ctlr, Status);
1145         if(r & Tbimode)
1146                 return -1;
1147         if((ctlr->mii = malloc(sizeof(Mii))) == nil)
1148                 return -1;
1149         ctlr->mii->ctlr = ctlr;
1150
1151         ctrl = csr32r(ctlr, Ctrl);
1152         ctrl |= Slu;
1153
1154         switch(ctlr->id){
1155         case i82543gc:
1156                 ctrl |= Frcdplx|Frcspd;
1157                 csr32w(ctlr, Ctrl, ctrl);
1158
1159                 /*
1160                  * The reset pin direction (Mdro) should already
1161                  * be set from the EEPROM load.
1162                  * If it's not set this configuration is unexpected
1163                  * so bail.
1164                  */
1165                 r = csr32r(ctlr, Ctrlext);
1166                 if(!(r & Mdro))
1167                         return -1;
1168                 csr32w(ctlr, Ctrlext, r);
1169                 delay(20);
1170                 r = csr32r(ctlr, Ctrlext);
1171                 r &= ~Mdr;
1172                 csr32w(ctlr, Ctrlext, r);
1173                 delay(20);
1174                 r = csr32r(ctlr, Ctrlext);
1175                 r |= Mdr;
1176                 csr32w(ctlr, Ctrlext, r);
1177                 delay(20);
1178
1179                 ctlr->mii->mir = i82543miimir;
1180                 ctlr->mii->miw = i82543miimiw;
1181                 break;
1182         case i82544ei:
1183         case i82544eif:
1184         case i82544gc:
1185         case i82540em:
1186         case i82540eplp:
1187         case i82547ei:
1188         case i82547gi:
1189         case i82541gi:
1190         case i82541gi2:
1191         case i82541pi:
1192         case i82545em:
1193         case i82545gmc:
1194         case i82546gb:
1195         case i82546eb:
1196                 ctrl &= ~(Frcdplx|Frcspd);
1197                 csr32w(ctlr, Ctrl, ctrl);
1198                 ctlr->mii->mir = igbemiimir;
1199                 ctlr->mii->miw = igbemiimiw;
1200                 break;
1201         default:
1202                 free(ctlr->mii);
1203                 ctlr->mii = nil;
1204                 return -1;
1205         }
1206
1207         if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
1208                 if (0)
1209                         print("phy trouble: phy = 0x%lux\n", (ulong)phy);
1210                 free(ctlr->mii);
1211                 ctlr->mii = nil;
1212                 return -1;
1213         }
1214         if (Debug)
1215                 print("oui %X phyno %d\n", phy->oui, phy->phyno);
1216         else
1217                 USED(phy);
1218
1219         /*
1220          * 8254X-specific PHY registers not in 802.3:
1221          *      0x10    PHY specific control
1222          *      0x14    extended PHY specific control
1223          * Set appropriate values then reset the PHY to have
1224          * changes noted.
1225          */
1226         switch(ctlr->id){
1227         case i82547gi:
1228         case i82541gi:
1229         case i82541gi2:
1230         case i82541pi:
1231         case i82545em:
1232         case i82545gmc:
1233         case i82546gb:
1234         case i82546eb:
1235                 break;
1236         default:
1237                 r = miimir(ctlr->mii, 16);
1238                 r |= 0x0800;                    /* assert CRS on Tx */
1239                 r |= 0x0060;                    /* auto-crossover all speeds */
1240                 r |= 0x0002;                    /* polarity reversal enabled */
1241                 miimiw(ctlr->mii, 16, r);
1242
1243                 r = miimir(ctlr->mii, 20);
1244                 r |= 0x0070;                    /* +25MHz clock */
1245                 r &= ~0x0F00;
1246                 r |= 0x0100;                    /* 1x downshift */
1247                 miimiw(ctlr->mii, 20, r);
1248
1249                 miireset(ctlr->mii);
1250                 break;
1251         }
1252         p = 0;
1253         if(ctlr->txcw & TxcwPs)
1254                 p |= AnaP;
1255         if(ctlr->txcw & TxcwAs)
1256                 p |= AnaAP;
1257         miiane(ctlr->mii, ~0, p, ~0);
1258
1259         return 0;
1260 }
1261
1262 static int
1263 at93c46io(Ctlr* ctlr, char* op, int data)
1264 {
1265         char *lp, *p;
1266         int i, loop, eecd, r;
1267
1268         eecd = csr32r(ctlr, Eecd);
1269
1270         r = 0;
1271         loop = -1;
1272         lp = nil;
1273         for(p = op; *p != '\0'; p++){
1274                 switch(*p){
1275                 default:
1276                         return -1;
1277                 case ' ':
1278                         continue;
1279                 case ':':                       /* start of loop */
1280                         loop = strtol(p+1, &lp, 0)-1;
1281                         lp--;
1282                         if(p == lp)
1283                                 loop = 7;
1284                         p = lp;
1285                         continue;
1286                 case ';':                       /* end of loop */
1287                         if(lp == nil)
1288                                 return -1;
1289                         loop--;
1290                         if(loop >= 0)
1291                                 p = lp;
1292                         else
1293                                 lp = nil;
1294                         continue;
1295                 case 'C':                       /* assert clock */
1296                         eecd |= Sk;
1297                         break;
1298                 case 'c':                       /* deassert clock */
1299                         eecd &= ~Sk;
1300                         break;
1301                 case 'D':                       /* next bit in 'data' byte */
1302                         if(loop < 0)
1303                                 return -1;
1304                         if(data & (1<<loop))
1305                                 eecd |= Di;
1306                         else
1307                                 eecd &= ~Di;
1308                         break;
1309                 case 'O':                       /* collect data output */
1310                         i = (csr32r(ctlr, Eecd) & Do) != 0;
1311                         if(loop >= 0)
1312                                 r |= (i<<loop);
1313                         else
1314                                 r = i;
1315                         continue;
1316                 case 'I':                       /* assert data input */
1317                         eecd |= Di;
1318                         break;
1319                 case 'i':                       /* deassert data input */
1320                         eecd &= ~Di;
1321                         break;
1322                 case 'S':                       /* enable chip select */
1323                         eecd |= Cs;
1324                         break;
1325                 case 's':                       /* disable chip select */
1326                         eecd &= ~Cs;
1327                         break;
1328                 }
1329                 csr32w(ctlr, Eecd, eecd);
1330                 microdelay(50);
1331         }
1332         if(loop >= 0)
1333                 return -1;
1334         return r;
1335 }
1336
1337 static int
1338 at93c46r(Ctlr* ctlr)
1339 {
1340         ushort sum;
1341         char rop[20];
1342         int addr, areq, bits, data, eecd, i;
1343
1344         eecd = csr32r(ctlr, Eecd);
1345         if(eecd & Spi){
1346                 print("igbe: SPI EEPROM access not implemented\n");
1347                 return 0;
1348         }
1349         if(eecd & (Eeszaddr|Eesz256))
1350                 bits = 8;
1351         else
1352                 bits = 6;
1353         sum = 0;
1354
1355         switch(ctlr->id){
1356         default:
1357                 areq = 0;
1358                 break;
1359         case i82540em:
1360         case i82540eplp:
1361         case i82541ei:
1362         case i82541gi:
1363         case i82541gi2:
1364         case i82541pi:
1365         case i82545em:
1366         case i82545gmc:
1367         case i82546gb:
1368         case i82546eb:
1369         case i82547ei:
1370         case i82547gi:
1371                 areq = 1;
1372                 csr32w(ctlr, Eecd, eecd|Areq);
1373                 for(i = 0; i < 1000; i++){
1374                         if((eecd = csr32r(ctlr, Eecd)) & Agnt)
1375                                 break;
1376                         microdelay(5);
1377                 }
1378                 if(!(eecd & Agnt)){
1379                         print("igbe: not granted EEPROM access\n");
1380                         goto release;
1381                 }
1382                 break;
1383         }
1384         snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
1385
1386         for(addr = 0; addr < 0x40; addr++){
1387                 /*
1388                  * Read a word at address 'addr' from the Atmel AT93C46
1389                  * 3-Wire Serial EEPROM or compatible. The EEPROM access is
1390                  * controlled by 4 bits in Eecd. See the AT93C46 datasheet
1391                  * for protocol details.
1392                  */
1393                 if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
1394                         print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
1395                         goto release;
1396                 }
1397                 data = at93c46io(ctlr, ":16COc;", 0);
1398                 at93c46io(ctlr, "sic", 0);
1399                 ctlr->eeprom[addr] = data;
1400                 sum += data;
1401                 if (Debug) {
1402                         if(addr && ((addr & 0x07) == 0))
1403                                 print("\n");
1404                         print(" %4.4ux", data);
1405                 }
1406         }
1407         if (Debug)
1408                 print("\n");
1409 release:
1410         if(areq)
1411                 csr32w(ctlr, Eecd, eecd & ~Areq);
1412         return sum;
1413 }
1414
1415 static void
1416 detach(Ctlr *ctlr)
1417 {
1418         int r;
1419
1420         /*
1421          * Perform a device reset to get the chip back to the
1422          * power-on state, followed by an EEPROM reset to read
1423          * the defaults for some internal registers.
1424          */
1425         csr32w(ctlr, Imc, ~0);
1426         csr32w(ctlr, Rctl, 0);
1427         csr32w(ctlr, Tctl, 0);
1428
1429         delay(20);
1430
1431         csr32w(ctlr, Ctrl, Devrst);
1432         /* apparently needed on multi-GHz processors to avoid infinite loops */
1433         delay(1);
1434         while(csr32r(ctlr, Ctrl) & Devrst)
1435                 ;
1436
1437         csr32w(ctlr, Ctrlext, Eerst | csr32r(ctlr, Ctrlext));
1438         delay(1);
1439         while(csr32r(ctlr, Ctrlext) & Eerst)
1440                 ;
1441
1442         switch(ctlr->id){
1443         default:
1444                 break;
1445         case i82540em:
1446         case i82540eplp:
1447         case i82541gi:
1448         case i82541gi2:
1449         case i82541pi:
1450         case i82545em:
1451         case i82545gmc:
1452         case i82547gi:
1453         case i82546gb:
1454         case i82546eb:
1455                 r = csr32r(ctlr, Manc);
1456                 r &= ~Arpen;
1457                 csr32w(ctlr, Manc, r);
1458                 break;
1459         }
1460
1461         csr32w(ctlr, Imc, ~0);
1462         delay(1);
1463         while(csr32r(ctlr, Icr))
1464                 ;
1465 }
1466
1467 static void
1468 igbedetach(Ether *edev)
1469 {
1470         detach(edev->ctlr);
1471 }
1472
1473 static void
1474 igbeshutdown(Ether* ether)
1475 {
1476 print("igbeshutdown\n");
1477         igbedetach(ether);
1478 }
1479
1480 static int
1481 igbereset(Ctlr* ctlr)
1482 {
1483         int ctrl, i, pause, r, swdpio, txcw;
1484
1485         detach(ctlr);
1486
1487         /*
1488          * Read the EEPROM, validate the checksum
1489          * then get the device back to a power-on state.
1490          */
1491         r = at93c46r(ctlr);
1492         /* zero return means no SPI EEPROM access */
1493         if (r != 0 && r != 0xBABA){
1494                 print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r);
1495                 return -1;
1496         }
1497
1498         /*
1499          * Snarf and set up the receive addresses.
1500          * There are 16 addresses. The first should be the MAC address.
1501          * The others are cleared and not marked valid (MS bit of Rah).
1502          */
1503         if ((ctlr->id == i82546gb || ctlr->id == i82546eb) &&
1504             BUSFNO(ctlr->pcidev->tbdf) == 1)
1505                 ctlr->eeprom[Ea+2] += 0x100;            /* second interface */
1506         for(i = Ea; i < Eaddrlen/2; i++){
1507                 ctlr->ra[2*i]   = ctlr->eeprom[i];
1508                 ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
1509         }
1510         /* lan id seems to vary on 82543gc; don't use it */
1511         if (ctlr->id != i82543gc) {
1512                 r = (csr32r(ctlr, Status) & Lanid) >> 2;
1513                 ctlr->ra[5] += r;               /* ea ctlr[1] = ea ctlr[0]+1 */
1514         }
1515         r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
1516         csr32w(ctlr, Ral, r);
1517         r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
1518         csr32w(ctlr, Rah, r);
1519         for(i = 1; i < 16; i++){
1520                 csr32w(ctlr, Ral+i*8, 0);
1521                 csr32w(ctlr, Rah+i*8, 0);
1522         }
1523
1524         /*
1525          * Clear the Multicast Table Array.
1526          * It's a 4096 bit vector accessed as 128 32-bit registers.
1527          */
1528         memset(ctlr->mta, 0, sizeof(ctlr->mta));
1529         for(i = 0; i < 128; i++)
1530                 csr32w(ctlr, Mta+i*4, 0);
1531
1532         /*
1533          * Just in case the Eerst didn't load the defaults
1534          * (doesn't appear to fully on the 8243GC), do it manually.
1535          */
1536         if (ctlr->id == i82543gc) {
1537                 txcw = csr32r(ctlr, Txcw);
1538                 txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd);
1539                 ctrl = csr32r(ctlr, Ctrl);
1540                 ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd);
1541
1542                 if(ctlr->eeprom[Icw1] & 0x0400){
1543                         ctrl |= Fd;
1544                         txcw |= TxcwFd;
1545                 }
1546                 if(ctlr->eeprom[Icw1] & 0x0200)
1547                         ctrl |= Lrst;
1548                 if(ctlr->eeprom[Icw1] & 0x0010)
1549                         ctrl |= Ilos;
1550                 if(ctlr->eeprom[Icw1] & 0x0800)
1551                         ctrl |= Frcspd;
1552                 swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5;
1553                 ctrl |= swdpio<<SwdpioloSHIFT;
1554                 csr32w(ctlr, Ctrl, ctrl);
1555
1556                 ctrl = csr32r(ctlr, Ctrlext);
1557                 ctrl &= ~(Ips|SwdpiohiMASK);
1558                 swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4;
1559                 if(ctlr->eeprom[Icw1] & 0x1000)
1560                         ctrl |= Ips;
1561                 ctrl |= swdpio<<SwdpiohiSHIFT;
1562                 csr32w(ctlr, Ctrlext, ctrl);
1563
1564                 if(ctlr->eeprom[Icw2] & 0x0800)
1565                         txcw |= TxcwAne;
1566                 pause = (ctlr->eeprom[Icw2] & 0x3000)>>12;
1567                 txcw |= pause<<TxcwPauseSHIFT;
1568                 switch(pause){
1569                 default:
1570                         ctlr->fcrtl = 0x00002000;
1571                         ctlr->fcrth = 0x00004000;
1572                         txcw |= TxcwAs|TxcwPs;
1573                         break;
1574                 case 0:
1575                         ctlr->fcrtl = 0x00002000;
1576                         ctlr->fcrth = 0x00004000;
1577                         break;
1578                 case 2:
1579                         ctlr->fcrtl = 0;
1580                         ctlr->fcrth = 0;
1581                         txcw |= TxcwAs;
1582                         break;
1583                 }
1584                 ctlr->txcw = txcw;
1585                 csr32w(ctlr, Txcw, txcw);
1586         }
1587         /*
1588          * Flow control - values from the datasheet.
1589          */
1590         csr32w(ctlr, Fcal, 0x00C28001);
1591         csr32w(ctlr, Fcah, 0x00000100);
1592         csr32w(ctlr, Fct, 0x00008808);
1593         csr32w(ctlr, Fcttv, 0x00000100);
1594
1595         csr32w(ctlr, Fcrtl, ctlr->fcrtl);
1596         csr32w(ctlr, Fcrth, ctlr->fcrth);
1597
1598         ilock(&ctlr->imlock);
1599         csr32w(ctlr, Imc, ~0);
1600         ctlr->im = 0;           /* was = Lsc, which hangs some controllers */
1601         csr32w(ctlr, Ims, ctlr->im);
1602         iunlock(&ctlr->imlock);
1603
1604         if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0) {
1605                 print("igbe: igbemii failed\n");
1606                 return -1;
1607         }
1608
1609         return 0;
1610 }
1611
1612 static void
1613 igbepci(void)
1614 {
1615         int port, cls;
1616         Pcidev *p;
1617         Ctlr *ctlr;
1618         static int first = 1;
1619
1620         if (first)
1621                 first = 0;
1622         else
1623                 return;
1624
1625         p = nil;
1626         while(p = pcimatch(p, 0, 0)){
1627                 if(p->ccrb != 0x02 || p->ccru != 0)
1628                         continue;
1629
1630                 switch((p->did<<16)|p->vid){
1631                 case i82542:
1632                 default:
1633                         continue;
1634
1635                 case (0x1001<<16)|0x8086:       /* Intel PRO/1000 F */
1636                         break;
1637                 case i82543gc:
1638                 case i82544ei:
1639                 case i82544eif:
1640                 case i82544gc:
1641                 case i82547ei:
1642                 case i82547gi:
1643                 case i82540em:
1644                 case i82540eplp:
1645                 case i82541ei:
1646                 case i82541gi:
1647                 case i82541gi2:
1648                 case i82541pi:
1649                 case i82545em:
1650                 case i82545gmc:
1651                 case i82546gb:
1652                 case i82546eb:
1653                         break;
1654                 }
1655
1656                 /* the 82547EI is on the CSA bus, whatever that is */
1657                 port = upamalloc(p->mem[0].bar & ~0x0F, p->mem[0].size, 0);
1658                 if(port == 0){
1659                         print("igbe: can't map %d @ 0x%8.8luX\n",
1660                                 p->mem[0].size, p->mem[0].bar);
1661                         continue;
1662                 }
1663
1664                 /*
1665                  * from etherga620.c:
1666                  * If PCI Write-and-Invalidate is enabled set the max write DMA
1667                  * value to the host cache-line size (32 on Pentium or later).
1668                  */
1669                 if(p->pcr & MemWrInv){
1670                         cls = pcicfgr8(p, PciCLS) * 4;
1671                         if(cls != CACHELINESZ)
1672                                 pcicfgw8(p, PciCLS, CACHELINESZ/4);
1673                 }
1674
1675                 cls = pcicfgr8(p, PciCLS);
1676                 switch(cls){
1677                         default:
1678                                 print("igbe: unexpected CLS - %d bytes\n",
1679                                         cls*sizeof(long));
1680                                 break;
1681                         case 0x00:
1682                         case 0xFF:
1683                                 /* alphapc 164lx returns 0 */
1684                                 print("igbe: unusable PciCLS: %d, using %d longs\n",
1685                                         cls, CACHELINESZ/sizeof(long));
1686                                 cls = CACHELINESZ/sizeof(long);
1687                                 pcicfgw8(p, PciCLS, cls);
1688                                 break;
1689                         case 0x08:
1690                         case 0x10:
1691                                 break;
1692                 }
1693
1694                 ctlr = malloc(sizeof(Ctlr));
1695                 ctlr->port = port;
1696                 ctlr->pcidev = p;
1697                 ctlr->id = (p->did<<16)|p->vid;
1698                 ctlr->cls = cls*4;
1699                 ctlr->nic = KADDR(ctlr->port);
1700                 if (Debug)
1701                         print("status0 %8.8uX\n", csr32r(ctlr, Status));
1702                 if(igbereset(ctlr)){
1703                         free(ctlr);
1704                         continue;
1705                 }
1706                 if (Debug)
1707                         print("status1 %8.8uX\n", csr32r(ctlr, Status));
1708                 pcisetbme(p);
1709
1710                 if(ctlrhead != nil)
1711                         ctlrtail->next = ctlr;
1712                 else
1713                         ctlrhead = ctlr;
1714                 ctlrtail = ctlr;
1715         }
1716 }
1717
1718 int
1719 igbepnp(Ether* edev)
1720 {
1721         int i;
1722         Ctlr *ctlr;
1723         uchar ea[Eaddrlen];
1724
1725         if(ctlrhead == nil)
1726                 igbepci();
1727
1728         /*
1729          * Any adapter matches if no edev->port is supplied,
1730          * otherwise the ports must match.
1731          */
1732         for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
1733                 if(ctlr->active)
1734                         continue;
1735                 if(edev->port == 0 || edev->port == ctlr->port){
1736                         ctlr->active = 1;
1737                         break;
1738                 }
1739         }
1740         if(ctlr == nil)
1741                 return -1;
1742
1743         edev->ctlr = ctlr;
1744         edev->port = ctlr->port;
1745         edev->irq = ctlr->pcidev->intl;
1746         edev->tbdf = ctlr->pcidev->tbdf;
1747 //      edev->mbps = 1000;
1748
1749         /*
1750          * Check if the adapter's station address is to be overridden.
1751          * If not, read it from the EEPROM and set in ether->ea prior to
1752          * loading the station address in the hardware.
1753          */
1754         memset(ea, 0, Eaddrlen);
1755         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1756                 for(i = 0; i < Eaddrlen/2; i++){
1757                         edev->ea[2*i] = ctlr->eeprom[i];
1758                         edev->ea[2*i+1] = ctlr->eeprom[i]>>8;
1759                 }
1760         }
1761         igbeinit(edev);
1762
1763         /*
1764          * Linkage to the generic ethernet driver.
1765          */
1766         edev->attach = igbeattach;
1767         edev->transmit = igbetransmit;
1768         edev->interrupt = igbeinterrupt;
1769         edev->detach = igbedetach;
1770
1771         return 0;
1772 }