2 cardbus and pcmcia (grmph) support.
12 extern int pciscan(int, Pcidev **);
14 int (*_pcmspecial)(char *, ISAConf *);
15 void (*_pcmspecialclose)(int);
18 pcmspecial(char *idstr, ISAConf *isa)
20 return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
24 pcmspecialclose(int a)
26 if (_pcmspecialclose != nil)
31 ioreserve(ulong, int size, int align, char *)
33 static ulong isaend = 0x400; /*0xfd00*/
37 isaend = ((isaend + align - 1) / align) * align;
43 #define MAP(x,o) (Rmap + (x)*0x8 + o)
50 TI_1251A_did = 0xAC1D,
54 Ricoh_475_did = 0x0475,
55 Ricoh_476_did = 0x0476,
56 Ricoh_478_did = 0x0478,
59 O2_OZ711M3_did = 0x7134,
61 Nslots = 4, /* Maximum number of CardBus slots to use */
69 TI1131xSC = 0x80, // system control
70 TI122X_SC_INTRTIE = 1 << 29,
72 TI1131xCC = 0x91, // card control
73 TI113X_CC_RIENB = 1 << 7,
74 TI113X_CC_ZVENABLE = 1 << 6,
75 TI113X_CC_PCI_IRQ_ENA = 1 << 5,
76 TI113X_CC_PCI_IREQ = 1 << 4,
77 TI113X_CC_PCI_CSC = 1 << 3,
78 TI113X_CC_SPKROUTEN = 1 << 1,
79 TI113X_CC_IFG = 1 << 0,
80 TI1131xDC = 0x92, // device control
83 typedef struct Variant Variant;
90 static Variant variant[] = {
91 { Ricoh_vid, Ricoh_475_did, "Ricoh 475 PCI/Cardbus bridge", },
92 { Ricoh_vid, Ricoh_476_did, "Ricoh 476 PCI/Cardbus bridge", },
93 { Ricoh_vid, Ricoh_478_did, "Ricoh 478 PCI/Cardbus bridge", },
94 { TI_vid, TI_1131_did, "TI PCI-1131 Cardbus Controller", },
95 { TI_vid, TI_1250_did, "TI PCI-1250 Cardbus Controller", },
96 { TI_vid, TI_1450_did, "TI PCI-1450 Cardbus Controller", },
97 { TI_vid, TI_1251A_did, "TI PCI-1251A Cardbus Controller", },
98 { TI_vid, TI_1420_did, "TI PCI-1420 Cardbus Controller", },
99 { O2_vid, O2_OZ711M3_did, "O2Micro OZ711M3 MemoryCardBus", },
102 /* Cardbus registers */
126 PciPCR_Master = 1 << 2,
146 * Intel 82365SL PCIC controller for the PCMCIA or
147 * Cirrus Logic PD6710/PD6720 which is mostly register compatible
154 Rid= 0x0, /* identification and revision */
155 Ris= 0x1, /* interface status */
156 Rpc= 0x2, /* power control */
157 Foutena= (1<<7), /* output enable */
158 Fautopower= (1<<5), /* automatic power switching */
159 Fcardena= (1<<4), /* PC card enable */
160 Rigc= 0x3, /* interrupt and general control */
161 Fiocard= (1<<5), /* I/O card (vs memory) */
162 Fnotreset= (1<<6), /* reset if not set */
163 FSMIena= (1<<4), /* enable change interrupt on SMI */
164 Rcsc= 0x4, /* card status change */
165 Rcscic= 0x5, /* card status change interrupt config */
166 Fchangeena= (1<<3), /* card changed */
167 Fbwarnena= (1<<1), /* card battery warning */
168 Fbdeadena= (1<<0), /* card battery dead */
169 Rwe= 0x6, /* address window enable */
170 Fmem16= (1<<5), /* use A23-A12 to decode address */
171 Rio= 0x7, /* I/O control */
172 Fwidth16= (1<<0), /* 16 bit data width */
173 Fiocs16= (1<<1), /* IOCS16 determines data width */
174 Fzerows= (1<<2), /* zero wait state */
175 Ftiming= (1<<3), /* timing register to use */
176 Riobtm0lo= 0x8, /* I/O address 0 start low byte */
177 Riobtm0hi= 0x9, /* I/O address 0 start high byte */
178 Riotop0lo= 0xa, /* I/O address 0 stop low byte */
179 Riotop0hi= 0xb, /* I/O address 0 stop high byte */
180 Riobtm1lo= 0xc, /* I/O address 1 start low byte */
181 Riobtm1hi= 0xd, /* I/O address 1 start high byte */
182 Riotop1lo= 0xe, /* I/O address 1 stop low byte */
183 Riotop1hi= 0xf, /* I/O address 1 stop high byte */
184 Rmap= 0x10, /* map 0 */
187 * CL-PD67xx extension registers
189 Rmisc1= 0x16, /* misc control 1 */
196 Rfifo= 0x17, /* fifo control */
197 Fflush= (1<<7), /* flush fifo */
198 Rmisc2= 0x1E, /* misc control 2 */
199 Flowpow= (1<<1), /* low power mode */
200 Rchipinfo= 0x1F, /* chip information */
201 Ratactl= 0x26, /* ATA control */
204 * offsets into the system memory address maps
206 Mbtmlo= 0x0, /* System mem addr mapping start low byte */
207 Mbtmhi= 0x1, /* System mem addr mapping start high byte */
208 F16bit= (1<<7), /* 16-bit wide data path */
209 Mtoplo= 0x2, /* System mem addr mapping stop low byte */
210 Mtophi= 0x3, /* System mem addr mapping stop high byte */
211 Ftimer1= (1<<6), /* timer set 1 */
212 Mofflo= 0x4, /* Card memory offset address low byte */
213 Moffhi= 0x5, /* Card memory offset address high byte */
214 Fregactive= (1<<6), /* attribute memory */
217 * configuration registers - they start at an offset in attribute
218 * memory found in the CIS.
221 Creset= (1<<7), /* reset device */
222 Clevel= (1<<6), /* level sensitive interrupt line */
226 * read and crack the card information structure enough to set
227 * important parameters like power
229 /* cis memory walking */
230 typedef struct Cisdat Cisdat;
238 typedef struct Pcminfo Pcminfo;
240 char verstr[512]; /* Version string */
241 PCMmap mmap[4]; /* maps, last is always for the kernel */
242 ulong conf_addr; /* Config address */
243 uchar conf_present; /* Config register present */
244 int nctab; /* In use configuration tables */
245 PCMconftab ctab[8]; /* Configuration tables */
246 PCMconftab *defctab; /* Default conftab */
248 int port; /* Actual port usage */
249 int irq; /* Actual IRQ usage */
252 typedef struct Cardbus Cardbus;
255 Variant *variant; /* Which CardBus chipset */
256 Pcidev *pci; /* The bridge itself */
257 ulong *regs; /* Cardbus registers */
258 int ltype; /* Legacy type */
259 int lindex; /* Legacy port index address */
260 int ldata; /* Legacy port data address */
261 int lbase; /* Base register for this socket */
263 int state; /* Current state of card */
264 int type; /* Type of card */
265 Pcminfo linfo; /* PCMCIA slot info */
267 int special; /* card is allocated to a driver */
269 int refs; /* Number of refs to slot */
270 Lock refslock; /* inc/dev ref lock */
275 Mgran= (1<<Mshift), /* granularity of maps */
276 Mmask= ~(Mgran-1), /* mask for address bits important to the chip */
279 static Cardbus cbslots[Nslots];
282 static ulong exponent[8] = {
283 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
286 static ulong vmant[16] = {
287 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90,
290 static ulong mantissa[16] = {
291 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80,
294 static void cbint(Ureg *, void *);
295 static int powerup(Cardbus *);
296 static void configure(Cardbus *);
297 static void managecard(Cardbus *);
298 static void cardmanager(void *);
299 static void eject(Cardbus *);
300 static void interrupt(Ureg *, void *);
301 static void powerdown(Cardbus *cb);
302 static void unconfigure(Cardbus *cb);
304 static void i82365probe(Cardbus *cb, int lindex, int ldata);
305 static void i82365configure(Cardbus *cb);
306 static PCMmap *isamap(Cardbus *cb, ulong offset, int len, int attr);
307 static void isaunmap(PCMmap* m);
308 static uchar rdreg(Cardbus *cb, int index);
309 static void wrreg(Cardbus *cb, int index, uchar val);
310 static int readc(Cisdat *cis, uchar *x);
311 static void tvers1(Cardbus *cb, Cisdat *cis, int );
312 static void tcfig(Cardbus *cb, Cisdat *cis, int );
313 static void tentry(Cardbus *cb, Cisdat *cis, int );
314 static int vcode(int volt);
315 static int pccard_pcmspecial(char *idstr, ISAConf *isa);
316 static void pccard_pcmspecialclose(int slotno);
325 static char *messages[] = {
326 [CardDetected] "CardDetected",
327 [CardPowered] "CardPowered",
328 [CardEjected] "CardEjected",
329 [CardConfigured] "CardConfigured",
339 static char *states[] = {
340 [SlotEmpty] "SlotEmpty",
341 [SlotFull] "SlotFull",
342 [SlotPowered] "SlotPowered",
343 [SlotConfigured] "SlotConfigured",
347 engine(Cardbus *cb, int message)
349 // print("engine(%d): %s(%s)\n",
350 // (int)(cb - cbslots), states[cb->state], messages[message]);
356 cb->state = SlotFull;
362 //print("#Y%d: Invalid message %s in SlotEmpty state\n",
363 // (int)(cb - cbslots), messages[message]);
372 cb->state = SlotPowered;
376 cb->state = SlotEmpty;
380 //print("#Y%d: Invalid message %s in SlotFull state\n",
381 // (int)(cb - cbslots), messages[message]);
390 cb->state = SlotConfigured;
393 cb->state = SlotEmpty;
398 print("#Y%d: Invalid message %s in SlotPowered state\n",
399 (int)(cb - cbslots), messages[message]);
408 cb->state = SlotEmpty;
413 //print("#Y%d: Invalid message %s in SlotConfigured state\n",
414 // (int)(cb - cbslots), messages[message]);
424 static int initialized;
433 if((p=getconf("pccard0")) && strncmp(p, "disabled", 8)==0)
440 /* Allocate legacy space */
441 if (ioalloc(LegacyAddr, 2, 0, "i82365.0") < 0)
442 print("#Y: WARNING: Cannot allocate legacy ports\n");
444 /* Find all CardBus controllers */
446 while ((pci = pcimatch(pci, 0, 0)) != nil) {
452 if(pci->ccrb != 6 || pci->ccru != 7)
454 for (i = 0; i != nelem(variant); i++)
455 if (pci->vid == variant[i].vid && pci->did == variant[i].did)
457 if (i == nelem(variant))
460 /* initialize this slot */
465 cb->variant = &variant[i];
467 // Set up PCI bus numbers if needed.
468 if (pcicfgr8(pci, PciSBN) == 0) {
469 static int busbase = 0x20;
471 pcicfgw8(pci, PciSBN, busbase);
472 pcicfgw8(pci, PciUBN, busbase + 2);
476 // Patch up intl if needed.
477 if ((pin = pcicfgr8(pci, PciINTP)) != 0 &&
478 (pci->intl == 0xff || pci->intl == 0)) {
479 pci->intl = pciipin(nil, pin);
480 pcicfgw8(pci, PciINTL, pci->intl);
482 if (pci->intl == 0xff || pci->intl == 0)
483 print("#Y%d: No interrupt?\n", (int)(cb - cbslots));
486 // Don't you love standards!
487 if (pci->vid == TI_vid) {
488 if (pci->did <= TI_1131_did) {
491 cc = pcicfgr8(pci, TI1131xCC);
492 cc &= ~(TI113X_CC_PCI_IRQ_ENA |
496 cc |= TI113X_CC_PCI_IRQ_ENA |
499 pcicfgw8(pci, TI1131xCC, cc);
501 // PCI interrupts only
502 pcicfgw8(pci, TI1131xDC,
503 pcicfgr8(pci, TI1131xDC) & ~6);
505 // CSC ints to PCI bus.
506 wrreg(cb, Rigc, rdreg(cb, Rigc) | 0x10);
508 else if (pci->did == TI_1250_did) {
509 print("No support yet for the TI_1250_did, prod pb\n");
511 else if (pci->did == TI_1420_did) {
512 // Disable Vcc protection
513 pcicfgw32(cb->pci, 0x80,
514 pcicfgr32(cb->pci, 0x80) | (1 << 21));
517 pcicfgw16(cb->pci, PciPMC, pcicfgr16(cb->pci, PciPMC) & ~3);
520 if ((baddr = pcicfgr32(cb->pci, PciBAR0)) == 0) {
521 int size = (pci->did == Ricoh_478_did)? 0x10000: 0x1000;
523 baddr = upamalloc(baddr, size, size);
524 pcicfgw32(cb->pci, PciBAR0, baddr);
525 cb->regs = (ulong *)KADDR(baddr);
528 cb->regs = (ulong *)KADDR(upamalloc(baddr, 4096, 0));
529 cb->state = SlotEmpty;
531 /* Don't really know what to do with this... */
532 i82365probe(cb, LegacyAddr, LegacyAddr + 1);
534 print("#Y%ld: %s, %.8ulX intl %d\n", cb - cbslots,
535 variant[i].name, baddr, pci->intl);
541 _pcmspecial = pccard_pcmspecial;
542 _pcmspecialclose = pccard_pcmspecialclose;
544 for (i = 0; i != nslots; i++) {
545 Cardbus *cb = &cbslots[i];
547 if ((cb->regs[SocketState] & SE_CCD) == 0)
548 engine(cb, CardDetected);
551 delay(500); /* Allow time for power up */
553 for (i = 0; i != nslots; i++) {
554 Cardbus *cb = &cbslots[i];
556 if (cb->regs[SocketState] & SE_POWER)
557 engine(cb, CardPowered);
559 /* Ack and enable interrupts on all events */
560 //cb->regs[SocketEvent] = cb->regs[SocketEvent];
561 //cb->regs[SocketMask] |= 0xF;
562 //wrreg(cb, Rcscic, 0xC);
572 state = cb->regs[SocketState];
573 if (state & SS_PC16) {
575 // print("#Y%ld: Probed a PC16 card, powering up card\n", cb - cbslots);
577 memset(&cb->linfo, 0, sizeof(Pcminfo));
579 /* power up and unreset, wait's are empirical (???) */
580 wrreg(cb, Rpc, Fautopower|Foutena|Fcardena);
584 wrreg(cb, Rigc, Fnotreset);
593 if (state & SS_NOTCARD) {
594 print("#Y%ld: No card inserted\n", cb - cbslots);
598 if (state & SS_BADVCC) {
599 print("#Y%ld: Bad VCC request to card, powering down card!\n",
601 cb->regs[SocketControl] = 0;
605 if ((state & SS_3V) == 0 && (state & SS_5V) == 0) {
606 print("#Y%ld: Unsupported voltage, powering down card!\n",
608 cb->regs[SocketControl] = 0;
612 //print("#Y%ld: card %spowered at %d volt\n", cb - cbslots,
613 // (state & SS_POWER)? "": "not ",
614 // (state & SS_3V)? 3: (state & SS_5V)? 5: -1);
617 * and make sure the secondary bus is not in reset.
619 cb->regs[SocketControl] = (state & SS_5V)? SC_5V: SC_3V;
621 bcr = pcicfgr16(cb->pci, PciBCR);
623 pcicfgw16(cb->pci, PciBCR, bcr);
632 powerdown(Cardbus *cb)
636 if (cb->type == PC16) {
638 wrreg(cb, Rpc, 0); /* turn off card power */
639 wrreg(cb, Rwe, 0); /* no windows */
645 bcr = pcicfgr16(cb->pci, PciBCR);
647 pcicfgw16(cb->pci, PciBCR, bcr);
648 cb->regs[SocketControl] = 0;
653 configure(Cardbus *cb)
657 int i, ioindex, memindex, r;
659 //print("configuring slot %d (%s)\n", (int)(cb - cbslots), states[cb->state]);
660 if (cb->state == SlotConfigured)
662 engine(cb, CardConfigured);
664 delay(50); /* Emperically established */
666 if (cb->type == PC16) {
671 /* Scan the CardBus for new PCI devices */
672 pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge);
673 pci = cb->pci->bridge;
675 r = pcicfgr16(pci, PciPCR);
676 r &= ~(PciPCR_IO|PciPCR_MEM);
677 pcicfgw16(pci, PciPCR, r);
680 * Treat the found device as an ordinary PCI card.
681 * It seems that the CIS is not always present in
683 * XXX, need to support multifunction cards
685 memindex = ioindex = 0;
686 for (i = 0; i != Nbars; i++) {
688 if (pci->mem[i].size == 0)
690 if (pci->mem[i].bar & 1) {
692 // Allocate I/O space
694 print("#Y%ld: WARNING: Can only configure 2 I/O slots\n", cb - cbslots);
697 bar = ioreserve(-1, pci->mem[i].size, 0, "cardbus");
698 pci->mem[i].bar = bar | 1;
699 pcicfgw32(pci, PciBAR0 + i * sizeof(ulong),
701 pcicfgw16(cb->pci, PciCBIBR0 + ioindex * 8, bar);
702 pcicfgw16(cb->pci, PciCBILR0 + ioindex * 8,
703 bar + pci->mem[i].size - 1);
704 //print("ioindex[%d] %.8uX (%d)\n",
705 // ioindex, bar, pci->mem[i].size);
710 // Allocating memory space
712 print("#Y%ld: WARNING: Can only configure 2 memory slots\n", cb - cbslots);
716 bar = upamalloc(0, pci->mem[i].size, BY2PG);
717 pci->mem[i].bar = bar | (pci->mem[i].bar & 0x80);
718 pcicfgw32(pci, PciBAR0 + i * sizeof(ulong), pci->mem[i].bar);
719 pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, bar);
720 pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8,
721 bar + pci->mem[i].size - 1);
723 if (pci->mem[i].bar & 0x80) {
724 /* Enable prefetch */
725 r = pcicfgr16(cb->pci, PciBCR);
726 r |= 1 << (8 + memindex);
727 pcicfgw16(cb->pci, PciBCR, r);
730 //print("memindex[%d] %.8uX (%d)\n",
731 // memindex, bar, pci->mem[i].size);
735 if ((size = pcibarsize(pci, PciEBAR0)) > 0) {
738 print("#Y%ld: WARNING: Too many memory spaces, not mapping ROM space\n",
741 pci->rom.bar = upamalloc(0, size, BY2PG);
742 pci->rom.size = size;
744 pcicfgw32(pci, PciEBAR0, pci->rom.bar);
745 pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8,
747 pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8,
748 pci->rom.bar + pci->rom.size - 1);
752 /* Set the basic PCI registers for the device */
753 pci->pcr = pcicfgr16(pci, PciPCR);
754 pci->pcr |= PciPCR_IO|PciPCR_MEM|PciPCR_Master;
757 pcicfgw16(pci, PciPCR, pci->pcr);
758 pcicfgw8(pci, PciCLS, pci->cls);
759 pcicfgw8(pci, PciLTR, pci->ltr);
761 if (pcicfgr8(pci, PciINTP)) {
762 pci->intl = pcicfgr8(cb->pci, PciINTL);
763 pcicfgw8(pci, PciINTL, pci->intl);
765 /* Route interrupts to INTA#/B# */
766 pcicfgw16(cb->pci, PciBCR,
767 pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));
775 unconfigure(Cardbus *cb)
778 int i, ioindex, memindex, r;
780 if (cb->type == PC16) {
781 print("#Y%d: Don't know how to unconfigure a PC16 card\n",
782 (int)(cb - cbslots));
784 memset(&cb->linfo, 0, sizeof(Pcminfo));
788 pci = cb->pci->bridge;
790 return; /* Not configured */
791 cb->pci->bridge = nil;
793 memindex = ioindex = 0;
797 for (i = 0; i != Nbars; i++) {
798 if (pci->mem[i].size == 0)
800 if (pci->mem[i].bar & 1) {
801 iofree(pci->mem[i].bar & ~1);
802 pcicfgw16(cb->pci, PciCBIBR0 + ioindex * 8,
804 pcicfgw16(cb->pci, PciCBILR0 + ioindex * 8, 0);
809 upafree(pci->mem[i].bar & ~0xF, pci->mem[i].size);
810 pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1);
811 pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0);
812 r = pcicfgr16(cb->pci, PciBCR);
813 r &= ~(1 << (8 + memindex));
814 pcicfgw16(cb->pci, PciBCR, r);
818 if (pci->rom.bar && memindex < 2) {
819 upafree(pci->rom.bar & ~0xF, pci->rom.size);
820 pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1);
821 pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0);
832 i82365configure(Cardbus *cb)
840 * Read all tuples in attribute space.
842 m = isamap(cb, 0, 0, 1);
846 cis.cisbase = KADDR(m->isa);
851 /* loop through all the tuples */
854 if(readc(&cis, &type) != 1)
858 if(readc(&cis, &link) != 1)
865 tvers1(cb, &cis, type);
868 tcfig(cb, &cis, type);
871 tentry(cb, &cis, type);
877 cis.cispos = this + (2+link);
883 * look for a card whose version contains 'idstr'
886 pccard_pcmspecial(char *idstr, ISAConf *isa)
895 for (i = 0; i != nslots; i++) {
899 if (cb->state == SlotConfigured &&
902 strstr(cb->linfo.verstr, idstr))
908 // print("#Y: %s not found\n", idstr);
915 * configure the PCMslot for IO. We assume very heavily that we can read
916 * configuration info from the CIS. If not, we won't set up correctly.
922 et = &pi->ctab[pi->nctab];
924 for(i = 0; i < isa->nopt; i++){
928 if(strncmp(isa->opt[i], "index=", 6))
930 index = strtol(&isa->opt[i][6], &cp, 0);
931 if(cp == &isa->opt[i][6] || index >= pi->nctab) {
933 print("#Y%d: Cannot find index %d in conf table\n",
934 (int)(cb - cbslots), index);
937 ct = &pi->ctab[index];
943 /* assume default is right */
949 /* try for best match */
951 || ct->io[0].start != isa->port || ((1<<irq) & ct->irqs) == 0){
952 for(t = pi->ctab; t < et; t++)
954 && t->io[0].start == isa->port
955 && ((1<<irq) & t->irqs)){
960 if(ct->nio == 0 || ((1<<irq) & ct->irqs) == 0){
961 for(t = pi->ctab; t < et; t++)
962 if(t->nio && ((1<<irq) & t->irqs)){
968 for(t = pi->ctab; t < et; t++)
976 if(ct == et || ct->nio == 0) {
978 print("#Y%d: No configuration?\n", (int)(cb - cbslots));
981 if(isa->port == 0 && ct->io[0].start == 0) {
983 print("#Y%d: No part or start address\n", (int)(cb - cbslots));
987 cb->special = 1; /* taken */
989 /* route interrupts */
991 wrreg(cb, Rigc, irq | Fnotreset | Fiocard);
993 /* set power and enable device */
995 wrreg(cb, Rpc, x|Fautopower|Foutena|Fcardena);
997 /* 16-bit data path */
999 x = Ftiming|Fiocs16|Fwidth16;
1002 if(ct->nio == 2 && ct->io[1].start)
1007 * enable io port map 0
1008 * the 'top' register value includes the last valid address
1011 isa->port = ct->io[0].start;
1012 we = rdreg(cb, Rwe);
1013 wrreg(cb, Riobtm0lo, isa->port);
1014 wrreg(cb, Riobtm0hi, isa->port>>8);
1015 i = isa->port+ct->io[0].len-1;
1016 wrreg(cb, Riotop0lo, i);
1017 wrreg(cb, Riotop0hi, i>>8);
1019 if(ct->nio == 2 && ct->io[1].start){
1020 wrreg(cb, Riobtm1lo, ct->io[1].start);
1021 wrreg(cb, Riobtm1hi, ct->io[1].start>>8);
1022 i = ct->io[1].start+ct->io[1].len-1;
1023 wrreg(cb, Riotop1lo, i);
1024 wrreg(cb, Riotop1hi, i>>8);
1029 /* only touch Rconfig if it is present */
1030 if(pi->conf_present & (1<<Rconfig)){
1034 m = isamap(cb, pi->conf_addr + Rconfig, 1, 1);
1035 p = KADDR(m->isa + pi->conf_addr + Rconfig - m->ca);
1037 /* set configuration and interrupt type */
1039 if((ct->irqtype & 0x20)/* && ((ct->irqtype & 0x40)==0 || isa->irq>7)*/)
1047 pi->port = isa->port;
1051 print("#Y%d: %s irq %ld, port %lX\n", (int)(cb - cbslots), pi->verstr, isa->irq, isa->port);
1052 return (int)(cb - cbslots);
1056 pccard_pcmspecialclose(int slotno)
1058 Cardbus *cb = &cbslots[slotno];
1060 wrreg(cb, Rwe, 0); /* no windows */
1065 xcistuple(int slotno, int tuple, int subtuple, void *v, int nv, int attr)
1071 uchar type, link, n, c;
1073 Cardbus *cb = &cbslots[slotno];
1075 m = isamap(cb, 0, 0, attr);
1079 cis.cisbase = KADDR(m->isa);
1081 cis.cisskip = attr ? 2 : 1;
1082 cis.cislen = m->len;
1084 /* loop through all the tuples */
1085 for(i = 0; i < 1000; i++){
1087 if(readc(&cis, &type) != 1)
1091 if(readc(&cis, &link) != 1)
1097 if (link > 1 && subtuple != -1) {
1098 if (readc(&cis, &c) != 1)
1105 if(type == tuple && subtype == subtuple) {
1107 for(l=0; l<nv && l<n; l++)
1108 if(readc(&cis, p++) != 1)
1113 cis.cispos = this + (2+link);
1120 isamap(Cardbus *cb, ulong offset, int len, int attr)
1130 /* convert offset to granularity */
1133 e = ROUND(offset+len, Mgran);
1137 /* look for a map that covers the right area */
1138 we = rdreg(cb, Rwe);
1141 for(m = pi->mmap; m < &pi->mmap[nelem(pi->mmap)]; m++){
1144 if(offset >= m->ca && e <= m->cea){
1150 if(nm == 0 && m->ref == 0)
1157 /* if isa space isn't big enough, free it and get more */
1160 umbfree(m->isa, m->len);
1163 m->isa = PADDR(umbmalloc(0, len, Mgran));
1165 print("isamap: out of isa space\n");
1171 /* set up new map */
1173 m->cea = m->ca + m->len;
1177 wrreg(cb, Rwe, we & ~bit); /* disable map before changing it */
1178 wrreg(cb, MAP(i, Mbtmlo), m->isa>>Mshift);
1179 wrreg(cb, MAP(i, Mbtmhi), (m->isa>>(Mshift+8)) | F16bit);
1180 wrreg(cb, MAP(i, Mtoplo), (m->isa+m->len-1)>>Mshift);
1181 wrreg(cb, MAP(i, Mtophi), ((m->isa+m->len-1)>>(Mshift+8)));
1183 offset &= (1<<25)-1;
1185 wrreg(cb, MAP(i, Mofflo), offset);
1186 wrreg(cb, MAP(i, Moffhi), (offset>>8) | (attr ? Fregactive : 0));
1187 wrreg(cb, Rwe, we | bit); /* enable map */
1200 * reading and writing card registers
1203 rdreg(Cardbus *cb, int index)
1205 outb(cb->lindex, cb->lbase + index);
1206 return inb(cb->ldata);
1210 wrreg(Cardbus *cb, int index, uchar val)
1212 outb(cb->lindex, cb->lbase + index);
1213 outb(cb->ldata, val);
1217 readc(Cisdat *cis, uchar *x)
1219 if(cis->cispos >= cis->cislen)
1221 *x = cis->cisbase[cis->cisskip*cis->cispos];
1227 getlong(Cisdat *cis, int size)
1234 for(i = 0; i < size; i++){
1235 if(readc(cis, &c) != 1)
1243 tcfig(Cardbus *cb, Cisdat *cis, int )
1245 uchar size, rasize, rmsize;
1249 if(readc(cis, &size) != 1)
1251 rasize = (size&0x3) + 1;
1252 rmsize = ((size>>2)&0xf) + 1;
1253 if(readc(cis, &last) != 1)
1257 pi->conf_addr = getlong(cis, rasize);
1258 pi->conf_present = getlong(cis, rmsize);
1262 tvers1(Cardbus *cb, Cisdat *cis, int )
1264 uchar c, major, minor, last;
1269 if(readc(cis, &major) != 1)
1271 if(readc(cis, &minor) != 1)
1274 for(i = 0; i < sizeof(pi->verstr) - 1; i++){
1275 if(readc(cis, &c) != 1)
1283 if(c == ';' && last == ';')
1292 microvolt(Cisdat *cis)
1298 if(readc(cis, &c) != 1)
1300 exp = exponent[c&0x7];
1301 microvolts = vmant[(c>>3)&0xf]*exp;
1303 if(readc(cis, &c) != 1)
1307 break; /* high impedence when sleeping */
1310 microvolts = 0; /* no connection */
1314 microvolts += exp*(c&0x7f);
1321 nanoamps(Cisdat *cis)
1326 if(readc(cis, &c) != 1)
1328 nanoamps = exponent[c&0x7]*vmant[(c>>3)&0xf];
1330 if(readc(cis, &c) != 1)
1332 if(c == 0x7d || c == 0x7e || c == 0x7f)
1339 * only nominal voltage (feature 1) is important for config,
1340 * other features must read card to stay in sync.
1349 if(readc(cis, &feature) != 1)
1352 mv = microvolt(cis);
1369 ttiming(Cisdat *cis, int scale)
1374 if(readc(cis, &unscaled) != 1)
1376 nanosecs = (mantissa[(unscaled>>3)&0xf]*exponent[unscaled&7])/10;
1377 nanosecs = nanosecs * exponent[scale];
1382 timing(Cisdat *cis, PCMconftab *ct)
1386 if(readc(cis, &c) != 1)
1390 ct->maxwait = ttiming(cis, i); /* max wait */
1393 ct->readywait = ttiming(cis, i); /* max ready/busy wait */
1396 ct->otherwait = ttiming(cis, i); /* reserved wait */
1400 iospaces(Cisdat *cis, PCMconftab *ct)
1406 if(readc(cis, &c) != 1)
1409 ct->bit16 = ((c>>5)&3) >= 2;
1411 ct->io[0].start = 0;
1412 ct->io[0].len = 1<<(c&0x1f);
1417 if(readc(cis, &c) != 1)
1421 * For each of the range descriptions read the
1422 * start address and the length (value is length-1).
1425 for(i = 0; i < nio; i++){
1426 ct->io[i].start = getlong(cis, (c>>4)&0x3);
1427 ct->io[i].len = getlong(cis, (c>>6)&0x3)+1;
1433 irq(Cisdat *cis, PCMconftab *ct)
1437 if(readc(cis, &c) != 1)
1439 ct->irqtype = c & 0xe0;
1441 ct->irqs = getlong(cis, 2);
1443 ct->irqs = 1<<(c&0xf);
1444 ct->irqs &= 0xDEB8; /* levels available to card */
1448 memspace(Cisdat *cis, int asize, int lsize, int host)
1450 ulong haddress, address, len;
1452 len = getlong(cis, lsize)*256;
1453 address = getlong(cis, asize)*256;
1456 haddress = getlong(cis, asize)*256;
1462 tentry(Cardbus *cb, Cisdat *cis, int )
1464 uchar c, i, feature;
1469 if(pi->nctab >= nelem(pi->ctab))
1471 if(readc(cis, &c) != 1)
1473 ct = &pi->ctab[pi->nctab++];
1475 /* copy from last default config */
1479 ct->index = c & 0x3f;
1481 /* is this the new default? */
1485 /* memory wait specified? */
1487 if(readc(cis, &i) != 1)
1493 if(readc(cis, &feature) != 1)
1495 switch(feature&0x3){
1497 ct->vpp1 = ct->vpp2 = power(cis);
1501 ct->vpp1 = ct->vpp2 = power(cis);
1505 ct->vpp1 = power(cis);
1506 ct->vpp2 = power(cis);
1517 switch((feature>>5)&0x3){
1519 memspace(cis, 0, 2, 0);
1522 memspace(cis, 2, 2, 0);
1525 if(readc(cis, &c) != 1)
1527 for(i = 0; i <= (c&0x7); i++)
1528 memspace(cis, (c>>5)&0x3, (c>>3)&0x3, c&0x80);
1534 i82365probe(Cardbus *cb, int lindex, int ldata)
1537 int dev = 0; /* According to the Ricoh spec 00->3F _and_ 80->BF seem
1538 to be the same socket A (ditto for B). */
1540 outb(lindex, Rid + (dev<<7));
1542 if((id & 0xf0) != 0x80)
1543 return; /* not a memory & I/O card */
1544 if((id & 0x0f) == 0x00)
1545 return; /* no revision number, not possible */
1547 cb->lindex = lindex;
1549 cb->ltype = Ti82365;
1550 cb->lbase = (int)(cb - cbslots) * 0x40;
1556 /* could be a cirrus */
1557 outb(cb->lindex, Rchipinfo + (dev<<7));
1560 if((c & 0xc0) != 0xc0)
1563 if((c & 0xc0) != 0x00)
1566 cb->ltype = Tpd6720;
1568 cb->ltype = Tpd6710;
1573 /* if it's not a Cirrus, it could be a Vadem... */
1574 if(cb->ltype == Ti82365){
1575 /* unlock the Vadem extended regs */
1576 outb(cb->lindex, 0x0E + (dev<<7));
1577 outb(cb->lindex, 0x37 + (dev<<7));
1579 /* make the id register show the Vadem id */
1580 outb(cb->lindex, 0x3A + (dev<<7));
1582 outb(cb->ldata, c|0xC0);
1583 outb(cb->lindex, Rid + (dev<<7));
1588 /* go back to Intel compatible id */
1589 outb(cb->lindex, 0x3A + (dev<<7));
1591 outb(cb->ldata, c & ~0xC0);