2 * Definitions for IO devices. Used only in C.
7 /* hardware counter frequency */
12 * IRQ's defined by SA1100
50 * GPIO lines (signal names from compaq document). _i indicates input
55 GPIO_PWR_ON_i= 1<<0, /* power button */
56 GPIO_UP_IRQ_i= 1<<1, /* microcontroller interrupts */
57 GPIO_LDD8_o= 1<<2, /* LCD data 8-15 */
65 GPIO_CARD_IND1_i= 1<<10, /* card inserted in PCMCIA socket 1 */
66 GPIO_CARD_IRQ1_i= 1<<11, /* PCMCIA socket 1 interrupt */
67 GPIO_CLK_SET0_o= 1<<12, /* clock selects for audio codec */
68 GPIO_CLK_SET1_o= 1<<13,
69 GPIO_L3_SDA_io= 1<<14, /* UDA1341 interface */
70 GPIO_L3_MODE_o= 1<<15,
71 GPIO_L3_SCLK_o= 1<<16,
72 GPIO_CARD_IND0_i= 1<<17, /* card inserted in PCMCIA socket 0 */
73 GPIO_KEY_ACT_i= 1<<18, /* hot key from cradle */
74 GPIO_SYS_CLK_i= 1<<19, /* clock from codec */
75 GPIO_BAT_FAULT_i= 1<<20, /* battery fault */
76 GPIO_CARD_IRQ0_i= 1<<21, /* PCMCIA socket 0 interrupt */
77 GPIO_LOCK_i= 1<<22, /* expansion pack lock/unlock */
78 GPIO_COM_DCD_i= 1<<23, /* DCD from UART3 */
79 GPIO_OPT_IRQ_i= 1<<24, /* expansion pack IRQ */
80 GPIO_COM_CTS_i= 1<<25, /* CTS from UART3 */
81 GPIO_COM_RTS_o= 1<<26, /* RTS to UART3 */
82 GPIO_OPT_IND_i= 1<<27, /* expansion pack inserted */
84 /* Peripheral Unit GPIO pin assignments: alternate functions */
85 GPIO_SSP_TXD_o= 1<<10, /* SSP Transmit Data */
86 GPIO_SSP_RXD_i= 1<<11, /* SSP Receive Data */
87 GPIO_SSP_SCLK_o= 1<<12, /* SSP Sample CLocK */
88 GPIO_SSP_SFRM_o= 1<<13, /* SSP Sample FRaMe */
90 GPIO_UART_TXD_o= 1<<14, /* UART Transmit Data */
91 GPIO_UART_RXD_i= 1<<15, /* UART Receive Data */
92 GPIO_SDLC_SCLK_io= 1<<16, /* SDLC Sample CLocK (I/O) */
93 GPIO_SDLC_AAF_o= 1<<17, /* SDLC Abort After Frame */
94 GPIO_UART_SCLK1_i= 1<<18, /* UART Sample CLocK 1 */
96 GPIO_SSP_CLK_i= 1<<19, /* SSP external CLocK */
98 GPIO_UART_SCLK3_i= 1<<20, /* UART Sample CLocK 3 */
100 GPIO_MCP_CLK_i= 1<<21, /* MCP CLocK */
101 /* test controller: */
102 GPIO_TIC_ACK_o= 1<<21, /* TIC ACKnowledge */
103 GPIO_MBGNT_o= 1<<21, /* Memory Bus GraNT */
104 GPIO_TREQA_i= 1<<22, /* TIC REQuest A */
105 GPIO_MBREQ_i= 1<<22, /* Memory Bus REQuest */
106 GPIO_TREQB_i= 1<<23, /* TIC REQuest B */
107 GPIO_1Hz_o= 1<<25, /* 1 Hz clock */
108 GPIO_RCLK_o= 1<<26, /* internal (R) CLocK (O, fcpu/2) */
109 GPIO_32_768kHz_o= 1<<27, /* 32.768 kHz clock (O, RTC) */
113 * types of interrupts
123 /* hardware registers */
124 typedef struct Uartregs Uartregs;
135 /* general purpose I/O lines control registers */
136 typedef struct GPIOregs GPIOregs;
139 ulong level; /* 1 == high */
140 ulong direction; /* 1 == output */
141 ulong set; /* a 1 sets the bit, 0 leaves it alone */
142 ulong clear; /* a 1 clears the bit, 0 leaves it alone */
143 ulong rising; /* rising edge detect enable */
144 ulong falling; /* falling edge detect enable */
145 ulong edgestatus; /* writing a 1 bit clears */
146 ulong altfunc; /* turn on alternate function for any set bits */
149 extern GPIOregs *gpioregs;
151 /* extra general purpose I/O bits, output only */
154 EGPIO_prog_flash= 1<<0,
155 EGPIO_pcmcia_reset= 1<<1,
156 EGPIO_exppack_reset= 1<<2,
157 EGPIO_codec_reset= 1<<3,
158 EGPIO_exp_nvram_power= 1<<4,
159 EGPIO_exp_full_power= 1<<5,
161 EGPIO_rs232_power= 1<<7,
162 EGPIO_lcd_ic_power= 1<<8,
163 EGPIO_ir_power= 1<<9,
164 EGPIO_audio_power= 1<<10,
165 EGPIO_audio_ic_power= 1<<11,
166 EGPIO_audio_mute= 1<<12,
167 EGPIO_fir= 1<<13, /* not set is sir */
171 extern ulong *egpioreg;
173 /* Peripheral pin controller registers */
174 typedef struct PPCregs PPCregs;
182 extern PPCregs *ppcregs;
184 /* Synchronous Serial Port controller registers */
185 typedef struct SSPregs SSPregs;
194 extern SSPregs *sspregs;
196 /* Multimedia Communications Port controller registers */
197 typedef struct MCPregs MCPregs;
209 extern MCPregs *mcpregs;
212 * memory configuration
216 /* bit shifts for pcmcia access time counters */
221 MECR_io1= MECR_io0+16,
222 MECR_attr1= MECR_attr0+16,
223 MECR_mem1= MECR_mem0+16,
224 MECR_fast1= MECR_fast0+16,
227 typedef struct MemConfRegs MemConfRegs;
230 ulong mdcnfg; /* dram */
231 ulong mdcas00; /* dram banks 0/1 */
234 ulong msc0; /* static */
236 ulong mecr; /* pcmcia */
237 ulong mdrefr; /* dram refresh */
238 ulong mdcas20; /* dram banks 2/3 */
241 ulong msc2; /* static */
242 ulong smcnfg; /* SMROM config */
244 extern MemConfRegs *memconfregs;
249 typedef struct PowerRegs PowerRegs;
252 ulong pmcr; /* Power manager control register */
253 ulong pssr; /* Power manager sleep status register */
254 ulong pspr; /* Power manager scratch pad register */
255 ulong pwer; /* Power manager wakeup enable register */
256 ulong pcfr; /* Power manager general configuration register */
257 ulong ppcr; /* Power manager PPL configuration register */
258 ulong pgsr; /* Power manager GPIO sleep state register */
259 ulong posr; /* Power manager oscillator status register */
261 extern PowerRegs *powerregs;