2 #include "../port/lib.h"
12 ARM_PLL_CTRL = 0x100/4,
13 ARM_CLK_CTRL = 0x120/4,
31 while(µs() - now < n);
49 hi = mpcore[GTIMERVALH];
50 lo = mpcore[GTIMERVALL];
51 }while(hi != mpcore[GTIMERVALH]);
52 return lo | (uvlong)hi << 32;
58 return fastticks2us(fastticks(nil));
66 w = v - fastticks(nil);
71 mpcore[LTIMERCTL] &= ~1;
72 mpcore[LTIMERVAL] = w;
73 mpcore[LTIMERCTL] |= 1;
77 timerirq(Ureg *u, void *)
79 if((mpcore[LTIMERISR] & 1) != 0){
80 mpcore[LTIMERISR] |= 1;
88 m->cpumhz = PS_CLK * (slcr[ARM_PLL_CTRL] >> 12 & 0x7f) / (slcr[ARM_CLK_CTRL] >> 8 & 0x3f);
89 m->cpuhz = m->cpumhz * 1000000;
90 timerhz = m->cpuhz / 2;
91 mpcore[GTIMERCTL] = TIMERDIV - 1 << 8 | 3;
92 mpcore[LTIMERCTL] = LTIMERDIV - 1 << 8 | 4;
93 intrenable(TIMERIRQ, timerirq, nil, EDGE, "clock");
95 /* enable and reset cycle counter register */
96 m->cyclefreq = m->cpuhz;
103 * synchronize all cpu's cycle counter registers
114 while(r1.ref != conf.nmach)
117 m->cycleshi = MACHP(0)->cycleshi;
119 while(r2.ref != conf.nmach)