2 #include "../port/lib.h"
12 ARM_PLL_CTRL = 0x100/4,
13 ARM_CLK_CTRL = 0x120/4,
43 hi = mpcore[GTIMERVALH];
44 lo = mpcore[GTIMERVALL];
45 }while(hi != mpcore[GTIMERVALH]);
46 return lo | (uvlong)hi << 32;
52 return fastticks2us(fastticks(nil));
60 w = v - fastticks(nil);
65 mpcore[LTIMERCTL] &= ~1;
66 mpcore[LTIMERVAL] = w;
67 mpcore[LTIMERCTL] |= 1;
71 timerirq(Ureg *u, void *)
73 if((mpcore[LTIMERISR] & 1) != 0){
74 mpcore[LTIMERISR] |= 1;
82 m->cpumhz = PS_CLK * (slcr[ARM_PLL_CTRL] >> 12 & 0x7f) / (slcr[ARM_CLK_CTRL] >> 8 & 0x3f);
83 m->cpuhz = m->cpumhz * 1000000;
84 timerhz = m->cpuhz / 2;
85 mpcore[GTIMERCTL] = TIMERDIV - 1 << 8 | 3;
86 mpcore[LTIMERCTL] = LTIMERDIV - 1 << 8 | 4;
87 intrenable(TIMERIRQ, timerirq, nil, EDGE, "clock");
89 /* enable and reset cycle counter register */
90 m->cyclefreq = m->cpuhz;
97 * synchronize all cpu's cycle counter registers
108 while(r1.ref != conf.nmach)
111 m->cycleshi = MACHP(0)->cycleshi;
113 while(r2.ref != conf.nmach)