3 #include "../port/lib.h"
9 #include "../port/error.h"
12 int normalprint, delaylink;
14 enum { MAXCONF = 64 };
16 char *confname[MAXCONF], *confval[MAXCONF];
27 reboot(void *, void *, ulong)
36 postnote(up, 1, "sys: odd address", NDebug);
46 p->kentry = up->kentry;
47 p->pcycles = -p->kentry;
50 switch(up->fpstate & ~FPillegal){
53 up->fpstate = FPinactive;
55 memmove(p->fpsave, up->fpsave, sizeof(FPsave));
56 p->fpstate = FPinactive;
68 p->pcycles = -p->kentry;
77 tos = (Tos*)(USTKTOP-sizeof(Tos));
79 tos->kcycles += t - up->kentry;
80 tos->pcycles = t + up->pcycles;
100 slcr[0xa1c/4] = 0x020202;
101 l2 = vmap(L2_BASE, BY2PG);
103 l2[TAGRAM] = l2[TAGRAM] & ~0x777 | 0x111;
104 l2[DATARAM] = l2[DATARAM] & ~0x777 | 0x121;
105 l2[PREFETCH] |= 3<<28 | 1<<24;
106 l2[AUX] |= 3<<28 | 1<<20;
108 while((l2[INVPA] & 1) != 0)
114 clean2pa(uintptr start, uintptr end)
119 end = (end + 31) & ~31;
120 for(pa = start; pa < end; pa += 32)
125 inval2pa(uintptr start, uintptr end)
130 end = (end + 31) & ~31;
131 for(pa = start; pa < end; pa += 32)
136 dmaflush(int clean, void *data, ulong len)
140 va = (uintptr)data & ~31;
142 len = ROUND(len, 32);
144 /* flush cache before write */
145 cleandse((uchar*)va, (uchar*)va+len);
146 clean2pa(pa, pa+len);
148 /* invalidate cache before read */
149 invaldse((uchar*)va, (uchar*)va+len);
150 inval2pa(pa, pa+len);
158 char *cp, *line[MAXCONF], *p, *q;
160 cp = (char *) CONFADDR;
163 for(q = cp; *q; q++){
172 n = getfields(cp, line, MAXCONF, 1, "\n");
173 for(i = 0; i < n; i++){
176 cp = strchr(line[i], '=');
180 confname[nconf] = line[i];
195 conf.ialloc = 16*1024*1024;
197 conf.mem[0].base = PGROUND((ulong)end - KZERO);
198 conf.mem[0].npage = (1024*1024*1024 - conf.mem[0].base) >> PGSHIFT;
203 for(i = 0; i < nelem(conf.mem); i++)
204 conf.npage += conf.mem[i].npage;
206 kmem = 200*1024*1024;
207 conf.upages = conf.npage - kmem/BY2PG;
208 kmem -= conf.upages*sizeof(Page)
209 + conf.nproc*sizeof(Proc)
210 + conf.nimage*sizeof(Image);
211 mainmem->maxsize = kmem;
212 imagmem->maxsize = kmem - (kmem/10);
218 char buf[ERRMAX], **sp;
225 ksetenv("cputype", "arm", 0);
227 ksetenv("service", "cpu", 0);
229 ksetenv("service", "terminal", 0);
230 ksetenv("console", "0", 0);
231 snprint(buf, sizeof(buf), "zynq %s", conffile);
232 ksetenv("terminal", buf, 0);
233 for(i = 0; i < nconf; i++){
234 if(*confname[i] != '*')
235 ksetenv(confname[i], confval[i], 0);
236 ksetenv(confname[i], confval[i], 1);
240 kproc("alarm", alarmkproc, 0);
242 sp = (char**)(USTKTOP - sizeof(Tos) - 8 - sizeof(sp[0])*4);
244 strcpy(sp[1] = (char*)&sp[4], "boot");
252 static int dat = 0xdeadbeef;
253 extern ulong vectors[];
255 assert(dat == 0xdeadbeef);
256 assert(((uintptr)vectors & 31) == 0);
257 assert(sizeof(Mach) + KSTACK <= MACHSIZE);
258 assert((KZERO & SECSZ - 1) == 0);
266 for(i = 0; i < nconf; i++)
267 if(cistrcmp(confname[i], n) == 0)
273 isaconfig(char *, int, ISAConf*)
281 print("cpu%d: %dMHz ARM Cortex-A9\n", m->machno, m->cpumhz);
287 extern void mpbootstrap(void); /* l.s */
299 memset(m1, 0, MACHSIZE);
301 m1->l1.pa = MACHL1(m1->machno)-KZERO;
302 m1->l1.va = KADDR(m1->l1.pa);
304 memset(m1->l1.va, 0, L1SZ);
305 for(i=0; i<L1X(VMAPSZ); i++)
306 m1->l1.va[L1X(VMAP)+i] = m->l1.va[L1X(VMAP)+i];
307 for(i=0; i<L1X(-KZERO); i++)
308 m1->l1.va[L1X(KZERO)+i] = m->l1.va[L1X(KZERO)+i];
310 cleandse((uchar*)KZERO, (uchar*)0xFFFFFFFF);
311 invaldse((uchar*)KZERO, (uchar*)0xFFFFFFFF);
313 /* ocm is uncached */
314 v = KADDR(0xFFFFF000);
315 v[0xFF0/4] = PADDR(mpbootstrap);
325 active.machs[m->machno] = 1;
344 uartputs(" from Bell Labs\n", 16);
368 setupwatchpts(Proc *, Watchpt *, int n)
371 error("no watchpoints");