2 #include "../port/lib.h"
7 #include "../port/netif.h"
10 #define Rbsz ROUNDUP(sizeof(Etherpkt)+16, 64)
96 typedef struct Ctlr Ctlr;
102 int rxconsi, rxprodi, txi;
112 return ((Ctlr*)v)->r[NET_STATUS] & PHY_IDLE;
116 mdwrite(Ctlr *c, int r, u16int v)
118 sleep(&c->phy, phyidle, c);
119 c->r[PHY_MAINT] = 1<<30 | 1<<28 | 1<<17 | c->phyaddr << 23 | r << 18 | v;
120 sleep(&c->phy, phyidle, c);
124 mdread(Ctlr *c, int r)
126 sleep(&c->phy, phyidle, c);
127 c->r[PHY_MAINT] = 1<<30 | 1<< 29 | 1<<17 | c->phyaddr << 23 | r << 18;
128 sleep(&c->phy, phyidle, c);
129 return c->r[PHY_MAINT];
142 mdwrite(c, MDCTRL, AUTONEG);
144 if((mdread(c, MDSTATUS) & LINK) == 0){
146 print("eth: no link\n");
147 while((mdread(c, MDSTATUS) & LINK) == 0)
148 tsleep(&up->sleep, return0, nil, Linkdelay);
150 v = mdread(c, MDPHYCTRL);
153 while((mdread(c, MDGSTATUS) & RECVOK) != RECVOK)
156 c->r[NET_CFG] |= GIGE_EN;
157 }else if((v & 0x20) != 0){
160 c->r[NET_CFG] = NET_CFG & ~GIGE_EN | SPEED;
161 }else if((v & 0x10) != 0){
164 c->r[NET_CFG] = NET_CFG & ~(GIGE_EN | SPEED);
169 c->r[NET_CFG] |= FDEN;
172 c->r[NET_CFG] &= ~FDEN;
175 print("eth: %s %s duplex link\n", sp, dpl);
176 while((mdread(c, MDSTATUS) & LINK) != 0)
177 tsleep(&up->sleep, return0, nil, Linkdelay);
188 while(c->rxprodi != c->rxconsi){
192 print("eth: out of memory for receive buffers\n");
197 r[0] = RxUsed | PADDR(bp->rp);
201 cleandse(bp->base, bp->lim);
202 clean2pa(PADDR(bp->base), PADDR(bp->lim));
204 c->rxprodi = (c->rxprodi + 1) & (RXRING - 1);
217 // print("rx! %p %p\n", PADDR(&c->rxr[2 * c->rxconsi]), c->r[RX_QBAR]);
219 r = &c->rxr[2 * c->rxconsi];
220 if((r[0] & RxUsed) == 0)
222 if((r[1] & FrameEnd) == 0)
223 print("eth: partial frame received -- shouldn't happen\n");
224 bp = c->rxs[c->rxconsi];
225 bp->wp = bp->rp + (r[1] & 0x1fff);
226 invaldse(bp->rp, bp->wp);
227 inval2pa(PADDR(bp->rp), PADDR(bp->wp));
228 etheriq(edev, bp, 1);
229 c->rxconsi = (c->rxconsi + 1) & (RXRING - 1);
244 r = &c->txr[2 * c->txi];
245 if((r[1] & TxUsed) == 0){
246 print("eth: transmit buffer full\n");
252 if(c->txs[c->txi] != nil)
253 freeb(c->txs[c->txi]);
255 cleandse(bp->rp, bp->wp);
256 clean2pa(PADDR(bp->rp), PADDR(bp->wp));
257 r[0] = PADDR(bp->rp);
258 r[1] = BLEN(bp) | FrameEnd | TxUsed;
259 if(r == c->txr + 2 * (TXRING - 1))
264 c->r[NET_CTRL] |= STARTTX;
265 c->txi = (c->txi + 1) & (TXRING - 1);
271 ethirq(Ureg *, void *arg)
279 fl = c->r[INTR_STATUS];
280 c->r[INTR_STATUS] = fl;
281 if((fl & MGMTDONE) != 0)
283 if((fl & TXUNDER) != 0)
285 if((fl & RXCOMPL) != 0)
287 if((fl & RXUSED) != 0)
288 print("eth: DMA read RX descriptor with used bit set, shouldn't happen\n");
289 if((fl & RXOVER) != 0)
290 print("eth: RX overrun, shouldn't happen\n");
301 c->r[RX_STATUS] = 0xf;
302 c->r[TX_STATUS] = 0xff;
303 c->r[INTR_DIS] = 0x7FFFEFF;
304 c->r[NET_CFG] = MDC_DIV << 18 | FDEN | SPEED | RX1536EN | GIGE_EN | RXCHKSUMEN;
305 c->r[SPEC_ADDR1_BOT] = edev->ea[0] | edev->ea[1] << 8 | edev->ea[2] << 16 | edev->ea[3] << 24;
306 c->r[SPEC_ADDR1_TOP] = edev->ea[4] | edev->ea[5] << 8;
307 c->r[DMA_CFG] = TXCHKSUMEN | (Rbsz/64) << 16 | 1 << 10 | 3 << 8 | 0x10;
309 c->rxr = ucalloc(8 * RXRING);
310 c->txr = ucalloc(8 * TXRING);
311 c->rxs = xspanalloc(4 * RXRING, 4, 0);
312 c->txs = xspanalloc(4 * TXRING, 4, 0);
313 for(i = 0; i < 2 * RXRING; ){
321 for(i = 0; i < 2 * TXRING; ){
325 c->txr[2 * (TXRING - 1)] |= 1<<30;
326 c->r[RX_QBAR] = PADDR(c->rxr);
327 c->r[TX_QBAR] = PADDR(c->txr);
329 c->r[NET_CTRL] = MDEN | TXEN | RXEN;
330 c->r[INTR_EN] = MGMTDONE | TXUNDER | RXCOMPL | RXUSED | RXOVER;
335 ethattach(Ether *edev)
343 kproc("ethproc", ethproc, edev);
347 etherpnp(Ether *edev)
350 static uchar mac[] = {0x0e, 0xa7, 0xde, 0xad, 0xbe, 0xef};
355 memmove(edev->ea, mac, 6);
357 edev->port = ETH0_BASE;
358 ct.r = vmap(edev->port, BY2PG);
360 edev->irqlevel = LEVEL;
362 edev->interrupt = ethirq;
363 edev->transmit = ethtx;
364 edev->attach = ethattach;
368 if(ethinit(edev) < 0){
378 addethercard("eth", etherpnp);