1 this is a plan 9 port to the Trimslice with tegra2 soc: dual-core,
2 dual-issue 1GHz Cortex-A9 system (v7a arch).
5 linux believes that u-boot runs in the bottom 4MB.
6 the l2 cache is a non-architectural bag nailed on the side.
7 mp arm systems have a generic interrupt controller; this one is gic v1(!).
8 vfp 3 floating-point is present.
10 section numbers (§) are in the tegra 2 tech. ref. man.
11 for a minimal cpu server, need these devices to work:
12 clock signals §5 (leave to u-boot),
13 pad mux + gpio crap §8, §11 and §18 (leave to u-boot),
15 ☑ uart (16[45]50) §22,
18 ☑ ether8169 via pcie §31.
20 ☑ 2nd cpu (cortex.a9.mpcore.pdf),
21 ☑ l2 cache (l2cache.pl310.pdf, errata),
22 ☑ fpu (cortex.a9.fp.pdf),
25 in-line 64-bit arithmetic,
26 eventually might want:
27 usb (e.g., for sata) §26,
30 and the really horrid ones:
38 40000000 256K iram (audio/video memory)
39 50000000 cortex-a9 cpu regs, periphbase, intr distrib, memsel,
41 54000000 graphics regs
42 58000000 gart (graphics window)
43 60000000 256MB ppsb bus dev regs, including semas, intr ctlr, dma,
44 arm7 cache, gpio, except. vects
45 70000000 256MB apc bus regs, including uarts, nand, nor, spi, rtc
47 80000000 1GB ahb extern mem, pcie for cpu only
48 90000000-97ffffff pcie 0 mem(?)
49 a0000000-a7ffffff pcie 0 prefetch mem, includes rtl8111dl ether(?)
50 a0020000 ether region 4
51 a0024000 ether region 2
53 c0000000 256MB ahb bus virtual b0000000
54 c3000000-c80007ff 81MB ide, usb, sata, mmc
55 d0000000 256MB nor flash virtual 40000000
57 fff00000 48K irom boot code
58 ffff0000 64K high vectors
60 use 0xc0000000 as KZERO.