6 #include "../port/lib.h"
11 enum { /* registers */
12 Rbr = 0, /* Receiver Buffer (RO) */
13 Thr = 0, /* Transmitter Holding (WO) */
14 Ier = 1, /* Interrupt Enable */
15 Iir = 2, /* Interrupt Identification (RO) */
16 Fcr = 2, /* FIFO Control (WO) */
17 Lcr = 3, /* Line Control */
18 Mcr = 4, /* Modem Control */
19 Lsr = 5, /* Line Status */
20 Msr = 6, /* Modem Status */
21 Scr = 7, /* Scratch Pad */
22 Mdr = 8, /* Mode Def'n (omap rw) */
23 // Usr = 31, /* Uart Status Register; missing in omap? */
24 Dll = 0, /* Divisor Latch LSB */
25 Dlm = 1, /* Divisor Latch MSB */
33 Erda = 0x01, /* Enable Received Data Available */
34 Ethre = 0x02, /* Enable Thr Empty */
35 Erls = 0x04, /* Enable Receiver Line Status */
36 Ems = 0x08, /* Enable Modem Status */
40 Ims = 0x00, /* Ms interrupt */
41 Ip = 0x01, /* Interrupt Pending (not) */
42 Ithre = 0x02, /* Thr Empty */
43 Irda = 0x04, /* Received Data Available */
44 Irls = 0x06, /* Receiver Line Status */
45 Ictoi = 0x0C, /* Character Time-out Indication */
47 Ifena = 0xC0, /* FIFOs enabled */
51 FIFOena = 0x01, /* FIFO enable */
52 FIFOrclr = 0x02, /* clear Rx FIFO */
53 FIFOtclr = 0x04, /* clear Tx FIFO */
55 FIFO1 = 0x00, /* Rx FIFO trigger level 1 byte */
56 FIFO4 = 0x40, /* 4 bytes */
57 FIFO8 = 0x80, /* 8 bytes */
58 FIFO14 = 0xC0, /* 14 bytes */
62 Wls5 = 0x00, /* Word Length Select 5 bits/byte */
63 Wls6 = 0x01, /* 6 bits/byte */
64 Wls7 = 0x02, /* 7 bits/byte */
65 Wls8 = 0x03, /* 8 bits/byte */
67 Stb = 0x04, /* 2 stop bits */
68 Pen = 0x08, /* Parity Enable */
69 Eps = 0x10, /* Even Parity Select */
70 Stp = 0x20, /* Stick Parity */
71 Brk = 0x40, /* Break */
72 Dlab = 0x80, /* Divisor Latch Access Bit */
76 Dtr = 0x01, /* Data Terminal Ready */
77 Rts = 0x02, /* Ready To Send */
78 Out1 = 0x04, /* no longer in use */
79 // Ie = 0x08, /* IRQ Enable (cd_sts_ch on omap) */
80 Dm = 0x10, /* Diagnostic Mode loopback */
84 Dr = 0x01, /* Data Ready */
85 Oe = 0x02, /* Overrun Error */
86 Pe = 0x04, /* Parity Error */
87 Fe = 0x08, /* Framing Error */
88 Bi = 0x10, /* Break Interrupt */
89 Thre = 0x20, /* Thr Empty */
90 Temt = 0x40, /* Transmitter Empty */
91 FIFOerr = 0x80, /* error in receiver FIFO */
95 Dcts = 0x01, /* Delta Cts */
96 Ddsr = 0x02, /* Delta Dsr */
97 Teri = 0x04, /* Trailing Edge of Ri */
98 Ddcd = 0x08, /* Delta Dcd */
99 Cts = 0x10, /* Clear To Send */
100 Dsr = 0x20, /* Data Set Ready */
101 Ri = 0x40, /* Ring Indicator */
102 Dcd = 0x80, /* Carrier Detect */
111 typedef struct Ctlr {
126 extern PhysUart i8250physuart;
128 static Ctlr i8250ctlr[] = {
129 { .io = (u32int*)PHYSCONS,
135 static Uart i8250uart[] = {
136 { .regs = &i8250ctlr[0], /* not [2] */
138 .freq = 3686000, /* Not used, we use the global i8250freq */
139 .phys = &i8250physuart,
144 #define csr8r(c, r) ((c)->io[r])
145 #define csr8w(c, r, v) ((c)->io[r] = (c)->sticky[r] | (v), coherence())
146 #define csr8o(c, r, v) ((c)->io[r] = (v), coherence())
149 i8250status(Uart* uart, void* buf, long n, long offset)
153 uchar ier, lcr, mcr, msr;
157 mcr = ctlr->sticky[Mcr];
158 msr = csr8r(ctlr, Msr);
159 ier = ctlr->sticky[Ier];
160 lcr = ctlr->sticky[Lcr];
162 "b%d c%d d%d e%d l%d m%d p%c r%d s%d i%d\n"
163 "dev(%d) type(%d) framing(%d) overruns(%d) "
164 "berr(%d) serr(%d)%s%s%s%s\n",
172 (lcr & Pen) ? ((lcr & Eps) ? 'e': 'o'): 'n',
183 (msr & Cts) ? " cts": "",
184 (msr & Dsr) ? " dsr": "",
185 (msr & Dcd) ? " dcd": "",
186 (msr & Ri) ? " ring": ""
188 n = readstr(offset, buf, n, p);
195 i8250fifo(Uart* uart, int level)
200 if(ctlr->hasfifo == 0)
204 * Changing the FIFOena bit in Fcr flushes data
205 * from both receive and transmit FIFOs; there's
206 * no easy way to guarantee not losing data on
207 * the receive side, but it's possible to wait until
208 * the transmitter is really empty.
211 while(!(csr8r(ctlr, Lsr) & Temt))
215 * Set the trigger level, default is the max.
217 * Some UARTs require FIFOena to be set before
218 * other bits can take effect, so set it twice.
225 level = FIFO1|FIFOena;
228 level = FIFO4|FIFOena;
231 level = FIFO8|FIFOena;
234 level = FIFO14|FIFOena;
237 csr8w(ctlr, Fcr, level);
238 csr8w(ctlr, Fcr, level);
243 i8250dtr(Uart* uart, int on)
252 ctlr->sticky[Mcr] |= Dtr;
254 ctlr->sticky[Mcr] &= ~Dtr;
259 i8250rts(Uart* uart, int on)
268 ctlr->sticky[Mcr] |= Rts;
270 ctlr->sticky[Mcr] &= ~Rts;
275 i8250modemctl(Uart* uart, int on)
282 ctlr->sticky[Ier] |= Ems;
285 uart->cts = csr8r(ctlr, Msr) & Cts;
288 ctlr->sticky[Ier] &= ~Ems;
293 iunlock(&uart->tlock);
295 /* modem needs fifo */
296 (*uart->phys->fifo)(uart, on);
300 i8250parity(Uart* uart, int parity)
306 lcr = ctlr->sticky[Lcr] & ~(Eps|Pen);
320 ctlr->sticky[Lcr] = lcr;
323 uart->parity = parity;
329 i8250stop(Uart* uart, int stop)
335 lcr = ctlr->sticky[Lcr] & ~Stb;
346 ctlr->sticky[Lcr] = lcr;
355 i8250bits(Uart* uart, int bits)
361 lcr = ctlr->sticky[Lcr] & ~WlsMASK;
379 ctlr->sticky[Lcr] = lcr;
388 i8250baud(Uart* uart, int baud)
390 #ifdef notdef /* don't change the speed */
393 extern int i8250freq; /* In the config file */
396 * Set the Baud rate by calculating and setting the Baud rate
397 * Generator Constant. This will work with fairly non-standard
400 if(i8250freq == 0 || baud <= 0)
402 bgc = (i8250freq+8*baud-1)/(16*baud);
405 while(csr8r(ctlr, Usr) & Busy)
407 csr8w(ctlr, Lcr, Dlab); /* begin kludge */
408 csr8o(ctlr, Dlm, bgc>>8);
409 csr8o(ctlr, Dll, bgc);
417 i8250break(Uart* uart, int ms)
422 panic("i8250break: nil up");
430 csr8w(ctlr, Lcr, Brk);
431 tsleep(&up->sleep, return0, 0, ms);
436 emptyoutstage(Uart *uart, int n)
438 _uartputs((char *)uart->op, n);
439 uart->op = uart->oe = uart->ostage;
443 i8250kick(Uart* uart)
448 if(/* uart->cts == 0 || */ uart->blocked)
451 if(!normalprint) { /* early */
452 if (uart->op < uart->oe)
453 emptyoutstage(uart, uart->oe - uart->op);
454 while ((i = uartstageoutput(uart)) > 0)
455 emptyoutstage(uart, i);
459 /* nothing more to send? then disable xmit intr */
461 if (uart->op >= uart->oe && qlen(uart->oq) == 0 &&
462 csr8r(ctlr, Lsr) & Temt) {
463 ctlr->sticky[Ier] &= ~Ethre;
469 * 128 here is an arbitrary limit to make sure
470 * we don't stay in this loop too long. If the
471 * chip's output queue is longer than 128, too
474 for(i = 0; i < 128; i++){
475 if(!(csr8r(ctlr, Lsr) & Thre))
477 if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
479 csr8o(ctlr, Thr, *uart->op++); /* start tx */
480 ctlr->sticky[Ier] |= Ethre;
481 csr8w(ctlr, Ier, 0); /* intr when done */
488 uartkick(&i8250uart[CONSOLE]);
492 i8250interrupt(Ureg*, void* arg)
496 int iir, lsr, old, r;
500 for(iir = csr8r(ctlr, Iir); !(iir & Ip); iir = csr8r(ctlr, Iir)){
501 switch(iir & IirMASK){
502 case Ims: /* Ms interrupt */
503 r = csr8r(ctlr, Msr);
508 if(old == 0 && uart->cts)
509 uart->ctsbackoff = 2;
510 iunlock(&uart->tlock);
514 if(uart->hup_dsr && uart->dsr && !old)
520 if(uart->hup_dcd && uart->dcd && !old)
525 case Ithre: /* Thr Empty */
528 case Irda: /* Received Data Available */
529 case Irls: /* Receiver Line Status */
530 case Ictoi: /* Character Time-out Indication */
532 * Consume any received data.
533 * If the received byte came in with a break,
534 * parity or framing error, throw it away;
535 * overrun is an indication that something has
536 * already been tossed.
538 while((lsr = csr8r(ctlr, Lsr)) & Dr){
539 if(lsr & (FIFOerr|Oe))
545 r = csr8r(ctlr, Rbr);
546 if(!(lsr & (Bi|Fe|Pe)))
552 iprint("weird uart interrupt type %#2.2uX\n", iir);
559 i8250disable(Uart* uart)
564 * Turn off DTR and RTS, disable interrupts and fifos.
566 (*uart->phys->dtr)(uart, 0);
567 (*uart->phys->rts)(uart, 0);
568 (*uart->phys->fifo)(uart, 0);
571 ctlr->sticky[Ier] = 0;
575 if(irqdisable(ctlr->irq, i8250interrupt, uart, uart->name) == 0)
581 i8250enable(Uart* uart, int ie)
587 return; /* too soon */
591 /* omap only: set uart/irda/cir mode to uart */
592 mode = csr8r(ctlr, Mdr);
593 csr8o(ctlr, Mdr, (mode & ~Modemask) | Modeuart);
595 ctlr->sticky[Lcr] = Wls8; /* no parity */
599 * Check if there is a FIFO.
600 * Changing the FIFOena bit in Fcr flushes data
601 * from both receive and transmit FIFOs; there's
602 * no easy way to guarantee not losing data on
603 * the receive side, but it's possible to wait until
604 * the transmitter is really empty.
605 * Also, reading the Iir outwith i8250interrupt()
606 * can be dangerous, but this should only happen
607 * once, before interrupts are enabled.
610 if(!ctlr->checkfifo){
612 * Wait until the transmitter is really empty.
614 while(!(csr8r(ctlr, Lsr) & Temt))
616 csr8w(ctlr, Fcr, FIFOena);
617 if(csr8r(ctlr, Iir) & Ifena)
625 * Enable interrupts and turn on DTR and RTS.
626 * Be careful if this is called to set up a polled serial line
627 * early on not to try to enable interrupts as interrupt-
628 * -enabling mechanisms might not be set up yet.
631 if(ctlr->iena == 0 && !ctlr->poll){
632 irqenable(ctlr->irq, i8250interrupt, uart, uart->name);
635 ctlr->sticky[Ier] = Erda;
636 // ctlr->sticky[Mcr] |= Ie; /* not on omap */
637 ctlr->sticky[Mcr] = 0;
640 ctlr->sticky[Ier] = 0;
641 ctlr->sticky[Mcr] = 0;
646 (*uart->phys->dtr)(uart, 1);
647 (*uart->phys->rts)(uart, 1);
650 * During startup, the i8259 interrupt controller is reset.
651 * This may result in a lost interrupt from the i8250 uart.
652 * The i8250 thinks the interrupt is still outstanding and does not
653 * generate any further interrupts. The workaround is to call the
654 * interrupt handler to clear any pending interrupt events.
655 * Note: this must be done after setting Ier.
658 i8250interrupt(nil, uart);
668 i8250getc(Uart* uart)
673 while(!(csr8r(ctlr, Lsr) & Dr))
675 return csr8r(ctlr, Rbr);
679 i8250putc(Uart* uart, int c)
684 if (!normalprint) { /* too early; use brute force */
687 while (!(((ulong *)PHYSCONS)[Lsr] & Thre))
689 ((ulong *)PHYSCONS)[Thr] = c;
696 for(i = 0; !(csr8r(ctlr, Lsr) & Thre) && i < 128; i++)
698 csr8o(ctlr, Thr, (uchar)c);
699 for(i = 0; !(csr8r(ctlr, Lsr) & Thre) && i < 128; i++)
706 i8250putc(&i8250uart[CONSOLE], c);
710 serialputs(char* s, int n)
717 i8250poll(Uart* uart)
722 * If PhysUart has a non-nil .poll member, this
723 * routine will be called from the uartclock timer.
724 * If the Ctlr .poll member is non-zero, when the
725 * Uart is enabled interrupts will not be enabled
726 * and the result is polled input and output.
727 * Not very useful here, but ports to new hardware
728 * or simulators can use this to get serial I/O
729 * without setting up the interrupt mechanism.
732 if(ctlr->iena || !ctlr->poll)
734 i8250interrupt(nil, uart);
738 PhysUart i8250physuart = {
741 .enable = i8250enable,
742 .disable = i8250disable,
744 .dobreak = i8250break,
748 .parity = i8250parity,
749 .modemctl = i8250modemctl,
752 .status = i8250status,
756 // .poll = i8250poll, /* only in 9k, not 9 */
760 i8250dumpregs(Ctlr* ctlr)
763 int _uartprint(char*, ...);
765 csr8w(ctlr, Lcr, Dlab);
766 dlm = csr8r(ctlr, Dlm);
767 dll = csr8r(ctlr, Dll);
770 _uartprint("dlm %#ux dll %#ux\n", dlm, dll);
773 Uart* uartenable(Uart *p);
775 /* must call this from a process's context */
779 Uart *uart = &i8250uart[CONSOLE];
782 return -1; /* too early */
784 if(uartenable(uart) != nil /* && uart->console */){
785 // iprint("i8250console: enabling console uart\n");
790 uartctl(uart, "b115200 l8 pn r1 s1 i1");
795 _uartputs(char* s, int n)
799 for(e = s+n; s < e; s++){
801 i8250putc(&i8250uart[CONSOLE], '\r');
802 i8250putc(&i8250uart[CONSOLE], *s);
807 _uartprint(char* fmt, ...)
814 n = vseprint(buf, buf+sizeof(buf), fmt, arg) - buf;