2 * Memory and machine-specific definitions. Used in C and assembler.
4 #define KiB 1024u /* Kibi 0x0000000000000400 */
5 #define MiB 1048576u /* Mebi 0x0000000000100000 */
6 #define GiB 1073741824u /* Gibi 000000000040000000 */
8 #define MIN(a, b) ((a) < (b)? (a): (b))
9 #define MAX(a, b) ((a) > (b)? (a): (b))
12 * Not sure where these macros should go.
13 * This probably isn't right but will do for now.
14 * The macro names are problematic too.
17 * In B(o), 'o' is the bit offset in the register.
18 * For multi-bit fields use F(v, o, w) where 'v' is the value
19 * of the bit-field of width 'w' with LSb at bit offset 'o'.
22 #define F(v, o, w) (((v) & ((1<<(w))-1))<<(o))
24 #define FCLR(d, o, w) ((d) & ~(((1<<(w))-1)<<(o)))
25 #define FEXT(d, o, w) (((d)>>(o)) & ((1<<(w))-1))
26 #define FINS(d, o, w, v) (FCLR((d), (o), (w))|F((v), (o), (w)))
27 #define FSET(d, o, w) ((d)|(((1<<(w))-1)<<(o)))
29 #define FMASK(o, w) (((1<<(w))-1)<<(o))
34 #define BY2PG (4*KiB) /* bytes per page */
35 #define PGSHIFT 12 /* log(BY2PG) */
36 #define PGROUND(s) ROUND(s, BY2PG)
37 #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
39 /* max # of cpus system can run. tegra2 cpu ids are two bits wide. */
41 #define MACHSIZE BY2PG
42 #define L1SIZE (4 * BY2PG)
44 #define KSTKSIZE (16*KiB) /* was 8K */
45 #define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */
51 #define USER 9 /* R9 is up-> */
52 #define MACH 10 /* R10 is m-> */
56 * KTZERO is used by kprof and dumpstack (if any).
58 * KZERO (0xc0000000) is mapped to physical 0 (start of dram).
59 * u-boot claims to occupy the first 4 MB of dram, but we're willing to
60 * step on it once we're loaded.
62 * L2 PTEs are stored in 4K before cpu0's Mach (8K to 12K above KZERO).
63 * cpu0's Mach struct is at L1 - MACHSIZE(4K) to L1 (12K to 16K above KZERO).
64 * L1 PTEs are stored from L1 to L1+32K (16K to 48K above KZERO).
65 * plan9.ini is loaded at CONFADDR (4MB).
66 * KTZERO may be anywhere after that.
68 #define KSEG0 0xC0000000 /* kernel segment */
69 /* mask to check segment; good for 1GB dram */
70 #define KSEGM 0xC0000000
71 #define KZERO KSEG0 /* kernel address space */
72 #define L1 (KZERO+16*KiB) /* cpu0 l1 page table; 16KiB aligned */
73 #define CONFADDR (KZERO+0x400000) /* unparsed plan9.ini */
74 #define CACHECONF (CONFADDR+48*KiB)
75 /* KTZERO must match loadaddr in mkfile */
76 #define KTZERO (KZERO+0x410000) /* kernel text start */
78 #define L2pages (2*MiB) /* high memory reserved for l2 page tables */
79 #define RESRVDHIMEM (64*KiB + MiB + L2pages) /* avoid HVECTOR, l2 pages */
80 /* we assume that we have 1 GB of ram, which is true for all trimslices. */
83 #define UZERO 0 /* user segment */
84 #define UTZERO (UZERO+BY2PG) /* user text start */
86 * moved USTKTOP down to 1GB to keep MMIO space out of user space.
87 * moved it down another MB to utterly avoid KADDR(stack_base) mapping
88 * to high exception vectors. see confinit().
90 #define USTKTOP (0x40000000 - 64*KiB - MiB) /* user segment end +1 */
91 #define USTKSIZE (8*1024*1024) /* user stack size */
93 /* address at which to copy and execute rebootcode */
94 #define REBOOTADDR KADDR(0x100)
99 #define BLOCKALIGN CACHELINESZ /* only used in allocb.c */
100 #define KSTACK KSTKSIZE
105 #define BI2BY 8 /* bits per byte */
108 #define BY2V 8 /* only used in xalloc.c */
110 #define CACHELINESZ 32 /* bytes per cache line */
111 #define PTEMAPMEM (1024*1024)
112 #define PTEPERTAB (PTEMAPMEM/BY2PG)
113 #define SEGMAPSIZE 1984 /* magic 16*124 */
114 #define SSEGMAPSIZE 16 /* magic */
115 #define PPN(x) ((x)&~(BY2PG-1)) /* pure page number? */
118 * With a little work these move to port.
120 #define PTEVALID (1<<0)
122 #define PTEWRITE (1<<1)
123 #define PTEUNCACHED (1<<2)
124 #define PTEKERNEL (1<<3)
127 * Physical machine information from here on.
132 #define PHYSIO 0x50000000 /* cpu */
133 #define VIRTIO PHYSIO
134 #define PHYSL2BAG 0x50043000 /* l2 cache bag-on-the-side */
135 #define PHYSEVP 0x6000f100 /* undocumented `exception vector' */
136 #define PHYSCONS 0x70006000 /* uart console */
137 #define PHYSIOEND 0xc0000000 /* end of ahb mem & pcie */
139 #define PHYSAHB 0xc0000000 /* ahb bus */
140 #define VIRTAHB 0xb0000000
141 #define P2VAHB(pa) ((pa) - PHYSAHB + VIRTAHB)
143 #define PHYSNOR 0xd0000000
144 #define VIRTNOR 0x40000000