sys/src/9/teg2/ether8169.c

   1 /*
   2  * Realtek RTL8110/8168/8169 Gigabit Ethernet Controllers.
   3  * There are some magic register values used which are not described in
   4  * any datasheet or driver but seem to be necessary.
   5  * There are slight differences between the chips in the series so some
   6  * tweaks may be needed.
   7  *
   8  * we use l1 and l2 cache ops; data must reach ram for dma.
   9  */
  10 #include "u.h"
  11 #include "../port/lib.h"
  12 #include "mem.h"
  13 #include "dat.h"
  14 #include "fns.h"
  15 #include "io.h"
  16 #include "../port/error.h"
  17 #include "../port/netif.h"
  18 #include "../port/etherif.h"
  19 #include "../port/ethermii.h"
  20
  21 typedef struct Ctlr Ctlr;
  22 typedef struct D D;                     /* Transmit/Receive Descriptor */
  23 typedef struct Dtcc Dtcc;
  24
  25 enum {
  26         Debug = 0,  /* beware: > 1 interferes with correct operation */
  27 };
  28
  29 enum {                                  /* registers */
  30         Idr0            = 0x00,         /* MAC address */
  31         Mar0            = 0x08,         /* Multicast address */
  32         Dtccr           = 0x10,         /* Dump Tally Counter Command */
  33         Tnpds           = 0x20,         /* Transmit Normal Priority Descriptors */
  34         Thpds           = 0x28,         /* Transmit High Priority Descriptors */
  35         Flash           = 0x30,         /* Flash Memory Read/Write */
  36         Erbcr           = 0x34,         /* Early Receive Byte Count */
  37         Ersr            = 0x36,         /* Early Receive Status */
  38         Cr              = 0x37,         /* Command Register */
  39         Tppoll          = 0x38,         /* Transmit Priority Polling */
  40         Imr             = 0x3C,         /* Interrupt Mask */
  41         Isr             = 0x3E,         /* Interrupt Status */
  42         Tcr             = 0x40,         /* Transmit Configuration */
  43         Rcr             = 0x44,         /* Receive Configuration */
  44         Tctr            = 0x48,         /* Timer Count */
  45         Mpc             = 0x4C,         /* Missed Packet Counter */
  46         Cr9346          = 0x50,         /* 9346 Command Register */
  47         Config0         = 0x51,         /* Configuration Register 0 */
  48         Config1         = 0x52,         /* Configuration Register 1 */
  49         Config2         = 0x53,         /* Configuration Register 2 */
  50         Config3         = 0x54,         /* Configuration Register 3 */
  51         Config4         = 0x55,         /* Configuration Register 4 */
  52         Config5         = 0x56,         /* Configuration Register 5 */
  53         Timerint        = 0x58,         /* Timer Interrupt */
  54         Mulint          = 0x5C,         /* Multiple Interrupt Select */
  55         Phyar           = 0x60,         /* PHY Access */
  56         Tbicsr0         = 0x64,         /* TBI Control and Status */
  57         Tbianar         = 0x68,         /* TBI Auto-Negotiation Advertisment */
  58         Tbilpar         = 0x6A,         /* TBI Auto-Negotiation Link Partner */
  59         Phystatus       = 0x6C,         /* PHY Status */
  60
  61         Rms             = 0xDA,         /* Receive Packet Maximum Size */
  62         Cplusc          = 0xE0,         /* C+ Command */
  63         Coal            = 0xE2,         /* Interrupt Mitigation (Coalesce) */
  64         Rdsar           = 0xE4,         /* Receive Descriptor Start Address */
  65         Etx             = 0xEC,         /* 8169: Early Tx Threshold; 32-byte units */
  66         Mtps            = 0xEC,         /* 8168: Maximum Transmit Packet Size */
  67 };
  68
  69 enum {                                  /* Dtccr */
  70         Cmd             = 0x00000008,   /* Command */
  71 };
  72
  73 enum {                                  /* Cr */
  74         Te              = 0x04,         /* Transmitter Enable */
  75         Re              = 0x08,         /* Receiver Enable */
  76         Rst             = 0x10,         /* Software Reset */
  77 };
  78
  79 enum {                                  /* Tppoll */
  80         Fswint          = 0x01,         /* Forced Software Interrupt */
  81         Npq             = 0x40,         /* Normal Priority Queue polling */
  82         Hpq             = 0x80,         /* High Priority Queue polling */
  83 };
  84
  85 enum {                                  /* Imr/Isr */
  86         Rok             = 0x0001,       /* Receive OK */
  87         Rer             = 0x0002,       /* Receive Error */
  88         Tok             = 0x0004,       /* Transmit OK */
  89         Ter             = 0x0008,       /* Transmit Error */
  90         Rdu             = 0x0010,       /* Receive Descriptor Unavailable */
  91         Punlc           = 0x0020,       /* Packet Underrun or Link Change */
  92         Fovw            = 0x0040,       /* Receive FIFO Overflow */
  93         Tdu             = 0x0080,       /* Transmit Descriptor Unavailable */
  94         Swint           = 0x0100,       /* Software Interrupt */
  95         Timeout         = 0x4000,       /* Timer */
  96         Serr            = 0x8000,       /* System Error */
  97 };
  98
  99 enum {                                  /* Tcr */
 100         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 101         MtxdmaMASK      = 0x00000700,
 102         Mtxdmaunlimited = 0x00000700,
 103         Acrc            = 0x00010000,   /* Append CRC (not) */
 104         Lbk0            = 0x00020000,   /* Loopback Test 0 */
 105         Lbk1            = 0x00040000,   /* Loopback Test 1 */
 106         Ifg2            = 0x00080000,   /* Interframe Gap 2 */
 107         HwveridSHIFT    = 23,           /* Hardware Version ID */
 108         HwveridMASK     = 0x7C800000,
 109         Macv01          = 0x00000000,   /* RTL8169 */
 110         Macv02          = 0x00800000,   /* RTL8169S/8110S */
 111         Macv03          = 0x04000000,   /* RTL8169S/8110S */
 112         Macv04          = 0x10000000,   /* RTL8169SB/8110SB */
 113         Macv05          = 0x18000000,   /* RTL8169SC/8110SC */
 114         Macv07          = 0x24800000,   /* RTL8102e */
 115 //      Macv8103e       = 0x24C00000,
 116         Macv25          = 0x28000000,   /* RTL8168D */
 117 //      Macv8168dp      = 0x28800000,
 118 //      Macv8168e       = 0x2C000000,
 119         Macv11          = 0x30000000,   /* RTL8168B/8111B */
 120         Macv14          = 0x30800000,   /* RTL8100E */
 121         Macv13          = 0x34000000,   /* RTL8101E */
 122         Macv07a         = 0x34800000,   /* RTL8102e */
 123         Macv12          = 0x38000000,   /* RTL8169B/8111B */
 124 //      Macv8168spin3   = 0x38400000,
 125         Macv15          = 0x38800000,   /* RTL8100E */
 126         Macv12a         = 0x3c000000,   /* RTL8169C/8111C */
 127 //      Macv19          = 0x3c000000,   /* dup Macv12a: RTL8111c-gr */
 128 //      Macv8168cspin2  = 0x3c400000,
 129 //      Macv8168cp      = 0x3c800000,
 130 //      Macv8139        = 0x60000000,
 131 //      Macv8139a       = 0x70000000,
 132 //      Macv8139ag      = 0x70800000,
 133 //      Macv8139b       = 0x78000000,
 134 //      Macv8130        = 0x7C000000,
 135 //      Macv8139c       = 0x74000000,
 136 //      Macv8139d       = 0x74400000,
 137 //      Macv8139cplus   = 0x74800000,
 138 //      Macv8101        = 0x74c00000,
 139 //      Macv8100        = 0x78800000,
 140 //      Macv8169_8110sbl= 0x7cc00000,
 141 //      Macv8169_8110sce= 0x98000000,
 142         Ifg0            = 0x01000000,   /* Interframe Gap 0 */
 143         Ifg1            = 0x02000000,   /* Interframe Gap 1 */
 144 };
 145
 146 enum {                                  /* Rcr */
 147         Aap             = 0x00000001,   /* Accept All Packets */
 148         Apm             = 0x00000002,   /* Accept Physical Match */
 149         Am              = 0x00000004,   /* Accept Multicast */
 150         Ab              = 0x00000008,   /* Accept Broadcast */
 151         Ar              = 0x00000010,   /* Accept Runt */
 152         Aer             = 0x00000020,   /* Accept Error */
 153         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
 154         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 155         MrxdmaMASK      = 0x00000700,
 156         Mrxdmaunlimited = 0x00000700,
 157         RxfthSHIFT      = 13,           /* Receive Buffer Length */
 158         RxfthMASK       = 0x0000E000,
 159         Rxfth256        = 0x00008000,
 160         Rxfthnone       = 0x0000E000,
 161         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
 162         MulERINT        = 0x01000000,   /* Multiple Early Interrupt Select */
 163 };
 164
 165 enum {                                  /* Cr9346 */
 166         Eedo            = 0x01,         /* */
 167         Eedi            = 0x02,         /* */
 168         Eesk            = 0x04,         /* */
 169         Eecs            = 0x08,         /* */
 170         Eem0            = 0x40,         /* Operating Mode */
 171         Eem1            = 0x80,
 172 };
 173
 174 enum {                                  /* Phyar */
 175         DataMASK        = 0x0000FFFF,   /* 16-bit GMII/MII Register Data */
 176         DataSHIFT       = 0,
 177         RegaddrMASK     = 0x001F0000,   /* 5-bit GMII/MII Register Address */
 178         RegaddrSHIFT    = 16,
 179         Flag            = 0x80000000,   /* */
 180 };
 181
 182 enum {                                  /* Phystatus */
 183         Fd              = 0x01,         /* Full Duplex */
 184         Linksts         = 0x02,         /* Link Status */
 185         Speed10         = 0x04,         /* */
 186         Speed100        = 0x08,         /* */
 187         Speed1000       = 0x10,         /* */
 188         Rxflow          = 0x20,         /* */
 189         Txflow          = 0x40,         /* */
 190         Entbi           = 0x80,         /* */
 191 };
 192
 193 enum {                                  /* Cplusc */
 194         Init1           = 0x0001,       /* 8168 */
 195         Mulrw           = 0x0008,       /* PCI Multiple R/W Enable */
 196         Dac             = 0x0010,       /* PCI Dual Address Cycle Enable */
 197         Rxchksum        = 0x0020,       /* Receive Checksum Offload Enable */
 198         Rxvlan          = 0x0040,       /* Receive VLAN De-tagging Enable */
 199         Pktcntoff       = 0x0080,       /* 8168, 8101 */
 200         Endian          = 0x0200,       /* Endian Mode */
 201 };
 202
 203 struct D {
 204         u32int  control;
 205         u32int  vlan;
 206         u32int  addrlo;
 207         u32int  addrhi;
 208 };
 209
 210 enum {                                  /* Transmit Descriptor control */
 211         TxflMASK        = 0x0000FFFF,   /* Transmit Frame Length */
 212         TxflSHIFT       = 0,
 213         Tcps            = 0x00010000,   /* TCP Checksum Offload */
 214         Udpcs           = 0x00020000,   /* UDP Checksum Offload */
 215         Ipcs            = 0x00040000,   /* IP Checksum Offload */
 216         Lgsen           = 0x08000000,   /* TSO; WARNING: contains lark's vomit */
 217 };
 218
 219 enum {                                  /* Receive Descriptor control */
 220         RxflMASK        = 0x00001FFF,   /* Receive Frame Length */
 221         Tcpf            = 0x00004000,   /* TCP Checksum Failure */
 222         Udpf            = 0x00008000,   /* UDP Checksum Failure */
 223         Ipf             = 0x00010000,   /* IP Checksum Failure */
 224         Pid0            = 0x00020000,   /* Protocol ID0 */
 225         Pid1            = 0x00040000,   /* Protocol ID1 */
 226         Crce            = 0x00080000,   /* CRC Error */
 227         Runt            = 0x00100000,   /* Runt Packet */
 228         Res             = 0x00200000,   /* Receive Error Summary */
 229         Rwt             = 0x00400000,   /* Receive Watchdog Timer Expired */
 230         Fovf            = 0x00800000,   /* FIFO Overflow */
 231         Bovf            = 0x01000000,   /* Buffer Overflow */
 232         Bar             = 0x02000000,   /* Broadcast Address Received */
 233         Pam             = 0x04000000,   /* Physical Address Matched */
 234         Mar             = 0x08000000,   /* Multicast Address Received */
 235 };
 236
 237 enum {                                  /* General Descriptor control */
 238         Ls              = 0x10000000,   /* Last Segment Descriptor */
 239         Fs              = 0x20000000,   /* First Segment Descriptor */
 240         Eor             = 0x40000000,   /* End of Descriptor Ring */
 241         Own             = 0x80000000,   /* Ownership: belongs to hw */
 242 };
 243
 244 /*
 245  */
 246 enum {                                  /* Ring sizes  (<= 1024) */
 247         Ntd             = 1024,         /* Transmit Ring */
 248         /* at 1Gb/s, it only takes 12 ms. to fill a 1024-buffer ring */
 249         Nrd             = 1024,         /* Receive Ring */
 250         Nrb             = 4096,
 251
 252         Mtu             = ETHERMAXTU,
 253         Mps             = ROUNDUP(ETHERMAXTU+4, 128),
 254 //      Mps             = Mtu + 8 + 14, /* if(mtu>ETHERMAXTU) */
 255 };
 256
 257 struct Dtcc {
 258         u64int  txok;
 259         u64int  rxok;
 260         u64int  txer;
 261         u32int  rxer;
 262         u16int  misspkt;
 263         u16int  fae;
 264         u32int  tx1col;
 265         u32int  txmcol;
 266         u64int  rxokph;
 267         u64int  rxokbrd;
 268         u32int  rxokmu;
 269         u16int  txabt;
 270         u16int  txundrn;
 271 };
 272
 273 enum {                                          /* Variants */
 274         Rtl8100e        = (0x8136<<16)|0x10EC,  /* RTL810[01]E: pci -e */
 275         Rtl8169c        = (0x0116<<16)|0x16EC,  /* RTL8169C+ (USR997902) */
 276         Rtl8169sc       = (0x8167<<16)|0x10EC,  /* RTL8169SC */
 277         Rtl8168b        = (0x8168<<16)|0x10EC,  /* RTL8168B: pci-e */
 278         Rtl8169         = (0x8169<<16)|0x10EC,  /* RTL8169 */
 279         /*
 280          * trimslice is 10ec/8168 (8168b) Macv25 (8168D) but
 281          * compulab says 8111dl.
 282          *      oui 0x732 (aaeon) phyno 1, macv = 0x28000000 phyv = 0x0002
 283          */
 284 };
 285
 286 struct Ctlr {
 287         void*   nic;
 288         int     port;
 289         Pcidev* pcidev;
 290         Ctlr*   next;
 291         Ether*  ether;                  /* point back */
 292         int     active;
 293
 294         QLock   alock;                  /* attach */
 295         Lock    ilock;                  /* init */
 296         int     init;                   /*  */
 297
 298         int     pciv;                   /*  */
 299         int     macv;                   /* MAC version */
 300         int     phyv;                   /* PHY version */
 301         int     pcie;                   /* flag: pci-express device? */
 302
 303         uvlong  mchash;                 /* multicast hash */
 304
 305         Mii*    mii;
 306
 307 //      Lock    tlock;                  /* transmit */
 308         Rendez  trendez;
 309         D*      td;                     /* descriptor ring */
 310         Block** tb;                     /* transmit buffers */
 311         int     ntd;
 312
 313         int     tdh;                    /* head - producer index (host) */
 314         int     tdt;                    /* tail - consumer index (NIC) */
 315         int     ntdfree;
 316         int     ntq;
 317
 318         int     nrb;
 319
 320 //      Lock    rlock;                  /* receive */
 321         Rendez  rrendez;
 322         D*      rd;                     /* descriptor ring */
 323         Block** rb;                     /* receive buffers */
 324         int     nrd;
 325
 326         int     rdh;                    /* head - producer index (NIC) */
 327         int     rdt;                    /* tail - consumer index (host) */
 328         int     nrdfree;
 329
 330         Lock    reglock;
 331         int     tcr;                    /* transmit configuration register */
 332         int     rcr;                    /* receive configuration register */
 333         int     imr;
 334         int     isr;                    /* sw copy for kprocs */
 335
 336         QLock   slock;                  /* statistics */
 337         Dtcc*   dtcc;
 338         uint    txdu;
 339         uint    tcpf;
 340         uint    udpf;
 341         uint    ipf;
 342         uint    fovf;
 343         uint    ierrs;
 344         uint    rer;
 345         uint    rdu;
 346         uint    punlc;
 347         uint    fovw;
 348         uint    mcast;
 349         uint    frag;                   /* partial packets; rb was too small */
 350 };
 351
 352 static Ctlr* rtl8169ctlrhead;
 353 static Ctlr* rtl8169ctlrtail;
 354
 355 static Lock rblock;                     /* free receive Blocks */
 356 static Block* rbpool;
 357
 358 #define csr8r(c, r)     (*((uchar *) ((c)->nic)+(r)))
 359 #define csr16r(c, r)    (*((u16int *)((c)->nic)+((r)/2)))
 360 #define csr32p(c, r)    ((u32int *)  ((c)->nic)+((r)/4))
 361 #define csr32r(c, r)    (*csr32p(c, r))
 362
 363 #define csr8w(c, r, b)  (*((uchar *) ((c)->nic)+(r))     = (b), coherence())
 364 #define csr16w(c, r, w) (*((u16int *)((c)->nic)+((r)/2)) = (w), coherence())
 365 #define csr32w(c, r, v) (*csr32p(c, r) = (v), coherence())
 366
 367 static int
 368 rtl8169miimir(Mii* mii, int pa, int ra)
 369 {
 370         uint r;
 371         int timeo;
 372         Ctlr *ctlr;
 373
 374         if(pa != 1)
 375                 return -1;
 376         ctlr = mii->ctlr;
 377         r = (ra<<16) & RegaddrMASK;
 378         csr32w(ctlr, Phyar, r);
 379         delay(1);
 380         for(timeo = 0; timeo < 2000; timeo++){
 381                 if((r = csr32r(ctlr, Phyar)) & Flag)
 382                         break;
 383                 microdelay(100);
 384         }
 385         if(!(r & Flag))
 386                 return -1;
 387
 388         return (r & DataMASK)>>DataSHIFT;
 389 }
 390
 391 static int
 392 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
 393 {
 394         uint r;
 395         int timeo;
 396         Ctlr *ctlr;
 397
 398         if(pa != 1)
 399                 return -1;
 400         ctlr = mii->ctlr;
 401         r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
 402         csr32w(ctlr, Phyar, r);
 403         delay(1);
 404         for(timeo = 0; timeo < 2000; timeo++){
 405                 if(!((r = csr32r(ctlr, Phyar)) & Flag))
 406                         break;
 407                 microdelay(100);
 408         }
 409         if(r & Flag)
 410                 return -1;
 411
 412         return 0;
 413 }
 414
 415 static int
 416 rtl8169mii(Ctlr* ctlr)
 417 {
 418         MiiPhy *phy;
 419
 420         /*
 421          * Link management.
 422          */
 423         if((ctlr->mii = malloc(sizeof(Mii))) == nil)
 424                 return -1;
 425         ctlr->mii->mir = rtl8169miimir;
 426         ctlr->mii->miw = rtl8169miimiw;
 427         ctlr->mii->ctlr = ctlr;
 428
 429         /*
 430          * Get rev number out of Phyidr2 so can config properly.
 431          * There's probably more special stuff for Macv0[234] needed here.
 432          */
 433         ilock(&ctlr->reglock);
 434         ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
 435         if(ctlr->macv == Macv02){
 436                 csr8w(ctlr, 0x82, 1);                           /* magic */
 437                 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);      /* magic */
 438         }
 439
 440         if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
 441                 iunlock(&ctlr->reglock);
 442                 free(ctlr->mii);
 443                 ctlr->mii = nil;
 444                 return -1;
 445         }
 446         print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 447                 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 448
 449         miiane(ctlr->mii, ~0, ~0, ~0);
 450         iunlock(&ctlr->reglock);
 451
 452         return 0;
 453 }
 454
 455 static Block*
 456 rballoc(void)
 457 {
 458         Block *bp;
 459
 460         ilock(&rblock);
 461         if((bp = rbpool) != nil){
 462                 rbpool = bp->next;
 463                 bp->next = nil;
 464         }
 465         iunlock(&rblock);
 466         return bp;
 467 }
 468
 469 static void
 470 rbfree(Block *bp)
 471 {
 472         bp->wp = bp->rp = bp->lim - Mps;
 473         bp->flag &= ~(Bipck | Budpck | Btcpck | Bpktck);
 474
 475         ilock(&rblock);
 476         bp->next = rbpool;
 477         rbpool = bp;
 478         iunlock(&rblock);
 479 }
 480
 481 static void
 482 rtl8169promiscuous(void* arg, int on)
 483 {
 484         Ether *edev;
 485         Ctlr * ctlr;
 486
 487         edev = arg;
 488         ctlr = edev->ctlr;
 489         ilock(&ctlr->ilock);
 490         ilock(&ctlr->reglock);
 491
 492         if(on)
 493                 ctlr->rcr |= Aap;
 494         else
 495                 ctlr->rcr &= ~Aap;
 496         csr32w(ctlr, Rcr, ctlr->rcr);
 497         iunlock(&ctlr->reglock);
 498         iunlock(&ctlr->ilock);
 499 }
 500
 501 enum {
 502         /* everyone else uses 0x04c11db7, but they both produce the same crc */
 503         Etherpolybe = 0x04c11db6,
 504         Bytemask = (1<<8) - 1,
 505 };
 506
 507 static ulong
 508 ethercrcbe(uchar *addr, long len)
 509 {
 510         int i, j;
 511         ulong c, crc, carry;
 512
 513         crc = ~0UL;
 514         for (i = 0; i < len; i++) {
 515                 c = addr[i];
 516                 for (j = 0; j < 8; j++) {
 517                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
 518                         crc <<= 1;
 519                         c >>= 1;
 520                         if (carry)
 521                                 crc = (crc ^ Etherpolybe) | carry;
 522                 }
 523         }
 524         return crc;
 525 }
 526
 527 static ulong
 528 swabl(ulong l)
 529 {
 530         return l>>24 | (l>>8) & (Bytemask<<8) |
 531                 (l<<8) & (Bytemask<<16) | l<<24;
 532 }
 533
 534 static void
 535 rtl8169multicast(void* ether, uchar *eaddr, int add)
 536 {
 537         Ether *edev;
 538         Ctlr *ctlr;
 539
 540         if (!add)
 541                 return; /* ok to keep receiving on old mcast addrs */
 542
 543         edev = ether;
 544         ctlr = edev->ctlr;
 545         ilock(&ctlr->ilock);
 546         ilock(&ctlr->reglock);
 547
 548         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
 549
 550         ctlr->rcr |= Am;
 551         csr32w(ctlr, Rcr, ctlr->rcr);
 552
 553         /* pci-e variants reverse the order of the hash byte registers */
 554         if (ctlr->pcie) {
 555                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
 556                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
 557         } else {
 558                 csr32w(ctlr, Mar0,   ctlr->mchash);
 559                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
 560         }
 561
 562         iunlock(&ctlr->reglock);
 563         iunlock(&ctlr->ilock);
 564 }
 565
 566 static long
 567 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
 568 {
 569         char *p;
 570         Ctlr *ctlr;
 571         Dtcc *dtcc;
 572         int i, l, r, timeo;
 573
 574         ctlr = edev->ctlr;
 575         qlock(&ctlr->slock);
 576
 577         p = nil;
 578         if(waserror()){
 579                 qunlock(&ctlr->slock);
 580                 free(p);
 581                 nexterror();
 582         }
 583
 584         /* copy hw statistics into ctlr->dtcc */
 585         dtcc = ctlr->dtcc;
 586         allcache->invse(dtcc, sizeof *dtcc);
 587         ilock(&ctlr->reglock);
 588         csr32w(ctlr, Dtccr+4, 0);
 589         csr32w(ctlr, Dtccr, PCIWADDR(dtcc)|Cmd);        /* initiate dma? */
 590         for(timeo = 0; timeo < 1000; timeo++){
 591                 if(!(csr32r(ctlr, Dtccr) & Cmd))
 592                         break;
 593                 delay(1);
 594         }
 595         iunlock(&ctlr->reglock);
 596         if(csr32r(ctlr, Dtccr) & Cmd)
 597                 error(Eio);
 598
 599         edev->oerrs = dtcc->txer;
 600         edev->crcs = dtcc->rxer;
 601         edev->frames = dtcc->fae;
 602         edev->buffs = dtcc->misspkt;
 603         edev->overflows = ctlr->txdu + ctlr->rdu;
 604
 605         if(n == 0){
 606                 qunlock(&ctlr->slock);
 607                 poperror();
 608                 return 0;
 609         }
 610
 611         if((p = malloc(READSTR)) == nil)
 612                 error(Enomem);
 613
 614         l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
 615         l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
 616         l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
 617         l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
 618         l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
 619         l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
 620         l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
 621         l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
 622         l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
 623         l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
 624         l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
 625         l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
 626         l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
 627
 628         l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
 629         l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
 630         l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
 631         l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
 632         l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
 633         l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs);
 634         l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
 635         l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
 636         l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
 637         l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
 638
 639         l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
 640         l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
 641         l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
 642
 643         if(ctlr->mii != nil && ctlr->mii->curphy != nil){
 644                 l += snprint(p+l, READSTR, "phy:   ");
 645                 for(i = 0; i < NMiiPhyr; i++){
 646                         if(i && ((i & 0x07) == 0))
 647                                 l += snprint(p+l, READSTR-l, "\n       ");
 648                         r = miimir(ctlr->mii, i);
 649                         l += snprint(p+l, READSTR-l, " %4.4ux", r);
 650                 }
 651                 snprint(p+l, READSTR-l, "\n");
 652         }
 653
 654         n = readstr(offset, a, n, p);
 655
 656         qunlock(&ctlr->slock);
 657         poperror();
 658         free(p);
 659
 660         return n;
 661 }
 662
 663 static void
 664 rtl8169halt(Ctlr* ctlr)
 665 {
 666         ilock(&ctlr->reglock);
 667         csr32w(ctlr, Timerint, 0);
 668         csr8w(ctlr, Cr, 0);
 669         csr16w(ctlr, Imr, 0);
 670         csr16w(ctlr, Isr, ~0);
 671         iunlock(&ctlr->reglock);
 672 }
 673
 674 static int
 675 rtl8169reset(Ctlr* ctlr)
 676 {
 677         u32int r;
 678         int timeo;
 679
 680         /*
 681          * Soft reset the controller.
 682          */
 683         ilock(&ctlr->reglock);
 684         csr8w(ctlr, Cr, Rst);
 685         for(r = timeo = 0; timeo < 1000; timeo++){
 686                 r = csr8r(ctlr, Cr);
 687                 if(!(r & Rst))
 688                         break;
 689                 delay(1);
 690         }
 691         iunlock(&ctlr->reglock);
 692
 693         rtl8169halt(ctlr);
 694
 695         if(r & Rst)
 696                 return -1;
 697         return 0;
 698 }
 699
 700 static void
 701 rtl8169shutdown(Ether *ether)
 702 {
 703         rtl8169reset(ether->ctlr);
 704 }
 705
 706 static int
 707 rtl8169replenish(Ether *edev)
 708 {
 709         int rdt;
 710         Block *bp;
 711         Ctlr *ctlr;
 712         D *d;
 713
 714         ctlr = edev->ctlr;
 715         if (ctlr->nrd == 0) {
 716                 iprint("rtl8169replenish: not yet initialised\n");
 717                 return -1;
 718         }
 719         rdt = ctlr->rdt;
 720         assert(ctlr->rb);
 721         assert(ctlr->rd);
 722         while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
 723                 d = &ctlr->rd[rdt];
 724                 if (d == nil)
 725                         panic("rtl8169replenish: nil ctlr->rd[%d]", rdt);
 726                 if (d->control & Own) { /* ctlr owns it? shouldn't happen */
 727                         iprint("replenish: descriptor owned by hw\n");
 728                         break;
 729                 }
 730                 if(ctlr->rb[rdt] == nil){
 731                         bp = rballoc();
 732                         if(bp == nil){
 733                                 iprint("rtl8169: no available buffers\n");
 734                                 break;
 735                         }
 736                         ctlr->rb[rdt] = bp;
 737                         d->addrhi = 0;
 738                         coherence();
 739                         d->addrlo = PCIWADDR(bp->rp);
 740                         coherence();
 741                 } else
 742                         iprint("8169: replenish: rx overrun\n");
 743                 d->control = (d->control & ~RxflMASK) | Mps | Own;
 744                 coherence();
 745
 746                 rdt = NEXT(rdt, ctlr->nrd);
 747                 ctlr->nrdfree++;
 748         }
 749         ctlr->rdt = rdt;
 750         coherence();
 751         return 0;
 752 }
 753
 754 static void
 755 ckrderrs(Ctlr *ctlr, Block *bp, ulong control)
 756 {
 757         if(control & Fovf)
 758                 ctlr->fovf++;
 759         if(control & Mar)
 760                 ctlr->mcast++;
 761
 762         switch(control & (Pid1|Pid0)){
 763         case Pid0:
 764                 if(control & Tcpf){
 765                         iprint("8169: bad tcp checksum\n");
 766                         ctlr->tcpf++;
 767                         break;
 768                 }
 769                 bp->flag |= Btcpck;
 770                 break;
 771         case Pid1:
 772                 if(control & Udpf){
 773                         iprint("8169: bad udp checksum\n");
 774                         ctlr->udpf++;
 775                         break;
 776                 }
 777                 bp->flag |= Budpck;
 778                 break;
 779         case Pid1|Pid0:
 780                 if(control & Ipf){
 781                         iprint("8169: bad ip checksum\n");
 782                         ctlr->ipf++;
 783                         break;
 784                 }
 785                 bp->flag |= Bipck;
 786                 break;
 787         }
 788 }
 789
 790 static void
 791 badpkt(Ether *edev, int rdh, ulong control)
 792 {
 793         Ctlr *ctlr;
 794
 795         ctlr = edev->ctlr;
 796         /* Res is only valid if Fs is set */
 797         if(control & Res)
 798                 iprint("8169: rcv error; d->control %#.8lux\n", control);
 799         else if (control == 0) {                /* buggered? */
 800                 if (edev->link)
 801                         iprint("8169: rcv: d->control==0 (wtf?)\n");
 802         } else {
 803                 ctlr->frag++;
 804                 iprint("8169: rcv'd frag; d->control %#.8lux\n", control);
 805         }
 806         if (ctlr->rb[rdh])
 807                 freeb(ctlr->rb[rdh]);
 808 }
 809
 810 void
 811 qpkt(Ether *edev, int rdh, ulong control)
 812 {
 813         int len;
 814         Block *bp;
 815         Ctlr *ctlr;
 816
 817         ctlr = edev->ctlr;
 818         len = (control & RxflMASK) - 4;
 819         if ((uint)len > Mps)
 820                 if (len < 0)
 821                         panic("8169: received pkt non-existent");
 822                 else if (len > Mps)
 823                         panic("8169: received pkt too big");
 824         bp = ctlr->rb[rdh];
 825         bp->wp = bp->rp + len;
 826         bp->next = nil;
 827
 828         allcache->invse(bp->rp, len);   /* clear any stale cached packet */
 829         ckrderrs(ctlr, bp, control);
 830         etheriq(edev, bp);
 831
 832         if(Debug > 1)
 833                 iprint("R%d ", len);
 834 }
 835
 836 static int
 837 pktstoread(void* v)
 838 {
 839         Ctlr *ctlr = v;
 840
 841         return ctlr->isr & (Fovw|Rdu|Rer|Rok) &&
 842                 !(ctlr->rd[ctlr->rdh].control & Own);
 843 }
 844
 845 static void
 846 rproc(void* arg)
 847 {
 848         int rdh;
 849         ulong control;
 850         Ctlr *ctlr;
 851         D *rd;
 852         Ether *edev;
 853
 854         edev = arg;
 855         ctlr = edev->ctlr;
 856         while(waserror())
 857                 ;
 858         for(;;){
 859                 /* wait for next interrupt */
 860                 ilock(&ctlr->reglock);
 861                 ctlr->imr |= Fovw|Rdu|Rer|Rok;
 862                 csr16w(ctlr, Imr, ctlr->imr);
 863                 iunlock(&ctlr->reglock);
 864
 865                 sleep(&ctlr->rrendez, pktstoread, ctlr);
 866
 867                 /* clear saved isr bits */
 868                 ilock(&ctlr->reglock);
 869                 ctlr->isr &= ~(Fovw|Rdu|Rer|Rok);
 870                 iunlock(&ctlr->reglock);
 871
 872                 rdh = ctlr->rdh;
 873                 for (rd = &ctlr->rd[rdh]; !(rd->control & Own);
 874                      rd = &ctlr->rd[rdh]){
 875                         control = rd->control;
 876                         if((control & (Fs|Ls|Res)) == (Fs|Ls))
 877                                 qpkt(edev, rdh, control);
 878                         else
 879                                 badpkt(edev, rdh, control);
 880                         ctlr->rb[rdh] = nil;
 881                         coherence();
 882                         rd->control &= Eor;
 883                         coherence();
 884
 885                         ctlr->nrdfree--;
 886                         rdh = NEXT(rdh, ctlr->nrd);
 887                         if(ctlr->nrdfree < ctlr->nrd/2) {
 888                                 /* replenish reads ctlr->rdh */
 889                                 ctlr->rdh = rdh;
 890                                 rtl8169replenish(edev);
 891                                 /* if replenish called restart, rdh is reset */
 892                                 rdh = ctlr->rdh;
 893                         }
 894                 }
 895                 ctlr->rdh = rdh;
 896         }
 897 }
 898
 899 static int
 900 pktstosend(void* v)
 901 {
 902         Ether *edev = v;
 903         Ctlr *ctlr = edev->ctlr;
 904
 905         return ctlr->isr & (Ter|Tok) &&
 906                 !(ctlr->td[ctlr->tdh].control & Own) && edev->link;
 907 }
 908
 909 static void
 910 tproc(void* arg)
 911 {
 912         int x, len;
 913         Block *bp;
 914         Ctlr *ctlr;
 915         D *d;
 916         Ether *edev;
 917
 918         edev = arg;
 919         ctlr = edev->ctlr;
 920         for(;;){
 921                 /* wait for next interrupt */
 922                 ilock(&ctlr->reglock);
 923                 ctlr->imr |= Ter|Tok;
 924                 csr16w(ctlr, Imr, ctlr->imr);
 925                 iunlock(&ctlr->reglock);
 926
 927                 sleep(&ctlr->trendez, pktstosend, edev);
 928
 929                 /* clear saved isr bits */
 930                 ilock(&ctlr->reglock);
 931                 ctlr->isr &= ~(Ter|Tok);
 932                 iunlock(&ctlr->reglock);
 933
 934                 /* reclaim transmitted Blocks */
 935                 for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
 936                         d = &ctlr->td[x];
 937                         if(d == nil || d->control & Own)
 938                                 break;
 939
 940                         /*
 941                          * Free it up.
 942                          * Need to clean the descriptor here? Not really.
 943                          * Simple freeb for now (no chain and freeblist).
 944                          * Use ntq count for now.
 945                          */
 946                         freeb(ctlr->tb[x]);
 947                         ctlr->tb[x] = nil;
 948                         d->control &= Eor;
 949                         coherence();
 950
 951                         ctlr->ntq--;
 952                 }
 953                 ctlr->tdh = x;
 954
 955                 if (ctlr->ntq > 0)
 956                         csr8w(ctlr, Tppoll, Npq); /* kick xmiter to keep it going */
 957                 /* copy as much of my output q as possible into output ring */
 958                 x = ctlr->tdt;
 959                 while(ctlr->ntq < (ctlr->ntd-1)){
 960                         if((bp = qget(edev->oq)) == nil)
 961                                 break;
 962
 963                         /* make sure the whole packet is in ram */
 964                         len = BLEN(bp);
 965                         allcache->wbse(bp->rp, len);
 966
 967                         d = &ctlr->td[x];
 968                         assert(d);
 969                         assert(!(d->control & Own));
 970                         d->addrhi = 0;
 971                         d->addrlo = PCIWADDR(bp->rp);
 972                         ctlr->tb[x] = bp;
 973                         coherence();
 974                         d->control = (d->control & ~TxflMASK) |
 975                                 Own | Fs | Ls | len;
 976                         coherence();
 977
 978                         if(Debug > 1)
 979                                 iprint("T%d ", len);
 980
 981                         x = NEXT(x, ctlr->ntd);
 982                         ctlr->ntq++;
 983
 984                         ctlr->tdt = x;
 985                         coherence();
 986                         csr8w(ctlr, Tppoll, Npq);       /* kick xmiter again */
 987                 }
 988                 if(x != ctlr->tdt){             /* added new packet(s)? */
 989                         ctlr->tdt = x;
 990                         coherence();
 991                         csr8w(ctlr, Tppoll, Npq);
 992                 }
 993                 else if(ctlr->ntq >= (ctlr->ntd-1))
 994                         ctlr->txdu++;
 995         }
 996 }
 997
 998 static int
 999 rtl8169init(Ether* edev)
1000 {
1001         u32int r;
1002         Ctlr *ctlr;
1003         ushort cplusc;
1004
1005         ctlr = edev->ctlr;
1006         ilock(&ctlr->ilock);
1007         rtl8169reset(ctlr);
1008
1009         ilock(&ctlr->reglock);
1010         switch(ctlr->pciv){
1011         case Rtl8169sc:
1012                 csr8w(ctlr, Cr, 0);
1013                 break;
1014         case Rtl8168b:
1015         case Rtl8169c:
1016                 /* 8168b manual says set c+ reg first, then command */
1017                 csr16w(ctlr, Cplusc, 0x2000);           /* magic */
1018                 csr8w(ctlr, Cr, 0);
1019                 break;
1020         }
1021
1022         /*
1023          * MAC Address is not settable on some (all?) chips.
1024          * Must put chip into config register write enable mode.
1025          */
1026         csr8w(ctlr, Cr9346, Eem1|Eem0);
1027
1028         /*
1029          * Transmitter.
1030          */
1031         memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
1032         ctlr->tdh = ctlr->tdt = 0;
1033         ctlr->ntq = 0;
1034         ctlr->td[ctlr->ntd-1].control = Eor;
1035
1036         /*
1037          * Receiver.
1038          * Need to do something here about the multicast filter.
1039          */
1040         memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
1041         ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
1042         ctlr->rd[ctlr->nrd-1].control = Eor;
1043
1044         rtl8169replenish(edev);
1045
1046         switch(ctlr->pciv){
1047         default:
1048                 ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Apm;
1049                 break;
1050         case Rtl8168b:
1051         case Rtl8169c:
1052                 ctlr->rcr = Rxfthnone|6<<MrxdmaSHIFT|Ab|Apm; /* DMA max 1024 */
1053                 break;
1054         }
1055
1056         /*
1057          * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
1058          * settings in Tcr/Rcr; the (1<<14) is magic.
1059          */
1060         cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
1061         switch(ctlr->pciv){
1062         case Rtl8168b:
1063         case Rtl8169c:
1064                 cplusc |= Pktcntoff | Init1;
1065                 break;
1066         }
1067         cplusc |= /*Rxchksum|*/Mulrw;
1068         switch(ctlr->macv){
1069         default:
1070                 panic("ether8169: unknown macv %#08ux for vid %#ux did %#ux",
1071                         ctlr->macv, ctlr->pcidev->vid, ctlr->pcidev->did);
1072         case Macv01:
1073                 break;
1074         case Macv02:
1075         case Macv03:
1076                 cplusc |= 1<<14;                        /* magic */
1077                 break;
1078         case Macv05:
1079                 /*
1080                  * This is interpreted from clearly bogus code
1081                  * in the manufacturer-supplied driver, it could
1082                  * be wrong. Untested.
1083                  */
1084                 r = csr8r(ctlr, Config2) & 0x07;
1085                 if(r == 0x01)                           /* 66MHz PCI */
1086                         csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */
1087                 else
1088                         csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */
1089                 pciclrmwi(ctlr->pcidev);
1090                 break;
1091         case Macv13:
1092                 /*
1093                  * This is interpreted from clearly bogus code
1094                  * in the manufacturer-supplied driver, it could
1095                  * be wrong. Untested.
1096                  */
1097                 pcicfgw8(ctlr->pcidev, 0x68, 0x00);     /* magic */
1098                 pcicfgw8(ctlr->pcidev, 0x69, 0x08);     /* magic */
1099                 break;
1100         case Macv04:
1101         case Macv07:
1102         case Macv07a:
1103         case Macv11:
1104         case Macv12:
1105         case Macv12a:
1106         case Macv14:
1107         case Macv15:
1108         case Macv25:
1109                 break;
1110         }
1111
1112         /*
1113          * Enable receiver/transmitter.
1114          * Need to do this first or some of the settings below
1115          * won't take.
1116          */
1117         switch(ctlr->pciv){
1118         default:
1119                 csr8w(ctlr, Cr, Te|Re);
1120                 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
1121                 csr32w(ctlr, Rcr, ctlr->rcr);
1122                 break;
1123         case Rtl8169sc:
1124         case Rtl8168b:
1125                 break;
1126         }
1127         ctlr->mchash = 0;
1128         csr32w(ctlr, Mar0,   0);
1129         csr32w(ctlr, Mar0+4, 0);
1130
1131         /*
1132          * Interrupts.
1133          * Disable Tdu for now, the transmit routine will tidy.
1134          * Tdu means the NIC ran out of descriptors to send (i.e., the
1135          * output ring is empty), so it doesn't really need to ever be on.
1136          *
1137          * The timer runs at the PCI(-E) clock frequency, 125MHz for PCI-E,
1138          * presumably 66MHz for PCI.  Thus the units for PCI-E controllers
1139          * (e.g., 8168) are 8ns, and only the buggy 8168 seems to need to use
1140          * timeouts to keep from stalling.
1141          */
1142         csr32w(ctlr, Tctr, 0);
1143         /* Tok makes the whole system run faster */
1144         ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok;
1145         switch(ctlr->pciv){
1146         case Rtl8169sc:
1147         case Rtl8168b:
1148                 /* alleged workaround for rx fifo overflow on 8168[bd] */
1149                 ctlr->imr &= ~Rdu;
1150                 break;
1151         }
1152         csr16w(ctlr, Imr, ctlr->imr);
1153
1154         /*
1155          * Clear missed-packet counter;
1156          * clear early transmit threshold value;
1157          * set the descriptor ring base addresses;
1158          * set the maximum receive packet size;
1159          * no early-receive interrupts.
1160          *
1161          * note: the maximum rx size is a filter.  the size of the buffer
1162          * in the descriptor ring is still honored.  we will toss >Mtu
1163          * packets because they've been fragmented into multiple
1164          * rx buffers.
1165          */
1166         csr32w(ctlr, Mpc, 0);
1167         if (ctlr->pcie)
1168                 csr8w(ctlr, Mtps, Mps / 128);
1169         else
1170                 csr8w(ctlr, Etx, 0x3f);         /* max; no early transmission */
1171         csr32w(ctlr, Tnpds+4, 0);
1172         csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
1173         csr32w(ctlr, Rdsar+4, 0);
1174         csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
1175         csr16w(ctlr, Rms, 2048);                /* was Mps; see above comment */
1176         r = csr16r(ctlr, Mulint) & 0xF000;      /* no early rx interrupts */
1177         csr16w(ctlr, Mulint, r);
1178         csr16w(ctlr, Cplusc, cplusc);
1179         csr16w(ctlr, Coal, 0);
1180
1181         /*
1182          * Set configuration.
1183          */
1184         switch(ctlr->pciv){
1185         case Rtl8169sc:
1186                 csr8w(ctlr, Cr, Te|Re);
1187                 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
1188                 csr32w(ctlr, Rcr, ctlr->rcr);
1189                 break;
1190         case Rtl8168b:
1191         case Rtl8169c:
1192                 csr16w(ctlr, Cplusc, 0x2000);           /* magic */
1193                 csr8w(ctlr, Cr, Te|Re);
1194                 csr32w(ctlr, Tcr, Ifg1|Ifg0|6<<MtxdmaSHIFT); /* DMA max 1024 */
1195                 csr32w(ctlr, Rcr, ctlr->rcr);
1196                 break;
1197         }
1198         ctlr->tcr = csr32r(ctlr, Tcr);
1199         csr8w(ctlr, Cr9346, 0);
1200
1201         iunlock(&ctlr->reglock);
1202         iunlock(&ctlr->ilock);
1203
1204 //      rtl8169mii(ctlr);
1205
1206         return 0;
1207 }
1208
1209 static void
1210 rtl8169attach(Ether* edev)
1211 {
1212         int timeo, s, i;
1213         char name[KNAMELEN];
1214         Block *bp;
1215         Ctlr *ctlr;
1216
1217         ctlr = edev->ctlr;
1218         s = splhi();
1219         qlock(&ctlr->alock);
1220         if(ctlr->init || waserror()) {
1221                 qunlock(&ctlr->alock);
1222                 splx(s);
1223                 return;
1224         }
1225         ctlr->td = ucallocalign(sizeof(D)*Ntd, 256, 0);
1226         ctlr->tb = malloc(Ntd*sizeof(Block*));
1227         ctlr->ntd = Ntd;
1228
1229         ctlr->rd = ucallocalign(sizeof(D)*Nrd, 256, 0);
1230         ctlr->rb = malloc(Nrd*sizeof(Block*));
1231         ctlr->nrd = Nrd;
1232
1233         ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
1234         if(waserror()){
1235                 free(ctlr->td);
1236                 free(ctlr->tb);
1237                 free(ctlr->rd);
1238                 free(ctlr->rb);
1239                 free(ctlr->dtcc);
1240                 nexterror();
1241         }
1242         if(ctlr->td == nil || ctlr->tb == nil || ctlr->rd == nil ||
1243            ctlr->rb == nil || ctlr->dtcc == nil)
1244                 error(Enomem);
1245
1246         /* allocate private receive-buffer pool */
1247         ctlr->nrb = Nrb;
1248         for(i = 0; i < Nrb; i++){
1249                 if((bp = allocb(Mps)) == nil)
1250                         error(Enomem);
1251                 bp->free = rbfree;
1252                 freeb(bp);
1253         }
1254
1255         rtl8169init(edev);
1256         ctlr->init = 1;
1257         qunlock(&ctlr->alock);
1258         splx(s);
1259         poperror();                             /* free */
1260         poperror();                             /* qunlock */
1261
1262         /* signal secondary cpus that l1 ptes are stable */
1263         l1ptstable.word = 1;
1264         allcache->wbse(&l1ptstable, sizeof l1ptstable);
1265
1266         s = spllo();
1267         /* Don't wait long for link to be ready. */
1268         for(timeo = 0; timeo < 50 && miistatus(ctlr->mii) != 0; timeo++)
1269 //              tsleep(&up->sleep, return0, 0, 100); /* fewer miistatus msgs */
1270                 delay(100);
1271
1272         while (!edev->link)
1273                 tsleep(&up->sleep, return0, 0, 10);
1274         splx(s);
1275
1276         snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
1277         kproc(name, rproc, edev);
1278
1279         snprint(name, KNAMELEN, "#l%dtproc", edev->ctlrno);
1280         kproc(name, tproc, edev);
1281 }
1282
1283 /* call with ctlr->reglock held */
1284 static void
1285 rtl8169link(Ether* edev)
1286 {
1287         uint r;
1288         int limit;
1289         Ctlr *ctlr;
1290
1291         ctlr = edev->ctlr;
1292
1293         if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
1294                 if (edev->link) {
1295                         edev->link = 0;
1296                         csr8w(ctlr, Cr, Re);
1297                         iprint("#l%d: link down\n", edev->ctlrno);
1298                 }
1299                 return;
1300         }
1301         if (edev->link == 0) {
1302                 edev->link = 1;
1303                 csr8w(ctlr, Cr, Te|Re);
1304                 iprint("#l%d: link up\n", edev->ctlrno);
1305         }
1306         limit = 256*1024;
1307         if(r & Speed10){
1308                 edev->mbps = 10;
1309                 limit = 65*1024;
1310         } else if(r & Speed100)
1311                 edev->mbps = 100;
1312         else if(r & Speed1000)
1313                 edev->mbps = 1000;
1314
1315         if(edev->oq != nil)
1316                 qsetlimit(edev->oq, limit);
1317 }
1318
1319 static void
1320 rtl8169transmit(Ether* edev)
1321 {
1322         Ctlr *ctlr;
1323
1324         ctlr = edev->ctlr;
1325         if (ctlr == nil || ctlr->ntd == 0) {
1326                 iprint("rtl8169transmit: not yet initialised\n");
1327                 return;
1328         }
1329         wakeup(&ctlr->trendez);
1330 }
1331
1332 /*
1333  * the controller has lost its mind, so reset it.
1334  * call with ctlr->reglock held.
1335  */
1336 static void
1337 restart(Ether *edev, char *why)
1338 {
1339         int i, s, del;
1340         Ctlr *ctlr;
1341         static int inrestart;
1342         static Lock rstrtlck;
1343
1344         /* keep other cpus out */
1345         s = splhi();
1346         if (inrestart) {
1347                 splx(s);
1348                 return;
1349         }
1350         ilock(&rstrtlck);
1351
1352         ctlr = edev->ctlr;
1353         if (ctlr == nil || !ctlr->init) {
1354                 iunlock(&rstrtlck);
1355                 splx(s);
1356                 return;
1357         }
1358
1359         if (Debug)
1360                 iprint("#l%d: restart due to %s\n", edev->ctlrno, why);
1361         inrestart = 1;
1362
1363         /* process any pkts in the rings */
1364         wakeup(&ctlr->rrendez);
1365         coherence();
1366         rtl8169transmit(edev);
1367         /* allow time to drain 1024-buffer ring */
1368         for (del = 0; del < 13 && ctlr->ntq > 0; del++)
1369                 delay(1);
1370
1371         iunlock(&ctlr->reglock);
1372         rtl8169reset(ctlr);
1373         /* free any remaining unprocessed input buffers */
1374         for (i = 0; i < ctlr->nrd; i++) {
1375                 freeb(ctlr->rb[i]);
1376                 ctlr->rb[i] = nil;
1377         }
1378         rtl8169init(edev);
1379         ilock(&ctlr->reglock);
1380
1381         rtl8169link(edev);
1382         rtl8169transmit(edev);          /* drain any output queue */
1383         wakeup(&ctlr->rrendez);
1384
1385         inrestart = 0;
1386
1387         iunlock(&rstrtlck);
1388         splx(s);
1389 }
1390
1391 static ulong
1392 rcvdiag(Ether *edev, ulong isr)
1393 {
1394         Ctlr *ctlr;
1395
1396         ctlr = edev->ctlr;
1397         if(!(isr & (Punlc|Rok)))
1398                 ctlr->ierrs++;
1399         if(isr & Rer)
1400                 ctlr->rer++;
1401         if(isr & Rdu)
1402                 ctlr->rdu++;
1403         if(isr & Punlc)
1404                 ctlr->punlc++;
1405         if(isr & Fovw)
1406                 ctlr->fovw++;
1407         if (isr & (Fovw|Rdu|Rer)) {
1408                 if (isr & ~(Tdu|Tok|Rok))               /* harmless */
1409                         iprint("#l%d: isr %8.8#lux\n", edev->ctlrno, isr);
1410                 restart(edev, "rcv error");
1411                 isr = ~0;
1412         }
1413         return isr;
1414 }
1415
1416 void
1417 rtl8169interrupt(Ureg*, void* arg)
1418 {
1419         Ctlr *ctlr;
1420         Ether *edev;
1421         u32int isr;
1422
1423         edev = arg;
1424         ctlr = edev->ctlr;
1425         ilock(&ctlr->reglock);
1426
1427         while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
1428                 ctlr->isr |= isr;               /* merge bits for [rt]proc */
1429                 csr16w(ctlr, Isr, isr);         /* dismiss? */
1430                 if((isr & ctlr->imr) == 0)
1431                         break;
1432                 if(isr & Fovw && ctlr->pciv == Rtl8168b) {
1433                         /*
1434                          * Fovw means we got behind; relatively common on 8168.
1435                          * this is a big hammer, but it gets things going again.
1436                          */
1437                         ctlr->fovw++;
1438                         restart(edev, "rx fifo overrun");
1439                         break;
1440                 }
1441                 if(isr & (Fovw|Punlc|Rdu|Rer|Rok)) {
1442                         ctlr->imr &= ~(Fovw|Rdu|Rer|Rok);
1443                         csr16w(ctlr, Imr, ctlr->imr);
1444                         wakeup(&ctlr->rrendez);
1445
1446                         if (isr & (Fovw|Punlc|Rdu|Rer)) {
1447                                 isr = rcvdiag(edev, isr);
1448                                 if (isr == ~0)
1449                                         break;          /* restarted */
1450                         }
1451                         isr &= ~(Fovw|Rdu|Rer|Rok);
1452                 }
1453                 if(isr & (Ter|Tok)){
1454                         ctlr->imr &= ~(Ter|Tok);
1455                         csr16w(ctlr, Imr, ctlr->imr);
1456                         wakeup(&ctlr->trendez);
1457
1458                         if (isr & Ter)
1459                                 iprint("xmit err; isr %8.8#ux\n", isr);
1460                         isr &= ~(Ter|Tok);
1461                 }
1462
1463                 if(isr & Punlc){
1464                         rtl8169link(edev);
1465                         isr &= ~Punlc;
1466                 }
1467
1468                 /*
1469                  * Some of the reserved bits get set sometimes...
1470                  */
1471                 if(isr & (Serr|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
1472                         panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux",
1473                                 csr16r(ctlr, Imr), isr);
1474         }
1475         if (edev->link && ctlr->ntq > 0)
1476                 csr8w(ctlr, Tppoll, Npq); /* kick xmiter to keep it going */
1477         iunlock(&ctlr->reglock);
1478         /*
1479          * extinguish pci-e controller interrupt source.
1480          * should be done more cleanly.
1481          */
1482         if (ctlr->pcie)
1483                 pcieintrdone();
1484 }
1485
1486 int
1487 vetmacv(Ctlr *ctlr, uint *macv)
1488 {
1489         *macv = csr32r(ctlr, Tcr) & HwveridMASK;
1490         switch(*macv){
1491         default:
1492                 return -1;
1493         case Macv01:
1494         case Macv02:
1495         case Macv03:
1496         case Macv04:
1497         case Macv05:
1498         case Macv07:
1499         case Macv07a:
1500         case Macv11:
1501         case Macv12:
1502         case Macv12a:
1503         case Macv13:
1504         case Macv14:
1505         case Macv15:
1506         case Macv25:
1507                 break;
1508         }
1509         return 0;
1510 }
1511
1512 static void
1513 rtl8169pci(void)
1514 {
1515         Pcidev *p;
1516         Ctlr *ctlr;
1517         int i, pcie;
1518         uint macv, bar;
1519         void *mem;
1520
1521         p = nil;
1522         while(p = pcimatch(p, 0, 0)){
1523                 if(p->ccrb != 0x02 || p->ccru != 0)
1524                         continue;
1525
1526                 pcie = 0;
1527                 switch(i = ((p->did<<16)|p->vid)){
1528                 default:
1529                         continue;
1530                 case Rtl8100e:                  /* RTL810[01]E ? */
1531                 case Rtl8168b:                  /* RTL8168B */
1532                         pcie = 1;
1533                         break;
1534                 case Rtl8169c:                  /* RTL8169C */
1535                 case Rtl8169sc:                 /* RTL8169SC */
1536                 case Rtl8169:                   /* RTL8169 */
1537                         break;
1538                 case (0xC107<<16)|0x1259:       /* Corega CG-LAPCIGT */
1539                         i = Rtl8169;
1540                         break;
1541                 }
1542
1543                 bar = p->mem[2].bar & ~0x0F;
1544                 assert(bar != 0);
1545                 assert(!(p->mem[2].bar & Barioaddr));
1546                 if(0) iprint("rtl8169: %d-bit register accesses\n",
1547                         ((p->mem[2].bar >> Barwidthshift) & Barwidthmask) ==
1548                          Barwidth32? 32: 64);
1549                 mem = (void *)bar;      /* don't need to vmap on trimslice */
1550                 if(mem == 0){
1551                         print("rtl8169: can't map %#ux\n", bar);
1552                         continue;
1553                 }
1554                 ctlr = malloc(sizeof(Ctlr));
1555                 if(ctlr == nil)
1556                         error(Enomem);
1557                 ctlr->nic = mem;
1558                 ctlr->port = bar;
1559                 ctlr->pcidev = p;
1560                 ctlr->pciv = i;
1561                 ctlr->pcie = pcie;
1562
1563                 if(vetmacv(ctlr, &macv) == -1){
1564                         free(ctlr);
1565                         print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1566                         continue;
1567                 }
1568
1569                 if(pcigetpms(p) > 0){
1570                         pcisetpms(p, 0);
1571
1572                         for(i = 0; i < 6; i++)
1573                                 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1574                         pcicfgw8(p, PciINTL, p->intl);
1575                         pcicfgw8(p, PciLTR, p->ltr);
1576                         pcicfgw8(p, PciCLS, p->cls);
1577                         pcicfgw16(p, PciPCR, p->pcr);
1578                 }
1579
1580                 if(rtl8169reset(ctlr)){
1581                         free(ctlr);
1582                         continue;
1583                 }
1584
1585                 /*
1586                  * Extract the chip hardware version,
1587                  * needed to configure each properly.
1588                  */
1589                 ctlr->macv = macv;
1590
1591                 rtl8169mii(ctlr);
1592                 pcisetbme(p);
1593
1594                 if(rtl8169ctlrhead != nil)
1595                         rtl8169ctlrtail->next = ctlr;
1596                 else
1597                         rtl8169ctlrhead = ctlr;
1598                 rtl8169ctlrtail = ctlr;
1599         }
1600 }
1601
1602 static int
1603 rtl8169pnp(Ether* edev)
1604 {
1605         u32int r;
1606         Ctlr *ctlr;
1607         uchar ea[Eaddrlen];
1608         static int once;
1609
1610         if(once == 0){
1611                 once = 1;
1612                 rtl8169pci();
1613         }
1614
1615         /*
1616          * Any adapter matches if no edev->port is supplied,
1617          * otherwise the ports must match.
1618          */
1619         for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1620                 if(ctlr->active)
1621                         continue;
1622                 if(edev->port == 0 || edev->port == ctlr->port){
1623                         ctlr->active = 1;
1624                         break;
1625                 }
1626         }
1627         if(ctlr == nil)
1628                 return -1;
1629
1630         edev->ctlr = ctlr;
1631         ctlr->ether = edev;
1632         edev->port = ctlr->port;
1633 //      edev->irq = ctlr->pcidev->intl; /* incorrect on trimslice */
1634         edev->irq = Pcieirq;            /* trimslice: non-msi pci-e intr */
1635         edev->tbdf = ctlr->pcidev->tbdf;
1636         edev->mbps = 1000;
1637         edev->maxmtu = Mtu;
1638
1639         /*
1640          * Check if the adapter's station address is to be overridden.
1641          * If not, read it from the device and set in edev->ea.
1642          */
1643         memset(ea, 0, Eaddrlen);
1644         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1645                 r = csr32r(ctlr, Idr0);
1646                 edev->ea[0] = r;
1647                 edev->ea[1] = r>>8;
1648                 edev->ea[2] = r>>16;
1649                 edev->ea[3] = r>>24;
1650                 r = csr32r(ctlr, Idr0+4);
1651                 edev->ea[4] = r;
1652                 edev->ea[5] = r>>8;
1653         }
1654
1655         edev->attach = rtl8169attach;
1656         edev->transmit = rtl8169transmit;
1657         edev->ifstat = rtl8169ifstat;
1658
1659         edev->arg = edev;
1660         edev->promiscuous = rtl8169promiscuous;
1661         edev->multicast = rtl8169multicast;
1662         edev->shutdown = rtl8169shutdown;
1663
1664         ilock(&ctlr->reglock);
1665         rtl8169link(edev);
1666         iunlock(&ctlr->reglock);
1667
1668         intrenable(edev->irq, rtl8169interrupt, edev, 0, edev->name);
1669
1670         return 0;
1671 }
1672
1673 void
1674 ether8169link(void)
1675 {
1676         addethercard("rtl8169", rtl8169pnp);
1677 }