sys/src/9/teg2/ether8169.c

   1 /*
   2  * Realtek RTL8110/8168/8169 Gigabit Ethernet Controllers.
   3  * There are some magic register values used which are not described in
   4  * any datasheet or driver but seem to be necessary.
   5  * There are slight differences between the chips in the series so some
   6  * tweaks may be needed.
   7  *
   8  * we use l1 and l2 cache ops; data must reach ram for dma.
   9  */
  10 #include "u.h"
  11 #include "../port/lib.h"
  12 #include "mem.h"
  13 #include "dat.h"
  14 #include "fns.h"
  15 #include "io.h"
  16 #include "../port/pci.h"
  17 #include "../port/error.h"
  18 #include "../port/netif.h"
  19 #include "../port/etherif.h"
  20 #include "../port/ethermii.h"
  21
  22 typedef struct Ctlr Ctlr;
  23 typedef struct D D;                     /* Transmit/Receive Descriptor */
  24 typedef struct Dtcc Dtcc;
  25
  26 enum {
  27         Debug = 0,  /* beware: > 1 interferes with correct operation */
  28 };
  29
  30 enum {                                  /* registers */
  31         Idr0            = 0x00,         /* MAC address */
  32         Mar0            = 0x08,         /* Multicast address */
  33         Dtccr           = 0x10,         /* Dump Tally Counter Command */
  34         Tnpds           = 0x20,         /* Transmit Normal Priority Descriptors */
  35         Thpds           = 0x28,         /* Transmit High Priority Descriptors */
  36         Flash           = 0x30,         /* Flash Memory Read/Write */
  37         Erbcr           = 0x34,         /* Early Receive Byte Count */
  38         Ersr            = 0x36,         /* Early Receive Status */
  39         Cr              = 0x37,         /* Command Register */
  40         Tppoll          = 0x38,         /* Transmit Priority Polling */
  41         Imr             = 0x3C,         /* Interrupt Mask */
  42         Isr             = 0x3E,         /* Interrupt Status */
  43         Tcr             = 0x40,         /* Transmit Configuration */
  44         Rcr             = 0x44,         /* Receive Configuration */
  45         Tctr            = 0x48,         /* Timer Count */
  46         Mpc             = 0x4C,         /* Missed Packet Counter */
  47         Cr9346          = 0x50,         /* 9346 Command Register */
  48         Config0         = 0x51,         /* Configuration Register 0 */
  49         Config1         = 0x52,         /* Configuration Register 1 */
  50         Config2         = 0x53,         /* Configuration Register 2 */
  51         Config3         = 0x54,         /* Configuration Register 3 */
  52         Config4         = 0x55,         /* Configuration Register 4 */
  53         Config5         = 0x56,         /* Configuration Register 5 */
  54         Timerint        = 0x58,         /* Timer Interrupt */
  55         Mulint          = 0x5C,         /* Multiple Interrupt Select */
  56         Phyar           = 0x60,         /* PHY Access */
  57         Tbicsr0         = 0x64,         /* TBI Control and Status */
  58         Tbianar         = 0x68,         /* TBI Auto-Negotiation Advertisment */
  59         Tbilpar         = 0x6A,         /* TBI Auto-Negotiation Link Partner */
  60         Phystatus       = 0x6C,         /* PHY Status */
  61
  62         Rms             = 0xDA,         /* Receive Packet Maximum Size */
  63         Cplusc          = 0xE0,         /* C+ Command */
  64         Coal            = 0xE2,         /* Interrupt Mitigation (Coalesce) */
  65         Rdsar           = 0xE4,         /* Receive Descriptor Start Address */
  66         Etx             = 0xEC,         /* 8169: Early Tx Threshold; 32-byte units */
  67         Mtps            = 0xEC,         /* 8168: Maximum Transmit Packet Size */
  68 };
  69
  70 enum {                                  /* Dtccr */
  71         Cmd             = 0x00000008,   /* Command */
  72 };
  73
  74 enum {                                  /* Cr */
  75         Te              = 0x04,         /* Transmitter Enable */
  76         Re              = 0x08,         /* Receiver Enable */
  77         Rst             = 0x10,         /* Software Reset */
  78 };
  79
  80 enum {                                  /* Tppoll */
  81         Fswint          = 0x01,         /* Forced Software Interrupt */
  82         Npq             = 0x40,         /* Normal Priority Queue polling */
  83         Hpq             = 0x80,         /* High Priority Queue polling */
  84 };
  85
  86 enum {                                  /* Imr/Isr */
  87         Rok             = 0x0001,       /* Receive OK */
  88         Rer             = 0x0002,       /* Receive Error */
  89         Tok             = 0x0004,       /* Transmit OK */
  90         Ter             = 0x0008,       /* Transmit Error */
  91         Rdu             = 0x0010,       /* Receive Descriptor Unavailable */
  92         Punlc           = 0x0020,       /* Packet Underrun or Link Change */
  93         Fovw            = 0x0040,       /* Receive FIFO Overflow */
  94         Tdu             = 0x0080,       /* Transmit Descriptor Unavailable */
  95         Swint           = 0x0100,       /* Software Interrupt */
  96         Timeout         = 0x4000,       /* Timer */
  97         Serr            = 0x8000,       /* System Error */
  98 };
  99
 100 enum {                                  /* Tcr */
 101         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 102         MtxdmaMASK      = 0x00000700,
 103         Mtxdmaunlimited = 0x00000700,
 104         Acrc            = 0x00010000,   /* Append CRC (not) */
 105         Lbk0            = 0x00020000,   /* Loopback Test 0 */
 106         Lbk1            = 0x00040000,   /* Loopback Test 1 */
 107         Ifg2            = 0x00080000,   /* Interframe Gap 2 */
 108         HwveridSHIFT    = 23,           /* Hardware Version ID */
 109         HwveridMASK     = 0x7C800000,
 110         Macv01          = 0x00000000,   /* RTL8169 */
 111         Macv02          = 0x00800000,   /* RTL8169S/8110S */
 112         Macv03          = 0x04000000,   /* RTL8169S/8110S */
 113         Macv04          = 0x10000000,   /* RTL8169SB/8110SB */
 114         Macv05          = 0x18000000,   /* RTL8169SC/8110SC */
 115         Macv07          = 0x24800000,   /* RTL8102e */
 116 //      Macv8103e       = 0x24C00000,
 117         Macv25          = 0x28000000,   /* RTL8168D */
 118 //      Macv8168dp      = 0x28800000,
 119 //      Macv8168e       = 0x2C000000,
 120         Macv11          = 0x30000000,   /* RTL8168B/8111B */
 121         Macv14          = 0x30800000,   /* RTL8100E */
 122         Macv13          = 0x34000000,   /* RTL8101E */
 123         Macv07a         = 0x34800000,   /* RTL8102e */
 124         Macv12          = 0x38000000,   /* RTL8169B/8111B */
 125 //      Macv8168spin3   = 0x38400000,
 126         Macv15          = 0x38800000,   /* RTL8100E */
 127         Macv12a         = 0x3c000000,   /* RTL8169C/8111C */
 128 //      Macv19          = 0x3c000000,   /* dup Macv12a: RTL8111c-gr */
 129 //      Macv8168cspin2  = 0x3c400000,
 130 //      Macv8168cp      = 0x3c800000,
 131 //      Macv8139        = 0x60000000,
 132 //      Macv8139a       = 0x70000000,
 133 //      Macv8139ag      = 0x70800000,
 134 //      Macv8139b       = 0x78000000,
 135 //      Macv8130        = 0x7C000000,
 136 //      Macv8139c       = 0x74000000,
 137 //      Macv8139d       = 0x74400000,
 138 //      Macv8139cplus   = 0x74800000,
 139 //      Macv8101        = 0x74c00000,
 140 //      Macv8100        = 0x78800000,
 141 //      Macv8169_8110sbl= 0x7cc00000,
 142 //      Macv8169_8110sce= 0x98000000,
 143         Ifg0            = 0x01000000,   /* Interframe Gap 0 */
 144         Ifg1            = 0x02000000,   /* Interframe Gap 1 */
 145 };
 146
 147 enum {                                  /* Rcr */
 148         Aap             = 0x00000001,   /* Accept All Packets */
 149         Apm             = 0x00000002,   /* Accept Physical Match */
 150         Am              = 0x00000004,   /* Accept Multicast */
 151         Ab              = 0x00000008,   /* Accept Broadcast */
 152         Ar              = 0x00000010,   /* Accept Runt */
 153         Aer             = 0x00000020,   /* Accept Error */
 154         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
 155         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
 156         MrxdmaMASK      = 0x00000700,
 157         Mrxdmaunlimited = 0x00000700,
 158         RxfthSHIFT      = 13,           /* Receive Buffer Length */
 159         RxfthMASK       = 0x0000E000,
 160         Rxfth256        = 0x00008000,
 161         Rxfthnone       = 0x0000E000,
 162         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
 163         MulERINT        = 0x01000000,   /* Multiple Early Interrupt Select */
 164 };
 165
 166 enum {                                  /* Cr9346 */
 167         Eedo            = 0x01,         /* */
 168         Eedi            = 0x02,         /* */
 169         Eesk            = 0x04,         /* */
 170         Eecs            = 0x08,         /* */
 171         Eem0            = 0x40,         /* Operating Mode */
 172         Eem1            = 0x80,
 173 };
 174
 175 enum {                                  /* Phyar */
 176         DataMASK        = 0x0000FFFF,   /* 16-bit GMII/MII Register Data */
 177         DataSHIFT       = 0,
 178         RegaddrMASK     = 0x001F0000,   /* 5-bit GMII/MII Register Address */
 179         RegaddrSHIFT    = 16,
 180         Flag            = 0x80000000,   /* */
 181 };
 182
 183 enum {                                  /* Phystatus */
 184         Fd              = 0x01,         /* Full Duplex */
 185         Linksts         = 0x02,         /* Link Status */
 186         Speed10         = 0x04,         /* */
 187         Speed100        = 0x08,         /* */
 188         Speed1000       = 0x10,         /* */
 189         Rxflow          = 0x20,         /* */
 190         Txflow          = 0x40,         /* */
 191         Entbi           = 0x80,         /* */
 192 };
 193
 194 enum {                                  /* Cplusc */
 195         Init1           = 0x0001,       /* 8168 */
 196         Mulrw           = 0x0008,       /* PCI Multiple R/W Enable */
 197         Dac             = 0x0010,       /* PCI Dual Address Cycle Enable */
 198         Rxchksum        = 0x0020,       /* Receive Checksum Offload Enable */
 199         Rxvlan          = 0x0040,       /* Receive VLAN De-tagging Enable */
 200         Pktcntoff       = 0x0080,       /* 8168, 8101 */
 201         Endian          = 0x0200,       /* Endian Mode */
 202 };
 203
 204 struct D {
 205         u32int  control;
 206         u32int  vlan;
 207         u32int  addrlo;
 208         u32int  addrhi;
 209 };
 210
 211 enum {                                  /* Transmit Descriptor control */
 212         TxflMASK        = 0x0000FFFF,   /* Transmit Frame Length */
 213         TxflSHIFT       = 0,
 214         Tcps            = 0x00010000,   /* TCP Checksum Offload */
 215         Udpcs           = 0x00020000,   /* UDP Checksum Offload */
 216         Ipcs            = 0x00040000,   /* IP Checksum Offload */
 217         Lgsen           = 0x08000000,   /* TSO; WARNING: contains lark's vomit */
 218 };
 219
 220 enum {                                  /* Receive Descriptor control */
 221         RxflMASK        = 0x00001FFF,   /* Receive Frame Length */
 222         Tcpf            = 0x00004000,   /* TCP Checksum Failure */
 223         Udpf            = 0x00008000,   /* UDP Checksum Failure */
 224         Ipf             = 0x00010000,   /* IP Checksum Failure */
 225         Pid0            = 0x00020000,   /* Protocol ID0 */
 226         Pid1            = 0x00040000,   /* Protocol ID1 */
 227         Crce            = 0x00080000,   /* CRC Error */
 228         Runt            = 0x00100000,   /* Runt Packet */
 229         Res             = 0x00200000,   /* Receive Error Summary */
 230         Rwt             = 0x00400000,   /* Receive Watchdog Timer Expired */
 231         Fovf            = 0x00800000,   /* FIFO Overflow */
 232         Bovf            = 0x01000000,   /* Buffer Overflow */
 233         Bar             = 0x02000000,   /* Broadcast Address Received */
 234         Pam             = 0x04000000,   /* Physical Address Matched */
 235         Mar             = 0x08000000,   /* Multicast Address Received */
 236 };
 237
 238 enum {                                  /* General Descriptor control */
 239         Ls              = 0x10000000,   /* Last Segment Descriptor */
 240         Fs              = 0x20000000,   /* First Segment Descriptor */
 241         Eor             = 0x40000000,   /* End of Descriptor Ring */
 242         Own             = 0x80000000,   /* Ownership: belongs to hw */
 243 };
 244
 245 /*
 246  */
 247 enum {                                  /* Ring sizes  (<= 1024) */
 248         Ntd             = 1024,         /* Transmit Ring */
 249         /* at 1Gb/s, it only takes 12 ms. to fill a 1024-buffer ring */
 250         Nrd             = 1024,         /* Receive Ring */
 251         Nrb             = 4096,
 252
 253         Mtu             = ETHERMAXTU,
 254         Mps             = ROUNDUP(ETHERMAXTU+4, 128),
 255 //      Mps             = Mtu + 8 + 14, /* if(mtu>ETHERMAXTU) */
 256 };
 257
 258 struct Dtcc {
 259         u64int  txok;
 260         u64int  rxok;
 261         u64int  txer;
 262         u32int  rxer;
 263         u16int  misspkt;
 264         u16int  fae;
 265         u32int  tx1col;
 266         u32int  txmcol;
 267         u64int  rxokph;
 268         u64int  rxokbrd;
 269         u32int  rxokmu;
 270         u16int  txabt;
 271         u16int  txundrn;
 272 };
 273
 274 enum {                                          /* Variants */
 275         Rtl8100e        = (0x8136<<16)|0x10EC,  /* RTL810[01]E: pci -e */
 276         Rtl8169c        = (0x0116<<16)|0x16EC,  /* RTL8169C+ (USR997902) */
 277         Rtl8169sc       = (0x8167<<16)|0x10EC,  /* RTL8169SC */
 278         Rtl8168b        = (0x8168<<16)|0x10EC,  /* RTL8168B: pci-e */
 279         Rtl8169         = (0x8169<<16)|0x10EC,  /* RTL8169 */
 280         /*
 281          * trimslice is 10ec/8168 (8168b) Macv25 (8168D) but
 282          * compulab says 8111dl.
 283          *      oui 0x732 (aaeon) phyno 1, macv = 0x28000000 phyv = 0x0002
 284          */
 285 };
 286
 287 struct Ctlr {
 288         void*   nic;
 289         int     port;
 290         Pcidev* pcidev;
 291         Ctlr*   next;
 292         Ether*  ether;                  /* point back */
 293         int     active;
 294
 295         QLock   alock;                  /* attach */
 296         Lock    ilock;                  /* init */
 297         int     init;                   /*  */
 298
 299         int     pciv;                   /*  */
 300         int     macv;                   /* MAC version */
 301         int     phyv;                   /* PHY version */
 302         int     pcie;                   /* flag: pci-express device? */
 303
 304         uvlong  mchash;                 /* multicast hash */
 305
 306         Mii*    mii;
 307
 308 //      Lock    tlock;                  /* transmit */
 309         Rendez  trendez;
 310         D*      td;                     /* descriptor ring */
 311         Block** tb;                     /* transmit buffers */
 312         int     ntd;
 313
 314         int     tdh;                    /* head - producer index (host) */
 315         int     tdt;                    /* tail - consumer index (NIC) */
 316         int     ntdfree;
 317         int     ntq;
 318
 319         int     nrb;
 320
 321 //      Lock    rlock;                  /* receive */
 322         Rendez  rrendez;
 323         D*      rd;                     /* descriptor ring */
 324         Block** rb;                     /* receive buffers */
 325         int     nrd;
 326
 327         int     rdh;                    /* head - producer index (NIC) */
 328         int     rdt;                    /* tail - consumer index (host) */
 329         int     nrdfree;
 330
 331         Lock    reglock;
 332         int     tcr;                    /* transmit configuration register */
 333         int     rcr;                    /* receive configuration register */
 334         int     imr;
 335         int     isr;                    /* sw copy for kprocs */
 336
 337         QLock   slock;                  /* statistics */
 338         Dtcc*   dtcc;
 339         uint    txdu;
 340         uint    tcpf;
 341         uint    udpf;
 342         uint    ipf;
 343         uint    fovf;
 344         uint    ierrs;
 345         uint    rer;
 346         uint    rdu;
 347         uint    punlc;
 348         uint    fovw;
 349         uint    mcast;
 350         uint    frag;                   /* partial packets; rb was too small */
 351 };
 352
 353 static Ctlr* rtl8169ctlrhead;
 354 static Ctlr* rtl8169ctlrtail;
 355
 356 static Lock rblock;                     /* free receive Blocks */
 357 static Block* rbpool;
 358
 359 #define csr8r(c, r)     (*((uchar *) ((c)->nic)+(r)))
 360 #define csr16r(c, r)    (*((u16int *)((c)->nic)+((r)/2)))
 361 #define csr32p(c, r)    ((u32int *)  ((c)->nic)+((r)/4))
 362 #define csr32r(c, r)    (*csr32p(c, r))
 363
 364 #define csr8w(c, r, b)  (*((uchar *) ((c)->nic)+(r))     = (b), coherence())
 365 #define csr16w(c, r, w) (*((u16int *)((c)->nic)+((r)/2)) = (w), coherence())
 366 #define csr32w(c, r, v) (*csr32p(c, r) = (v), coherence())
 367
 368 static int
 369 rtl8169miimir(Mii* mii, int pa, int ra)
 370 {
 371         uint r;
 372         int timeo;
 373         Ctlr *ctlr;
 374
 375         if(pa != 1)
 376                 return -1;
 377         ctlr = mii->ctlr;
 378         r = (ra<<16) & RegaddrMASK;
 379         csr32w(ctlr, Phyar, r);
 380         delay(1);
 381         for(timeo = 0; timeo < 2000; timeo++){
 382                 if((r = csr32r(ctlr, Phyar)) & Flag)
 383                         break;
 384                 microdelay(100);
 385         }
 386         if(!(r & Flag))
 387                 return -1;
 388
 389         return (r & DataMASK)>>DataSHIFT;
 390 }
 391
 392 static int
 393 rtl8169miimiw(Mii* mii, int pa, int ra, int data)
 394 {
 395         uint r;
 396         int timeo;
 397         Ctlr *ctlr;
 398
 399         if(pa != 1)
 400                 return -1;
 401         ctlr = mii->ctlr;
 402         r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
 403         csr32w(ctlr, Phyar, r);
 404         delay(1);
 405         for(timeo = 0; timeo < 2000; timeo++){
 406                 if(!((r = csr32r(ctlr, Phyar)) & Flag))
 407                         break;
 408                 microdelay(100);
 409         }
 410         if(r & Flag)
 411                 return -1;
 412
 413         return 0;
 414 }
 415
 416 static int
 417 rtl8169mii(Ctlr* ctlr)
 418 {
 419         MiiPhy *phy;
 420
 421         /*
 422          * Link management.
 423          */
 424         if((ctlr->mii = malloc(sizeof(Mii))) == nil)
 425                 return -1;
 426         ctlr->mii->mir = rtl8169miimir;
 427         ctlr->mii->miw = rtl8169miimiw;
 428         ctlr->mii->ctlr = ctlr;
 429
 430         /*
 431          * Get rev number out of Phyidr2 so can config properly.
 432          * There's probably more special stuff for Macv0[234] needed here.
 433          */
 434         ilock(&ctlr->reglock);
 435         ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
 436         if(ctlr->macv == Macv02){
 437                 csr8w(ctlr, 0x82, 1);                           /* magic */
 438                 rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000);      /* magic */
 439         }
 440
 441         if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
 442                 iunlock(&ctlr->reglock);
 443                 free(ctlr->mii);
 444                 ctlr->mii = nil;
 445                 return -1;
 446         }
 447         print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
 448                 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
 449
 450         miiane(ctlr->mii, ~0, ~0, ~0);
 451         iunlock(&ctlr->reglock);
 452
 453         return 0;
 454 }
 455
 456 static Block*
 457 rballoc(void)
 458 {
 459         Block *bp;
 460
 461         ilock(&rblock);
 462         if((bp = rbpool) != nil){
 463                 rbpool = bp->next;
 464                 bp->next = nil;
 465         }
 466         iunlock(&rblock);
 467         return bp;
 468 }
 469
 470 static void
 471 rbfree(Block *bp)
 472 {
 473         bp->wp = bp->rp = bp->lim - Mps;
 474         bp->flag &= ~(Bipck | Budpck | Btcpck | Bpktck);
 475
 476         ilock(&rblock);
 477         bp->next = rbpool;
 478         rbpool = bp;
 479         iunlock(&rblock);
 480 }
 481
 482 static void
 483 rtl8169promiscuous(void* arg, int on)
 484 {
 485         Ether *edev;
 486         Ctlr * ctlr;
 487
 488         edev = arg;
 489         ctlr = edev->ctlr;
 490         ilock(&ctlr->ilock);
 491         ilock(&ctlr->reglock);
 492
 493         if(on)
 494                 ctlr->rcr |= Aap;
 495         else
 496                 ctlr->rcr &= ~Aap;
 497         csr32w(ctlr, Rcr, ctlr->rcr);
 498         iunlock(&ctlr->reglock);
 499         iunlock(&ctlr->ilock);
 500 }
 501
 502 enum {
 503         /* everyone else uses 0x04c11db7, but they both produce the same crc */
 504         Etherpolybe = 0x04c11db6,
 505         Bytemask = (1<<8) - 1,
 506 };
 507
 508 static ulong
 509 ethercrcbe(uchar *addr, long len)
 510 {
 511         int i, j;
 512         ulong c, crc, carry;
 513
 514         crc = ~0UL;
 515         for (i = 0; i < len; i++) {
 516                 c = addr[i];
 517                 for (j = 0; j < 8; j++) {
 518                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
 519                         crc <<= 1;
 520                         c >>= 1;
 521                         if (carry)
 522                                 crc = (crc ^ Etherpolybe) | carry;
 523                 }
 524         }
 525         return crc;
 526 }
 527
 528 static ulong
 529 swabl(ulong l)
 530 {
 531         return l>>24 | (l>>8) & (Bytemask<<8) |
 532                 (l<<8) & (Bytemask<<16) | l<<24;
 533 }
 534
 535 static void
 536 rtl8169multicast(void* ether, uchar *eaddr, int add)
 537 {
 538         Ether *edev;
 539         Ctlr *ctlr;
 540
 541         if (!add)
 542                 return; /* ok to keep receiving on old mcast addrs */
 543
 544         edev = ether;
 545         ctlr = edev->ctlr;
 546         ilock(&ctlr->ilock);
 547         ilock(&ctlr->reglock);
 548
 549         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
 550
 551         ctlr->rcr |= Am;
 552         csr32w(ctlr, Rcr, ctlr->rcr);
 553
 554         /* pci-e variants reverse the order of the hash byte registers */
 555         if (ctlr->pcie) {
 556                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
 557                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
 558         } else {
 559                 csr32w(ctlr, Mar0,   ctlr->mchash);
 560                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
 561         }
 562
 563         iunlock(&ctlr->reglock);
 564         iunlock(&ctlr->ilock);
 565 }
 566
 567 static long
 568 rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
 569 {
 570         char *p;
 571         Ctlr *ctlr;
 572         Dtcc *dtcc;
 573         int i, l, r, timeo;
 574
 575         ctlr = edev->ctlr;
 576         qlock(&ctlr->slock);
 577
 578         p = nil;
 579         if(waserror()){
 580                 qunlock(&ctlr->slock);
 581                 free(p);
 582                 nexterror();
 583         }
 584
 585         /* copy hw statistics into ctlr->dtcc */
 586         dtcc = ctlr->dtcc;
 587         allcache->invse(dtcc, sizeof *dtcc);
 588         ilock(&ctlr->reglock);
 589         csr32w(ctlr, Dtccr+4, 0);
 590         csr32w(ctlr, Dtccr, PCIWADDR(dtcc)|Cmd);        /* initiate dma? */
 591         for(timeo = 0; timeo < 1000; timeo++){
 592                 if(!(csr32r(ctlr, Dtccr) & Cmd))
 593                         break;
 594                 delay(1);
 595         }
 596         iunlock(&ctlr->reglock);
 597         if(csr32r(ctlr, Dtccr) & Cmd)
 598                 error(Eio);
 599
 600         edev->oerrs = dtcc->txer;
 601         edev->crcs = dtcc->rxer;
 602         edev->frames = dtcc->fae;
 603         edev->buffs = dtcc->misspkt;
 604         edev->overflows = ctlr->txdu + ctlr->rdu;
 605
 606         if(n == 0){
 607                 qunlock(&ctlr->slock);
 608                 poperror();
 609                 return 0;
 610         }
 611
 612         if((p = malloc(READSTR)) == nil)
 613                 error(Enomem);
 614
 615         l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
 616         l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
 617         l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
 618         l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
 619         l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
 620         l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
 621         l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
 622         l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
 623         l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
 624         l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
 625         l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
 626         l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
 627         l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
 628
 629         l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
 630         l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
 631         l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
 632         l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
 633         l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
 634         l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs);
 635         l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
 636         l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
 637         l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
 638         l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
 639
 640         l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
 641         l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
 642         l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
 643
 644         if(ctlr->mii != nil && ctlr->mii->curphy != nil){
 645                 l += snprint(p+l, READSTR, "phy:   ");
 646                 for(i = 0; i < NMiiPhyr; i++){
 647                         if(i && ((i & 0x07) == 0))
 648                                 l += snprint(p+l, READSTR-l, "\n       ");
 649                         r = miimir(ctlr->mii, i);
 650                         l += snprint(p+l, READSTR-l, " %4.4ux", r);
 651                 }
 652                 snprint(p+l, READSTR-l, "\n");
 653         }
 654
 655         n = readstr(offset, a, n, p);
 656
 657         qunlock(&ctlr->slock);
 658         poperror();
 659         free(p);
 660
 661         return n;
 662 }
 663
 664 static void
 665 rtl8169halt(Ctlr* ctlr)
 666 {
 667         ilock(&ctlr->reglock);
 668         csr32w(ctlr, Timerint, 0);
 669         csr8w(ctlr, Cr, 0);
 670         csr16w(ctlr, Imr, 0);
 671         csr16w(ctlr, Isr, ~0);
 672         iunlock(&ctlr->reglock);
 673 }
 674
 675 static int
 676 rtl8169reset(Ctlr* ctlr)
 677 {
 678         u32int r;
 679         int timeo;
 680
 681         /*
 682          * Soft reset the controller.
 683          */
 684         ilock(&ctlr->reglock);
 685         csr8w(ctlr, Cr, Rst);
 686         for(r = timeo = 0; timeo < 1000; timeo++){
 687                 r = csr8r(ctlr, Cr);
 688                 if(!(r & Rst))
 689                         break;
 690                 delay(1);
 691         }
 692         iunlock(&ctlr->reglock);
 693
 694         rtl8169halt(ctlr);
 695
 696         if(r & Rst)
 697                 return -1;
 698         return 0;
 699 }
 700
 701 static void
 702 rtl8169shutdown(Ether *ether)
 703 {
 704         rtl8169reset(ether->ctlr);
 705 }
 706
 707 static int
 708 rtl8169replenish(Ether *edev)
 709 {
 710         int rdt;
 711         Block *bp;
 712         Ctlr *ctlr;
 713         D *d;
 714
 715         ctlr = edev->ctlr;
 716         if (ctlr->nrd == 0) {
 717                 iprint("rtl8169replenish: not yet initialised\n");
 718                 return -1;
 719         }
 720         rdt = ctlr->rdt;
 721         assert(ctlr->rb);
 722         assert(ctlr->rd);
 723         while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
 724                 d = &ctlr->rd[rdt];
 725                 if (d == nil)
 726                         panic("rtl8169replenish: nil ctlr->rd[%d]", rdt);
 727                 if (d->control & Own) { /* ctlr owns it? shouldn't happen */
 728                         iprint("replenish: descriptor owned by hw\n");
 729                         break;
 730                 }
 731                 if(ctlr->rb[rdt] == nil){
 732                         bp = rballoc();
 733                         if(bp == nil){
 734                                 iprint("rtl8169: no available buffers\n");
 735                                 break;
 736                         }
 737                         ctlr->rb[rdt] = bp;
 738                         d->addrhi = 0;
 739                         coherence();
 740                         d->addrlo = PCIWADDR(bp->rp);
 741                         coherence();
 742                 } else
 743                         iprint("8169: replenish: rx overrun\n");
 744                 d->control = (d->control & ~RxflMASK) | Mps | Own;
 745                 coherence();
 746
 747                 rdt = NEXT(rdt, ctlr->nrd);
 748                 ctlr->nrdfree++;
 749         }
 750         ctlr->rdt = rdt;
 751         coherence();
 752         return 0;
 753 }
 754
 755 static void
 756 ckrderrs(Ctlr *ctlr, Block *bp, ulong control)
 757 {
 758         if(control & Fovf)
 759                 ctlr->fovf++;
 760         if(control & Mar)
 761                 ctlr->mcast++;
 762
 763         switch(control & (Pid1|Pid0)){
 764         case Pid0:
 765                 if(control & Tcpf){
 766                         iprint("8169: bad tcp checksum\n");
 767                         ctlr->tcpf++;
 768                         break;
 769                 }
 770                 bp->flag |= Btcpck;
 771                 break;
 772         case Pid1:
 773                 if(control & Udpf){
 774                         iprint("8169: bad udp checksum\n");
 775                         ctlr->udpf++;
 776                         break;
 777                 }
 778                 bp->flag |= Budpck;
 779                 break;
 780         case Pid1|Pid0:
 781                 if(control & Ipf){
 782                         iprint("8169: bad ip checksum\n");
 783                         ctlr->ipf++;
 784                         break;
 785                 }
 786                 bp->flag |= Bipck;
 787                 break;
 788         }
 789 }
 790
 791 static void
 792 badpkt(Ether *edev, int rdh, ulong control)
 793 {
 794         Ctlr *ctlr;
 795
 796         ctlr = edev->ctlr;
 797         /* Res is only valid if Fs is set */
 798         if(control & Res)
 799                 iprint("8169: rcv error; d->control %#.8lux\n", control);
 800         else if (control == 0) {                /* buggered? */
 801                 if (edev->link)
 802                         iprint("8169: rcv: d->control==0 (wtf?)\n");
 803         } else {
 804                 ctlr->frag++;
 805                 iprint("8169: rcv'd frag; d->control %#.8lux\n", control);
 806         }
 807         if (ctlr->rb[rdh])
 808                 freeb(ctlr->rb[rdh]);
 809 }
 810
 811 void
 812 qpkt(Ether *edev, int rdh, ulong control)
 813 {
 814         int len;
 815         Block *bp;
 816         Ctlr *ctlr;
 817
 818         ctlr = edev->ctlr;
 819         len = (control & RxflMASK) - 4;
 820         if ((uint)len > Mps)
 821                 if (len < 0)
 822                         panic("8169: received pkt non-existent");
 823                 else if (len > Mps)
 824                         panic("8169: received pkt too big");
 825         bp = ctlr->rb[rdh];
 826         bp->wp = bp->rp + len;
 827         bp->next = nil;
 828
 829         allcache->invse(bp->rp, len);   /* clear any stale cached packet */
 830         ckrderrs(ctlr, bp, control);
 831         etheriq(edev, bp);
 832
 833         if(Debug > 1)
 834                 iprint("R%d ", len);
 835 }
 836
 837 static int
 838 pktstoread(void* v)
 839 {
 840         Ctlr *ctlr = v;
 841
 842         return ctlr->isr & (Fovw|Rdu|Rer|Rok) &&
 843                 !(ctlr->rd[ctlr->rdh].control & Own);
 844 }
 845
 846 static void
 847 rproc(void* arg)
 848 {
 849         int rdh;
 850         ulong control;
 851         Ctlr *ctlr;
 852         D *rd;
 853         Ether *edev;
 854
 855         edev = arg;
 856         ctlr = edev->ctlr;
 857         while(waserror())
 858                 ;
 859         for(;;){
 860                 /* wait for next interrupt */
 861                 ilock(&ctlr->reglock);
 862                 ctlr->imr |= Fovw|Rdu|Rer|Rok;
 863                 csr16w(ctlr, Imr, ctlr->imr);
 864                 iunlock(&ctlr->reglock);
 865
 866                 sleep(&ctlr->rrendez, pktstoread, ctlr);
 867
 868                 /* clear saved isr bits */
 869                 ilock(&ctlr->reglock);
 870                 ctlr->isr &= ~(Fovw|Rdu|Rer|Rok);
 871                 iunlock(&ctlr->reglock);
 872
 873                 rdh = ctlr->rdh;
 874                 for (rd = &ctlr->rd[rdh]; !(rd->control & Own);
 875                      rd = &ctlr->rd[rdh]){
 876                         control = rd->control;
 877                         if((control & (Fs|Ls|Res)) == (Fs|Ls))
 878                                 qpkt(edev, rdh, control);
 879                         else
 880                                 badpkt(edev, rdh, control);
 881                         ctlr->rb[rdh] = nil;
 882                         coherence();
 883                         rd->control &= Eor;
 884                         coherence();
 885
 886                         ctlr->nrdfree--;
 887                         rdh = NEXT(rdh, ctlr->nrd);
 888                         if(ctlr->nrdfree < ctlr->nrd/2) {
 889                                 /* replenish reads ctlr->rdh */
 890                                 ctlr->rdh = rdh;
 891                                 rtl8169replenish(edev);
 892                                 /* if replenish called restart, rdh is reset */
 893                                 rdh = ctlr->rdh;
 894                         }
 895                 }
 896                 ctlr->rdh = rdh;
 897         }
 898 }
 899
 900 static int
 901 pktstosend(void* v)
 902 {
 903         Ether *edev = v;
 904         Ctlr *ctlr = edev->ctlr;
 905
 906         return ctlr->isr & (Ter|Tok) &&
 907                 !(ctlr->td[ctlr->tdh].control & Own) && edev->link;
 908 }
 909
 910 static void
 911 tproc(void* arg)
 912 {
 913         int x, len;
 914         Block *bp;
 915         Ctlr *ctlr;
 916         D *d;
 917         Ether *edev;
 918
 919         edev = arg;
 920         ctlr = edev->ctlr;
 921         for(;;){
 922                 /* wait for next interrupt */
 923                 ilock(&ctlr->reglock);
 924                 ctlr->imr |= Ter|Tok;
 925                 csr16w(ctlr, Imr, ctlr->imr);
 926                 iunlock(&ctlr->reglock);
 927
 928                 sleep(&ctlr->trendez, pktstosend, edev);
 929
 930                 /* clear saved isr bits */
 931                 ilock(&ctlr->reglock);
 932                 ctlr->isr &= ~(Ter|Tok);
 933                 iunlock(&ctlr->reglock);
 934
 935                 /* reclaim transmitted Blocks */
 936                 for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
 937                         d = &ctlr->td[x];
 938                         if(d == nil || d->control & Own)
 939                                 break;
 940
 941                         /*
 942                          * Free it up.
 943                          * Need to clean the descriptor here? Not really.
 944                          * Simple freeb for now (no chain and freeblist).
 945                          * Use ntq count for now.
 946                          */
 947                         freeb(ctlr->tb[x]);
 948                         ctlr->tb[x] = nil;
 949                         d->control &= Eor;
 950                         coherence();
 951
 952                         ctlr->ntq--;
 953                 }
 954                 ctlr->tdh = x;
 955
 956                 if (ctlr->ntq > 0)
 957                         csr8w(ctlr, Tppoll, Npq); /* kick xmiter to keep it going */
 958                 /* copy as much of my output q as possible into output ring */
 959                 x = ctlr->tdt;
 960                 while(ctlr->ntq < (ctlr->ntd-1)){
 961                         if((bp = qget(edev->oq)) == nil)
 962                                 break;
 963
 964                         /* make sure the whole packet is in ram */
 965                         len = BLEN(bp);
 966                         allcache->wbse(bp->rp, len);
 967
 968                         d = &ctlr->td[x];
 969                         assert(d);
 970                         assert(!(d->control & Own));
 971                         d->addrhi = 0;
 972                         d->addrlo = PCIWADDR(bp->rp);
 973                         ctlr->tb[x] = bp;
 974                         coherence();
 975                         d->control = (d->control & ~TxflMASK) |
 976                                 Own | Fs | Ls | len;
 977                         coherence();
 978
 979                         if(Debug > 1)
 980                                 iprint("T%d ", len);
 981
 982                         x = NEXT(x, ctlr->ntd);
 983                         ctlr->ntq++;
 984
 985                         ctlr->tdt = x;
 986                         coherence();
 987                         csr8w(ctlr, Tppoll, Npq);       /* kick xmiter again */
 988                 }
 989                 if(x != ctlr->tdt){             /* added new packet(s)? */
 990                         ctlr->tdt = x;
 991                         coherence();
 992                         csr8w(ctlr, Tppoll, Npq);
 993                 }
 994                 else if(ctlr->ntq >= (ctlr->ntd-1))
 995                         ctlr->txdu++;
 996         }
 997 }
 998
 999 static int
1000 rtl8169init(Ether* edev)
1001 {
1002         u32int r;
1003         Ctlr *ctlr;
1004         ushort cplusc;
1005
1006         ctlr = edev->ctlr;
1007         ilock(&ctlr->ilock);
1008         rtl8169reset(ctlr);
1009
1010         ilock(&ctlr->reglock);
1011         switch(ctlr->pciv){
1012         case Rtl8169sc:
1013                 csr8w(ctlr, Cr, 0);
1014                 break;
1015         case Rtl8168b:
1016         case Rtl8169c:
1017                 /* 8168b manual says set c+ reg first, then command */
1018                 csr16w(ctlr, Cplusc, 0x2000);           /* magic */
1019                 csr8w(ctlr, Cr, 0);
1020                 break;
1021         }
1022
1023         /*
1024          * MAC Address is not settable on some (all?) chips.
1025          * Must put chip into config register write enable mode.
1026          */
1027         csr8w(ctlr, Cr9346, Eem1|Eem0);
1028
1029         /*
1030          * Transmitter.
1031          */
1032         memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
1033         ctlr->tdh = ctlr->tdt = 0;
1034         ctlr->ntq = 0;
1035         ctlr->td[ctlr->ntd-1].control = Eor;
1036
1037         /*
1038          * Receiver.
1039          * Need to do something here about the multicast filter.
1040          */
1041         memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
1042         ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
1043         ctlr->rd[ctlr->nrd-1].control = Eor;
1044
1045         rtl8169replenish(edev);
1046
1047         switch(ctlr->pciv){
1048         default:
1049                 ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Apm;
1050                 break;
1051         case Rtl8168b:
1052         case Rtl8169c:
1053                 ctlr->rcr = Rxfthnone|6<<MrxdmaSHIFT|Ab|Apm; /* DMA max 1024 */
1054                 break;
1055         }
1056
1057         /*
1058          * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
1059          * settings in Tcr/Rcr; the (1<<14) is magic.
1060          */
1061         cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
1062         switch(ctlr->pciv){
1063         case Rtl8168b:
1064         case Rtl8169c:
1065                 cplusc |= Pktcntoff | Init1;
1066                 break;
1067         }
1068         cplusc |= /*Rxchksum|*/Mulrw;
1069         switch(ctlr->macv){
1070         default:
1071                 panic("ether8169: unknown macv %#08ux for vid %#ux did %#ux",
1072                         ctlr->macv, ctlr->pcidev->vid, ctlr->pcidev->did);
1073         case Macv01:
1074                 break;
1075         case Macv02:
1076         case Macv03:
1077                 cplusc |= 1<<14;                        /* magic */
1078                 break;
1079         case Macv05:
1080                 /*
1081                  * This is interpreted from clearly bogus code
1082                  * in the manufacturer-supplied driver, it could
1083                  * be wrong. Untested.
1084                  */
1085                 r = csr8r(ctlr, Config2) & 0x07;
1086                 if(r == 0x01)                           /* 66MHz PCI */
1087                         csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */
1088                 else
1089                         csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */
1090                 pciclrmwi(ctlr->pcidev);
1091                 break;
1092         case Macv13:
1093                 /*
1094                  * This is interpreted from clearly bogus code
1095                  * in the manufacturer-supplied driver, it could
1096                  * be wrong. Untested.
1097                  */
1098                 pcicfgw8(ctlr->pcidev, 0x68, 0x00);     /* magic */
1099                 pcicfgw8(ctlr->pcidev, 0x69, 0x08);     /* magic */
1100                 break;
1101         case Macv04:
1102         case Macv07:
1103         case Macv07a:
1104         case Macv11:
1105         case Macv12:
1106         case Macv12a:
1107         case Macv14:
1108         case Macv15:
1109         case Macv25:
1110                 break;
1111         }
1112
1113         /*
1114          * Enable receiver/transmitter.
1115          * Need to do this first or some of the settings below
1116          * won't take.
1117          */
1118         switch(ctlr->pciv){
1119         default:
1120                 csr8w(ctlr, Cr, Te|Re);
1121                 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
1122                 csr32w(ctlr, Rcr, ctlr->rcr);
1123                 break;
1124         case Rtl8169sc:
1125         case Rtl8168b:
1126                 break;
1127         }
1128         ctlr->mchash = 0;
1129         csr32w(ctlr, Mar0,   0);
1130         csr32w(ctlr, Mar0+4, 0);
1131
1132         /*
1133          * Interrupts.
1134          * Disable Tdu for now, the transmit routine will tidy.
1135          * Tdu means the NIC ran out of descriptors to send (i.e., the
1136          * output ring is empty), so it doesn't really need to ever be on.
1137          *
1138          * The timer runs at the PCI(-E) clock frequency, 125MHz for PCI-E,
1139          * presumably 66MHz for PCI.  Thus the units for PCI-E controllers
1140          * (e.g., 8168) are 8ns, and only the buggy 8168 seems to need to use
1141          * timeouts to keep from stalling.
1142          */
1143         csr32w(ctlr, Tctr, 0);
1144         /* Tok makes the whole system run faster */
1145         ctlr->imr = Serr|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok;
1146         switch(ctlr->pciv){
1147         case Rtl8169sc:
1148         case Rtl8168b:
1149                 /* alleged workaround for rx fifo overflow on 8168[bd] */
1150                 ctlr->imr &= ~Rdu;
1151                 break;
1152         }
1153         csr16w(ctlr, Imr, ctlr->imr);
1154
1155         /*
1156          * Clear missed-packet counter;
1157          * clear early transmit threshold value;
1158          * set the descriptor ring base addresses;
1159          * set the maximum receive packet size;
1160          * no early-receive interrupts.
1161          *
1162          * note: the maximum rx size is a filter.  the size of the buffer
1163          * in the descriptor ring is still honored.  we will toss >Mtu
1164          * packets because they've been fragmented into multiple
1165          * rx buffers.
1166          */
1167         csr32w(ctlr, Mpc, 0);
1168         if (ctlr->pcie)
1169                 csr8w(ctlr, Mtps, Mps / 128);
1170         else
1171                 csr8w(ctlr, Etx, 0x3f);         /* max; no early transmission */
1172         csr32w(ctlr, Tnpds+4, 0);
1173         csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
1174         csr32w(ctlr, Rdsar+4, 0);
1175         csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
1176         csr16w(ctlr, Rms, 2048);                /* was Mps; see above comment */
1177         r = csr16r(ctlr, Mulint) & 0xF000;      /* no early rx interrupts */
1178         csr16w(ctlr, Mulint, r);
1179         csr16w(ctlr, Cplusc, cplusc);
1180         csr16w(ctlr, Coal, 0);
1181
1182         /*
1183          * Set configuration.
1184          */
1185         switch(ctlr->pciv){
1186         case Rtl8169sc:
1187                 csr8w(ctlr, Cr, Te|Re);
1188                 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
1189                 csr32w(ctlr, Rcr, ctlr->rcr);
1190                 break;
1191         case Rtl8168b:
1192         case Rtl8169c:
1193                 csr16w(ctlr, Cplusc, 0x2000);           /* magic */
1194                 csr8w(ctlr, Cr, Te|Re);
1195                 csr32w(ctlr, Tcr, Ifg1|Ifg0|6<<MtxdmaSHIFT); /* DMA max 1024 */
1196                 csr32w(ctlr, Rcr, ctlr->rcr);
1197                 break;
1198         }
1199         ctlr->tcr = csr32r(ctlr, Tcr);
1200         csr8w(ctlr, Cr9346, 0);
1201
1202         iunlock(&ctlr->reglock);
1203         iunlock(&ctlr->ilock);
1204
1205 //      rtl8169mii(ctlr);
1206
1207         return 0;
1208 }
1209
1210 static void
1211 rtl8169attach(Ether* edev)
1212 {
1213         int timeo, s, i;
1214         char name[KNAMELEN];
1215         Block *bp;
1216         Ctlr *ctlr;
1217
1218         ctlr = edev->ctlr;
1219         s = splhi();
1220         qlock(&ctlr->alock);
1221         if(ctlr->init || waserror()) {
1222                 qunlock(&ctlr->alock);
1223                 splx(s);
1224                 return;
1225         }
1226         ctlr->td = ucallocalign(sizeof(D)*Ntd, 256, 0);
1227         ctlr->tb = malloc(Ntd*sizeof(Block*));
1228         ctlr->ntd = Ntd;
1229
1230         ctlr->rd = ucallocalign(sizeof(D)*Nrd, 256, 0);
1231         ctlr->rb = malloc(Nrd*sizeof(Block*));
1232         ctlr->nrd = Nrd;
1233
1234         ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
1235         if(waserror()){
1236                 free(ctlr->td);
1237                 free(ctlr->tb);
1238                 free(ctlr->rd);
1239                 free(ctlr->rb);
1240                 free(ctlr->dtcc);
1241                 nexterror();
1242         }
1243         if(ctlr->td == nil || ctlr->tb == nil || ctlr->rd == nil ||
1244            ctlr->rb == nil || ctlr->dtcc == nil)
1245                 error(Enomem);
1246
1247         /* allocate private receive-buffer pool */
1248         ctlr->nrb = Nrb;
1249         for(i = 0; i < Nrb; i++){
1250                 if((bp = allocb(Mps)) == nil)
1251                         error(Enomem);
1252                 bp->free = rbfree;
1253                 freeb(bp);
1254         }
1255
1256         rtl8169init(edev);
1257         ctlr->init = 1;
1258         qunlock(&ctlr->alock);
1259         splx(s);
1260         poperror();                             /* free */
1261         poperror();                             /* qunlock */
1262
1263         /* signal secondary cpus that l1 ptes are stable */
1264         l1ptstable.word = 1;
1265         allcache->wbse(&l1ptstable, sizeof l1ptstable);
1266
1267         s = spllo();
1268         /* Don't wait long for link to be ready. */
1269         for(timeo = 0; timeo < 50 && miistatus(ctlr->mii) != 0; timeo++)
1270 //              tsleep(&up->sleep, return0, 0, 100); /* fewer miistatus msgs */
1271                 delay(100);
1272
1273         while (!edev->link)
1274                 tsleep(&up->sleep, return0, 0, 10);
1275         splx(s);
1276
1277         snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
1278         kproc(name, rproc, edev);
1279
1280         snprint(name, KNAMELEN, "#l%dtproc", edev->ctlrno);
1281         kproc(name, tproc, edev);
1282 }
1283
1284 /* call with ctlr->reglock held */
1285 static void
1286 rtl8169link(Ether* edev)
1287 {
1288         uint r;
1289         int limit;
1290         Ctlr *ctlr;
1291
1292         ctlr = edev->ctlr;
1293
1294         if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
1295                 if (edev->link) {
1296                         edev->link = 0;
1297                         csr8w(ctlr, Cr, Re);
1298                         iprint("#l%d: link down\n", edev->ctlrno);
1299                 }
1300                 return;
1301         }
1302         if (edev->link == 0) {
1303                 edev->link = 1;
1304                 csr8w(ctlr, Cr, Te|Re);
1305                 iprint("#l%d: link up\n", edev->ctlrno);
1306         }
1307         limit = 256*1024;
1308         if(r & Speed10){
1309                 edev->mbps = 10;
1310                 limit = 65*1024;
1311         } else if(r & Speed100)
1312                 edev->mbps = 100;
1313         else if(r & Speed1000)
1314                 edev->mbps = 1000;
1315
1316         if(edev->oq != nil)
1317                 qsetlimit(edev->oq, limit);
1318 }
1319
1320 static void
1321 rtl8169transmit(Ether* edev)
1322 {
1323         Ctlr *ctlr;
1324
1325         ctlr = edev->ctlr;
1326         if (ctlr == nil || ctlr->ntd == 0) {
1327                 iprint("rtl8169transmit: not yet initialised\n");
1328                 return;
1329         }
1330         wakeup(&ctlr->trendez);
1331 }
1332
1333 /*
1334  * the controller has lost its mind, so reset it.
1335  * call with ctlr->reglock held.
1336  */
1337 static void
1338 restart(Ether *edev, char *why)
1339 {
1340         int i, s, del;
1341         Ctlr *ctlr;
1342         static int inrestart;
1343         static Lock rstrtlck;
1344
1345         /* keep other cpus out */
1346         s = splhi();
1347         if (inrestart) {
1348                 splx(s);
1349                 return;
1350         }
1351         ilock(&rstrtlck);
1352
1353         ctlr = edev->ctlr;
1354         if (ctlr == nil || !ctlr->init) {
1355                 iunlock(&rstrtlck);
1356                 splx(s);
1357                 return;
1358         }
1359
1360         if (Debug)
1361                 iprint("#l%d: restart due to %s\n", edev->ctlrno, why);
1362         inrestart = 1;
1363
1364         /* process any pkts in the rings */
1365         wakeup(&ctlr->rrendez);
1366         coherence();
1367         rtl8169transmit(edev);
1368         /* allow time to drain 1024-buffer ring */
1369         for (del = 0; del < 13 && ctlr->ntq > 0; del++)
1370                 delay(1);
1371
1372         iunlock(&ctlr->reglock);
1373         rtl8169reset(ctlr);
1374         /* free any remaining unprocessed input buffers */
1375         for (i = 0; i < ctlr->nrd; i++) {
1376                 freeb(ctlr->rb[i]);
1377                 ctlr->rb[i] = nil;
1378         }
1379         rtl8169init(edev);
1380         ilock(&ctlr->reglock);
1381
1382         rtl8169link(edev);
1383         rtl8169transmit(edev);          /* drain any output queue */
1384         wakeup(&ctlr->rrendez);
1385
1386         inrestart = 0;
1387
1388         iunlock(&rstrtlck);
1389         splx(s);
1390 }
1391
1392 static ulong
1393 rcvdiag(Ether *edev, ulong isr)
1394 {
1395         Ctlr *ctlr;
1396
1397         ctlr = edev->ctlr;
1398         if(!(isr & (Punlc|Rok)))
1399                 ctlr->ierrs++;
1400         if(isr & Rer)
1401                 ctlr->rer++;
1402         if(isr & Rdu)
1403                 ctlr->rdu++;
1404         if(isr & Punlc)
1405                 ctlr->punlc++;
1406         if(isr & Fovw)
1407                 ctlr->fovw++;
1408         if (isr & (Fovw|Rdu|Rer)) {
1409                 if (isr & ~(Tdu|Tok|Rok))               /* harmless */
1410                         iprint("#l%d: isr %8.8#lux\n", edev->ctlrno, isr);
1411                 restart(edev, "rcv error");
1412                 isr = ~0;
1413         }
1414         return isr;
1415 }
1416
1417 void
1418 rtl8169interrupt(Ureg*, void* arg)
1419 {
1420         Ctlr *ctlr;
1421         Ether *edev;
1422         u32int isr;
1423
1424         edev = arg;
1425         ctlr = edev->ctlr;
1426         ilock(&ctlr->reglock);
1427
1428         while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
1429                 ctlr->isr |= isr;               /* merge bits for [rt]proc */
1430                 csr16w(ctlr, Isr, isr);         /* dismiss? */
1431                 if((isr & ctlr->imr) == 0)
1432                         break;
1433                 if(isr & Fovw && ctlr->pciv == Rtl8168b) {
1434                         /*
1435                          * Fovw means we got behind; relatively common on 8168.
1436                          * this is a big hammer, but it gets things going again.
1437                          */
1438                         ctlr->fovw++;
1439                         restart(edev, "rx fifo overrun");
1440                         break;
1441                 }
1442                 if(isr & (Fovw|Punlc|Rdu|Rer|Rok)) {
1443                         ctlr->imr &= ~(Fovw|Rdu|Rer|Rok);
1444                         csr16w(ctlr, Imr, ctlr->imr);
1445                         wakeup(&ctlr->rrendez);
1446
1447                         if (isr & (Fovw|Punlc|Rdu|Rer)) {
1448                                 isr = rcvdiag(edev, isr);
1449                                 if (isr == ~0)
1450                                         break;          /* restarted */
1451                         }
1452                         isr &= ~(Fovw|Rdu|Rer|Rok);
1453                 }
1454                 if(isr & (Ter|Tok)){
1455                         ctlr->imr &= ~(Ter|Tok);
1456                         csr16w(ctlr, Imr, ctlr->imr);
1457                         wakeup(&ctlr->trendez);
1458
1459                         if (isr & Ter)
1460                                 iprint("xmit err; isr %8.8#ux\n", isr);
1461                         isr &= ~(Ter|Tok);
1462                 }
1463
1464                 if(isr & Punlc){
1465                         rtl8169link(edev);
1466                         isr &= ~Punlc;
1467                 }
1468
1469                 /*
1470                  * Some of the reserved bits get set sometimes...
1471                  */
1472                 if(isr & (Serr|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
1473                         panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux",
1474                                 csr16r(ctlr, Imr), isr);
1475         }
1476         if (edev->link && ctlr->ntq > 0)
1477                 csr8w(ctlr, Tppoll, Npq); /* kick xmiter to keep it going */
1478         iunlock(&ctlr->reglock);
1479         /*
1480          * extinguish pci-e controller interrupt source.
1481          * should be done more cleanly.
1482          */
1483         if (ctlr->pcie)
1484                 pcieintrdone();
1485 }
1486
1487 int
1488 vetmacv(Ctlr *ctlr, uint *macv)
1489 {
1490         *macv = csr32r(ctlr, Tcr) & HwveridMASK;
1491         switch(*macv){
1492         default:
1493                 return -1;
1494         case Macv01:
1495         case Macv02:
1496         case Macv03:
1497         case Macv04:
1498         case Macv05:
1499         case Macv07:
1500         case Macv07a:
1501         case Macv11:
1502         case Macv12:
1503         case Macv12a:
1504         case Macv13:
1505         case Macv14:
1506         case Macv15:
1507         case Macv25:
1508                 break;
1509         }
1510         return 0;
1511 }
1512
1513 static void
1514 rtl8169pci(void)
1515 {
1516         Pcidev *p;
1517         Ctlr *ctlr;
1518         int i, pcie;
1519         uint macv, bar;
1520         void *mem;
1521
1522         p = nil;
1523         while(p = pcimatch(p, 0, 0)){
1524                 if(p->ccrb != 0x02 || p->ccru != 0)
1525                         continue;
1526
1527                 pcie = 0;
1528                 switch(i = ((p->did<<16)|p->vid)){
1529                 default:
1530                         continue;
1531                 case Rtl8100e:                  /* RTL810[01]E ? */
1532                 case Rtl8168b:                  /* RTL8168B */
1533                         pcie = 1;
1534                         break;
1535                 case Rtl8169c:                  /* RTL8169C */
1536                 case Rtl8169sc:                 /* RTL8169SC */
1537                 case Rtl8169:                   /* RTL8169 */
1538                         break;
1539                 case (0xC107<<16)|0x1259:       /* Corega CG-LAPCIGT */
1540                         i = Rtl8169;
1541                         break;
1542                 }
1543
1544                 bar = p->mem[2].bar & ~0x0F;
1545                 assert(bar != 0);
1546                 assert(!(p->mem[2].bar & Barioaddr));
1547                 if(0) iprint("rtl8169: %d-bit register accesses\n",
1548                         ((p->mem[2].bar >> Barwidthshift) & Barwidthmask) ==
1549                          Barwidth32? 32: 64);
1550                 mem = (void *)bar;      /* don't need to vmap on trimslice */
1551                 if(mem == 0){
1552                         print("rtl8169: can't map %#ux\n", bar);
1553                         continue;
1554                 }
1555                 ctlr = malloc(sizeof(Ctlr));
1556                 if(ctlr == nil)
1557                         error(Enomem);
1558                 ctlr->nic = mem;
1559                 ctlr->port = bar;
1560                 ctlr->pcidev = p;
1561                 ctlr->pciv = i;
1562                 ctlr->pcie = pcie;
1563
1564                 if(vetmacv(ctlr, &macv) == -1){
1565                         free(ctlr);
1566                         print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
1567                         continue;
1568                 }
1569
1570                 pcienable(p);
1571
1572                 if(rtl8169reset(ctlr)){
1573                         free(ctlr);
1574                         continue;
1575                 }
1576
1577                 /*
1578                  * Extract the chip hardware version,
1579                  * needed to configure each properly.
1580                  */
1581                 ctlr->macv = macv;
1582
1583                 rtl8169mii(ctlr);
1584                 pcisetbme(p);
1585
1586                 if(rtl8169ctlrhead != nil)
1587                         rtl8169ctlrtail->next = ctlr;
1588                 else
1589                         rtl8169ctlrhead = ctlr;
1590                 rtl8169ctlrtail = ctlr;
1591         }
1592 }
1593
1594 static int
1595 rtl8169pnp(Ether* edev)
1596 {
1597         u32int r;
1598         Ctlr *ctlr;
1599         uchar ea[Eaddrlen];
1600         static int once;
1601
1602         if(once == 0){
1603                 once = 1;
1604                 rtl8169pci();
1605         }
1606
1607         /*
1608          * Any adapter matches if no edev->port is supplied,
1609          * otherwise the ports must match.
1610          */
1611         for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
1612                 if(ctlr->active)
1613                         continue;
1614                 if(edev->port == 0 || edev->port == ctlr->port){
1615                         ctlr->active = 1;
1616                         break;
1617                 }
1618         }
1619         if(ctlr == nil)
1620                 return -1;
1621
1622         edev->ctlr = ctlr;
1623         ctlr->ether = edev;
1624         edev->port = ctlr->port;
1625 //      edev->irq = ctlr->pcidev->intl; /* incorrect on trimslice */
1626         edev->irq = Pcieirq;            /* trimslice: non-msi pci-e intr */
1627         edev->tbdf = ctlr->pcidev->tbdf;
1628         edev->mbps = 1000;
1629         edev->maxmtu = Mtu;
1630
1631         /*
1632          * Check if the adapter's station address is to be overridden.
1633          * If not, read it from the device and set in edev->ea.
1634          */
1635         memset(ea, 0, Eaddrlen);
1636         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1637                 r = csr32r(ctlr, Idr0);
1638                 edev->ea[0] = r;
1639                 edev->ea[1] = r>>8;
1640                 edev->ea[2] = r>>16;
1641                 edev->ea[3] = r>>24;
1642                 r = csr32r(ctlr, Idr0+4);
1643                 edev->ea[4] = r;
1644                 edev->ea[5] = r>>8;
1645         }
1646
1647         edev->attach = rtl8169attach;
1648         edev->transmit = rtl8169transmit;
1649         edev->ifstat = rtl8169ifstat;
1650
1651         edev->arg = edev;
1652         edev->promiscuous = rtl8169promiscuous;
1653         edev->multicast = rtl8169multicast;
1654         edev->shutdown = rtl8169shutdown;
1655
1656         ilock(&ctlr->reglock);
1657         rtl8169link(edev);
1658         iunlock(&ctlr->reglock);
1659
1660         intrenable(edev->irq, rtl8169interrupt, edev, 0, edev->name);
1661
1662         return 0;
1663 }
1664
1665 void
1666 ether8169link(void)
1667 {
1668         addethercard("rtl8169", rtl8169pnp);
1669 }