2 * tegra 2 SoC clocks; excludes cortex-a timers.
4 * SoC provides these shared clocks:
5 * 4 29-bit count-down `timers' @ 1MHz,
6 * 1 32-bit count-up time-stamp counter @ 1MHz,
7 * and a real-time clock @ 32KHz.
8 * the tegra watchdog (tegra 2 ref man §5.4.1) is tied to timers, not rtc.
11 #include "../port/lib.h"
17 typedef struct Shrdtmr Shrdtmr;
18 typedef struct µscnt µscnt;
20 /* tegra2 shared-intr timer registers */
21 struct Shrdtmr { /* 29-bit count-down timer (4); unused */
37 struct µscnt { /* tegra2 shared 32-bit count-up µs counter (1) */
40 * oscillator clock fraction - 1; initially 0xb (11) from u-boot
41 * for 12MHz periphclk.
44 uchar _pad0[0x3c - 0x8];
51 Dividendmask = MASK(8),
53 Divisormask = MASK(8),
62 /* appease the tegra dog */
63 tmr = (Shrdtmr *)soc.tmr[0];
69 * if on cpu0, shutdown the shared tegra2 watchdog timer.
72 tegclockshutdown(void)
77 tmr = (Shrdtmr *)soc.tmr[0];
78 tmr->prescnt = tmr->trigger = 0;
84 tegwdogintr(Ureg *, void *v)
90 tmr->prescnt |= Intrclr;
92 /* the lousy documentation says we also have to read trigger */
97 /* start tegra2 shared watch dog */
103 tmr = (Shrdtmr *)soc.tmr[0];
104 irqenable(Tn0irq, tegwdogintr, tmr, "tegra watchdog");
107 * tegra watchdog only fires on the second missed interrupt, thus /2.
109 tmr->trigger = (Dogsectimeout * Mhz / 2 - 1) | Periodintr | Enable;
114 * µscnt is a freerunning timer (cycle counter); it needs no
115 * initialisation, wraps and does not dispatch interrupts.
121 µscnt *µs = (µscnt *)soc.µs;
123 /* verify µs counter sanity */
124 assert(µs->cfg == 0xb); /* set by u-boot */
127 assert(old != µs->cntr);
131 perfticks(void) /* MHz rate, assumed by timing loops */
135 /* keep it non-zero to prevent m->fastclock ever going to zero. */
136 v = ((µscnt *)soc.µs)->cntr;